Accelerated simulation and verification of a system under test (SUT) using cache and replacement management tables

[0001] 1. Technical Field

[0002] The present invention relates generally to microprocessor systems and in particular to the testing of microprocessor systems. Still more particularly, the present invention relates to the testing of microprocessor systems in an accelerated simulation environment using cache and replacement management tables.

[0003] 2. Description of the Related Art

[0004] With the increasing complexity of microprocessor designs, a parallel increase in the resources devoted to verifying a design's correctness has also been made. The number of potential logic combinations on a microprocessor has far exceeded the number of atoms in the universe, and thus, ensuring the validity of a microprocessor's design is truly a Herculean task. Numerous methodologies are employed to tackle this seemingly insurmountable problem. One of the primary methods is cycle simulation. Cycle simulation uses a software model of a hardware design to simulate the cycle by cycle state transitions of a synchronous design. The current state of the art cycle simulators are able to simulate tens or possibly hundreds of cycles per second, which corresponds to several minutes of microprocessor operations. Thus, even using contemporary cycle simulators, the number of cycles that one can hope to simulate before fabrication only corresponds to a minimal period (i.e., the several minutes) of actual microprocessor operation. Because of finite resources, the state space one is able to cover with cycle simulation is limited.

[0005] To improve the coverage provided by cycle simulation, formal verification is also frequently employed. Formal verification proves mathematically that the hardware design is functioning as intended. While formal verification is extremely effective, this method requires significant resources to support, and not all parts of a design are practical to verify using this methodology. Typically, only small parts of a design can be verified formally because designs are often too big or too complex to fully employ formal verification.

[0006] Accelerated simulation is yet another methodology with its own pros and cons used to verify a microprocessor's validity. Accelerated simulation refers to the process of mapping the synthesizable portion of the design into a hardware platform to increase performance by evaluating the high definition language (HDL) constructs in parallel. The method does not map the remaining portions of the simulation into hardware but runs them in a software simulator. The software simulator works with the hardware platform to exchange simulation data. Removing most of the simulation events from the software simulator and evaluating them in parallel improve performance. Accelerated simulation makes use of an FPGA or other hardware to drastically increase the speed of simulation. Accelerated simulation is orders of magnitude faster than cycle simulation, achieving simulation speeds of thousands or tens of thousands of cycles per second. To achieve these drastic increases in performance, accelerated simulation foregoes much of the checking used in either formal verification or cycle simulation. As a result, the checking is less thorough and failures are much harder to debug. Because of this lack of checking, additional algorithms and methods that enable a subsequent “self check” are frequently required to be executed following the accelerated simulation.

[0007] In the light of the above limitations with conventional accelerated simulation techniques, the present invention provides an improved verification methodology to extend the debugging capabilities of accelerated simulation.

[0008] In accordance with the present invention, a cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes an emulator/accelerator, a workstation, a model of the microprocessor system being tested and a CBEA (Cell Broadband Engine Architecture) compliant system implementing Replacement Management Tables (RMTs). Further, the system includes direct high-speed/high-bandwidth connections between the emulator/accelerator system, the host workstation and the CBEA-compliant (RMT-implementing) system.

[0009] Cache Replacement in a CBEA-compliant system is managed by RMTs. RMTs allow the software to direct entries with specific address ranges at a particular subset of the cache. This mechanism allows for locking data in the cache and may also be used to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. In an accelerated simulation environment, implementation of this locking mechanism results in the user's ability to lock different portions of the cache and isolate data in order to check cache data and states. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, will generate identical (and verifiable) data and cache states in each of the different sets of the cache. Thus, Replacement Management Tables improve the debugging capabilities of accelerated simulation.

[0010] The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.

[0018] The present invention provides a method and system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking using a Cell Broadband Engine Architecture (CBEA) based cache replacement management system. It should be noted that the terms “accelerated simulation” or “emulator” as used within the description of the invention may refer to: (a) a hardware emulator; (b) a simulation accelerator; (c) an emulator used as a simulation accelerator; or (d) a simulation accelerator used as an emulator.

[0019] In the CBEA-compliant system as utilized within the invention, cache management is controlled by Replacement Management Tables (RMTs). RMTs allow the software to direct entries with specific address ranges at a particular subset of the cache. This mechanism allows for locking data in the cache and is also used to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Providing these functions enables increased efficiency and increased real-time control of the processor.

[0020] In an accelerated simulation environment, implementation of this locking mechanism results in the user's ability to lock different portions of the cache and isolate data in order to check cache data and states. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, will generate identical (and verifiable) data and cache states in each of the different sets of the cache.

[0021] In the following detailed description of exemplary embodiments, specific exemplary embodiments by which the invention may be practiced are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, architectural, programmatic, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

[0022] It is also understood that the use of specific parameter names are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with different nomenclature/terminology utilized to describe the above parameters, without limitation.

[0023] Additionally, within the descriptions of the various figures, similar elements are provided similar names and reference numerals as those of the previous figure(s). Where a later figure utilizes the element in a different context or with different functionality, the element is provided a different leading numeral representative of the figure number (e.g., 2xx for FIG. 2 and 3xx for FIG. 3). The specific numerals assigned to the elements are provided solely to aid in the description and not meant to imply any limitations (structural or functional) on the invention.

[0024] With reference now to the figures, FIG. 1 depicts a Cell Broadband Engine Architecture (CBEA). FIG. 1 illustrates a CBEA-compliant processor 100 in which a group of Synergistic Processor Elements (SPEs) 110 share single SL1 cache 122 (SL1 cache 122 is a first-level cache for DMA transfers between local storage 117 and main storage) and a group of PowerPC Processor Elements (PPEs) 101 share single second-level (L2) cache 135. Also included in the illustration are two controllers typically found in a processor: Memory Interface Controller (MIC) 137 and Bus Interface Controller (BIC) 129. Connecting the various units within processor 100 is an Element Interconnect Bus (EIB) 127.

[0025] Physically, CBEA-compliant processor 100 may consist of a single chip, a multi-chip module (or modules), or multiple single-chip modules on a motherboard or other second-level package, depending on the technology used and the cost/performance characteristics of the intended design point. Logically, the CBEA defines four separate types of functional components: PowerPC Processor Element (PPE) 101, Synergistic Processor Unit (SPU) 112, Memory Flow Controller (MFC) 114 and Internal Interrupt Controller (IIC) 139. The computational units in the CBEA-compliant processor are PPE 101 and SPU 112. Each SPU 112 has dedicated local storage 117, dedicated MFC 114 with its associated Memory Management Unit (MMU) 120 which can hold and process memory-protection and access-permission information, and its Replacement Management Table (RMT). The combination of these components is referred to as a SPU Element, or SPE 110.

[0026] A processor may include multiple groups of PPEs (PPE groups) and multiple groups of SPEs (SPE groups). Hardware resources may be shared between units within a group. However, the SPEs 110 and PPEs 101 appear as independent elements to the configuring software.

[0027] According to the described embodiment, the CBEA-compliant system comprises the following components:

• • [0028] 1. One or more PowerPC Processor Elements (PPEs)
  • [0029] 2. One or more Synergistic Processor Elements (SPEs), which are the combination of a Synergistic Processor Units (SPUs), a local storage area, and a Memory Flow Controller (MFC)
  • [0030] 3. One Internal Interrupt Controller (IIC) and
  • [0031] 4. One Element Interconnect Bus (EIB) for connecting units within the processor.

[0032] Referring now to FIG. 2, there is depicted a block diagram representation of an emulator/accelerator environment 200 which includes workstation 210 executing sequential operations model 220, emulator/accelerator 215 executing concurrent operations model 230, and target hardware 235. Workstation 210 is coupled to emulator/accelerator 215 via communication link 225. In addition, emulator/accelerator environment 200 includes high speed/high bandwidth communication link 240, linking emulator/accelerator 215 with target hardware 235 and optional feed-back link 245, linking target hardware 235 with workstation 210. Emulator/accelerator 215 is a large-scale hardware configuration implemented with Field Programmable Gate Arrays (FPGAs) or some other type of custom hardware. Emulator/accelerator 215 is capable of emulating many different types of computer system hardware components including, for example, memory devices. Emulator/accelerator 215 is capable of modeling concurrent operations such as concurrent operations model 230. Since emulator/accelerator 215 is designed to operate under the control of workstation 210, sequential operations model 220 and concurrent operations model 230 may operate in parallel (at the same time).

[0033] Target hardware system 235 includes any hardware that needs to be tested, whether the hardware is a portion of an integrated circuit, an entire integrated circuit, or multiple integrated circuits. Target hardware system 235 may be a part of a system under test and can represent any system or portion of a system that needs to be tested. One example of target hardware system 235 is a personal computer with the microprocessor removed. Also, a prototype microprocessor may be modeled using emulator/accelerator 215 and attached to target hardware system 235 via communication link 240. In this embodiment, communication link 240 consists of several interface cables and adapter pods. Target hardware system 235 is then exercised and tested for compliance with design parameters and specifications.

[0034] Workstation 210 may be any type of microprocessor-based computer or computer system known to those skilled in the art. Workstation 210 typically provides test data (such as test vectors) to emulator/accelerator 215 or target hardware system 235, which then performs the desired tests. Results of the test may be returned to workstation 210 via optional feedback link 245 or may be passed via communication link 240 to emulator/accelerator 215 and then to workstation 210 via communication link 225.

[0035] Communication link 225 is usually implemented with memory components (not shown) located within workstation 210. Software-based simulation systems typically have the ability to create models that can represent either concurrent or sequential operations. Concurrent modeling refers to a description of operational behavior which is designed to represent actual hardware logic components, where many events occur in parallel or at the same time. Each of these events will typically represent the transfer of information from one internal system register or memory location to another. Sequential modeling, on the other hand, is used to simulate operations or events which happen only one at a time in a serial fashion. With sequential modeling, the flow of events progresses from one to another in a sequence or series of steps.

[0036] In the described embodiment of the present invention, target system 235 is a CBEA-compliant processor system 100 with a 4-way set associative cache memory system employing Remote Management Tables (RMTs) (as illustrated by FIG. 5). In an alternate embodiment of the present invention, a CBEA-compliant processor system with a 4-way set associative cache memory system employing RMTs may have its concurrent operations modeled by emulator/accelerator 215, its sequential operations modeled by the workstation 210 with Target System 235 representing, if any, only some portion of the CBEA-compliant system.

[0037] Important considerations for determining cache performance are the organization of the cache and the cache management policies that are employed in the cache. In general, a cache can be organized into either a direct-mapped or set-associative configuration. In a direct-mapped configuration, the physical address space of the computer is conceptually divided into a number of equal pages, with the page size equaling the size of the cache.

[0038] A set-associative cache includes a number of banks, or ways, of memory that are each equivalent in size to a conceptual page defined in main memory. Accordingly, a page offset in main memory can be mapped to a number of locations in the cache equal to the number of ways in the cache. For example, in a four-way set-associative cache, a line or page offset from main memory can reside in the equivalent page offset location in any of the four ways of the cache. Additionally, each of the ways in a multiple way cache is partitioned into a number of sets each having a certain number of lines. In addition, a set-associative cache usually includes a cache replacement algorithm such as a Least Recently Used (LRU) algorithm, which determines which bank or way with which to fill data when a read miss occurs. “Cache replacement” as referred to herein relates to a process of replacement of data stored in a cache memory array with other data.

[0039] In the Cell Broadband Engine Architecture (CBEA), the management of cache replacement is controlled by Replacement Management Tables (RMTs) which allow software to direct entries with specific address ranges at a particular subset of the cache. As an example, a 2-way set associative cache mapping methodology is illustrated in FIG. 3. In FIG. 3, an example of the described embodiment, cache mapping structure 300, which is a 2-way set associative cache mapping methodology using RMTs, is illustrated. In cache mapping structure 300, address entries 302-304, which reside in main memory 301, are mapped using RMTs to cache locations 309-311 in 2-way set associative cache 305 comprising Way 0 307 and Way 1 308.

[0040] CBEA-based RMTs also allow for locking data in the cache and may also be used to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets that, when the microprocessor system being tested is correctly designed, will generate identical (and verifiable) data and cache states in each of the different sets of the cache. Specifically, a user is able to modify the address range of the load and store operations in the code sequence so that they fall into different partitions in the cache. Providing these functions enables increased efficiency and increased real-time control of the processor.

[0041] The Cell Broadband Engine Architecture (CBEA) provides a method of controlling the cache replacement based on a replacement class identifier (RClassID). The class ID is provided as a parameter in the Memory Flow Controller (MFC) instructions and is generated from the load-and-store address for PowerPC Processor Element (PPE) operations. The class ID is used to generate an index to a privileged-software managed table, which is used to control the replacement policy.

[0042] The format of the Replacement Management Table (RMT) is implementation-dependent. Any CBEA-compliant implementation provides an RMT for each major cache structure. FIG. 4 depicts a typical RMT entry for an 8-way, set-associative cache. The cache replacement is controlled by privileged software through a Relay Module (RM). Each level of cache has an independent RMT. The RMT consists of an implementation-dependent number of entries, which contain set-enable bits 401, valid bit 407, and other control information. Optionally, an implementation may also provide cache bypass bit 405 and algorithm bit 403. The number of entries and the size of each entry in the RMT table are implementation-dependent.

[0043] The RMT table is located in the real address space of the system memory. The RMT defines which sets in the set-associative cache are to be used for the respective replacement management class. If the value of the set-enable bit for the respective set is ‘1’, that set is used by that replacement class in the RMT entry. If the set-enable bit is not set (i.e., value equal to “0”), the associated set is not used for operations involving the respective replacement management class. One or more sets can be used for more than one replacement management class.

[0044] Using the replacement management policies described in the CBEA, code streams may be “locked” into different cache sets. After code streams that are expected to produce identical output to a cache set are executed under separate RMTs in an accelerated simulation, the results are systematically verified by comparing each stream's cache set to a cache set that had been output from a parallel code stream. The test fails if there is any variation in cache data or state. Set associative caches without a locking feature are not able to gain benefit from this accelerated simulation algorithm because the hardware replacement algorithm can not guarantee the code streams will not overwrite each other's cache data and states. A 4-way set associative cache with RMTs is illustrated in FIG. 5.

[0045] In a preferred embodiment of the present invention, design verification for which the cache locking and data isolation features of RMTs are exploited, is accomplished by following the steps as outlined in FIG. 6 which illustrates the Process for Accelerated Simulation and Improved Verification 600. Initially, the Accelerated Simulation environment is set up, as shown in block 601. Then at block 603, a simulation run takes place under the control of workstation 210. Following, as indicated at block 605, a results check is carried out. The results check is completed by comparing parallel streams of data in pre-determined cache locations, as the user searches for any variation. In the embodiment which utilizes a four-way set associative cache with RMTs, each of the different Ways 501-504 of the cache contains a separate code stream (A, B, C, and D, respectively) output region. According to this 4-way set associative cache embodiment, when a four-way system is used to generate four output regions, the correctness of these regions will be checked in the following way. First check Way 0 501 with Ways 1, 2, 3 502-504, and if they all match, then the test has passed.

[0046] Returning to the process, a determination of whether the results check passes is made at block 607. If the test passed, each of these regions would contain identical results after the code stream execution is complete. The identical results indicate that the system under test is functioning properly and/or meets the design requirements, and the accelerated simulation of the particular design is complete, as depicted at block 609. However, if the test fails, the simulation produces an error report of the miscompares and generates a log fault report, as shown at block 611.

[0047] When the test fails, one or more of the Ways of the cache will be different to the other regions. If any of the Ways miscompare, then a detailed report of the miscompares is produced, in one embodiment, by examining all of the Ways with all of the other Ways to produce a precise signature of the miscompare. Results are fed back to the host system or workstation 210, which flags the error, and a failure report is generated and logged.

[0048] As FIGS. 1-6 illustrate, with the corresponding descriptions above, Replacement Management Tables provide a very flexible and powerful tool that extends the capabilities of accelerated simulation. Accelerated simulation is generally known for its drastic performance increase over other simulation methods. However, performance is increased at the expense of less checking and great difficulty in debugging failures. Fortunately, Replacement Management Tables provide a mechanism for locking data in the cache and a way to prevent overwriting data in the cache. In an accelerated simulation environment, implementation of this mechanism results in the user's ability to lock different portions of the cache and isolate data in order to check cache data and states. The above described embodiments of the invention allows accelerated simulation to improve its debugging capabilities and achieve more complete verification by way of more thorough data checking.

[0049] Those of ordinary skill in the art will appreciate that the emulator/accelerator environment 200 may vary. For example, the operational and control functions normally under the direction of workstation 210 may be programmed into a behavior card. Thus the behavior card becomes one embodiment of a sequential control system in accordance with the present invention. In such embodiment, Workstation 210 transfers the instructions necessary to run the desired simulation into the behavior card. It should be noted that other types of program sources are contemplated and are within the scope of the present invention. For example, an Erasable Programmable Read Only Memory (EPROM) might be used to provide the instructions for the behavior card. Alternatively, a Direct Access Storage Device (DASD) may be used as a program source. Basically, any type of connection or system, internal or external to the behavior card that may be used to provide the necessary data or instructions may be considered a program source. Thus, the depicted example is not meant to imply architectural limitations with respect to the present invention.

[0050] While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.