Integrated circuit fabrication process using gas cluster ion beam etching

[0001] The invention generally relates to the field of semiconductor fabrication, and more particularly, to an integrated fabrication process of etching and smoothing surfaces using gas cluster ion beam (GCIB) etching.

[0002] Surfaces of microelectronic materials such as semiconductors, dielectrics, and metals (often as thin films on a substrate) are generally planarized after their fabrication. The close proximity of microelectronic components, either as multiple layers or as interacting and interconnected subcomponents, requires a high degree of uniformity of the surface. Advances in semiconductor technology have seen the advent of very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits, resulting in the integration of very many more devices in smaller areas on a semiconductor substrate.

[0003] The greater device densities require greater degrees of planarity to permit the higher resolution lithographic processes required to form the greater number of devices having smaller features as incorporated in current designs. That is, as successive generations of improvements in semiconductor fabrication are implemented, the tolerance for scratches, erosion, contamination, or other imperfections in the smoothed surface becomes smaller.

[0004] One such method of planarization is by chemical mechanical polishing (CMP). CMP, though, is limited because the physical polish often generates scratches, erosion, or other surface defects on the wafer surface. Additionally, the polish rate depends upon the pattern density factor; thus the longer the polish, the worse the uniformity. This non-uniformity of the surface is not within the acceptable tolerances for processing the very thin wire levels of emerging fabrication methods. Also, for fatwire levels, a thick CMP hard mask is often required in the film stack to be sure that some hard mask remains after CMP, if desired.

[0005] FIG. 1 shows a graph of the line resistance distribution of multiple chips on twelve wafers—each chip has nested lines with widths of 2.5 μm, 6 μm, 15 μm, and 25 μm, and having 50% pattern density—formed using a conventional CMP process. Along the x-axis are the wafer IDs, and along the y-axis is the line resistance in Ohms. As will be appreciated by one skilled in the art, it is desirable to have uniformity of resistance across the wafer in order to optimize performance. The four different lines on the graph show the resistance varies considerably across each wafer.

[0006] Thus, it is desirable to achieve a more planar and smoothed surface, with extremely uniform line resistance across the wafer, even when the surface includes complex structures.

[0007] In a first aspect of the invention a method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion or GCIB etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.

[0008] In a second aspect of the invention a method comprises performing a reactive ion etch step to selectively etch a dielectric film layer to form sub-lithographic features. The method further includes depositing metal layers on the dielectric film layer and polishing at least one of the metal layers to remove excess material from a surface with recess in metal lines. The method further includes performing a gas cluster ion beam (GCIB) etch to remove an exposed portion of one of the metal layers and a hard mask layer.

[0009] In a third aspect of the invention a system, such as a device, comprises a smoothed surface with variations and roughness of less than 1 nm (nanometer) in height across the chip.

[0015] The invention is generally directed to a system and method of etching and smoothing of surfaces during semiconductor fabrication by the process of gas cluster ion beam (GCIB) etching. GCIB etching by the method of the present invention achieves a uniform planar smoothed surface (compared to conventional processes), having extremely uniform line resistance across the wafer. In comparison with existing methods of smoothing of surfaces, the inventive process is more easily controlled than, for example, reactive ion etching (RIE). Additionally, the inventive process produces a more uniform and scratch-free surface, without dependency on pattern density, than conventional chemical mechanical polishing (CMP). In particular, the method of the present invention is well suited to application on surfaces that include complex structures such as very large scale integration and ultra large scale integration. The method of the present invention may produce a smoothed surface with variations and roughness of less than 1 nm in height across the chip.

[0016] FIG. 2 is a flow diagram of an embodiment of the invention, generally denoted by reference numeral 100. The methods of the invention require one new manufacturing GCIB process step 150 but eliminate one barrier metal CMP step, but do not introduce new materials into the final build, and further avoid many of the shortcomings of existing CMP planarization processes.

[0017] Being more specific and referring to FIG. 2, in one embodiment of the invention, at step 100, an inter-level dielectric film layer is deposited on a substrate and a hard mask is deposited on the inter-level dielectric film layer. At step 110, an Anti-Reflective Coating (ARC®) layer is deposited on the hard mask layer and a block patterned photo resist layer is deposit on the ARC layer. At step 120, a reactive ion or GCIB etch step is performed to selectively etch the inter-level dielectric film layer to form sub-lithographic features. At step 130, a barrier metal layer and a copper layer 130 are deposited. At step 140, a chemical mechanical polish (CMP) is performed to remove excess copper from the surface with controlled recess in the Copper line. At step 150, a gas cluster ion beam etch step is performed to remove the exposed barrier metal layer and hard mask layer. Each of these steps is discussed herein in greater detail.

[0018] FIG. 3 is a sectional schematic view of a substrate (not to scale), generally denoted by reference to numeral 10. In FIG. 3 an inter-layer dielectric film 12 is deposited on a substrate 10. The substrate 10 may be any conventional material such as, for example, Silicon.

[0019] The inter-layer dielectric film 12 is deposited on the substrate 10 using any known method such as, for example, plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), spin-on coating or other processes. The inter-layer dielectric film 12 may be a dense or porous CVD or spin-on material with dielectric constant (K) ranging from 1.5 to 4.5, such as, for example, dense or porous Silicon Dioxide (SiO₂), Silicon Oxycarbide (SiCOH), or Methylsilsesquioxane (MSQ). The dielectric constant (K) may also range upwards to 7.5. For a high-performance chip, the inter-layer dielectric film 12 will preferably have a low dielectric constant (K), ranging from 1.5 to 2.5.

[0020] Additionally, FIG. 3 shows depositing a hard mask 14 on the inter-layer dielectric film 12. The step of depositing a hard mask 14 is not required, but may be preferable when using a very low K inter-layer dielectric film 12 in order to sustain the lithography rework. The hard mask 14 also sometimes serves as a CMP stopping layer.

[0021] Although the structure shown in FIG. 3 is a single-level structure, i.e. single level wiring layer, shown for illustrative purposes, it should be understood by those of skill in the art that the structure shown and described herein can be a multi-level structure of several layers. The methods of manufacturing described herein are equally applicable to such a multi-level structure.

[0022] In FIG. 4, an Anti-Reflective Coating (ARC®) layer 16 and a blockout patterned photo resist layer 18 are deposited. The photo resist layer 18 may be deposited in any conventional manner, and may be any conventional photo resist material. The lithography process will preferably use a wavelength and a photo resist material that is suitable for the desired line width and pitch. The photo resist layer 18 may include holes 20 or features that are larger than the minimal resolution features; that is, in one implementation, the features of the photo resist layer 18 are larger that the spacings between the interconnects.

[0023] FIG. 5 illustrates a further step, which includes performing a reactive ion etch (RIE) or GCIB etch. In this step, the etch process opens up the ARC® layer 16 and the hard mask 14, and then etches into the inter-layer dielectric film 12 to a targeted depth 28. Finally, the etch process uses photo resist strip chemistry to strip away the remaining photo resist layer 18 and any remaining ARC® layer 16.

[0024] In FIG. 6, a barrier metal layer 22 and a copper layer 24 is deposited. The barrier metal layer 22 may be, for example, Tantalum (Ta), Tantalum Nitride (TaN), or Ruthenium (Ru). The barrier metal layer 22 may be deposited by any conventional method, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The copper layer 24 may be deposited by any conventional method, as should be understood by those of skill in the art.

[0025] FIG. 7 illustrates a further step in the fabrication process of the invention. In FIG. 7, a copper CMP process is performed, leaving a recess 26. In this step, the excess copper may be removed from the surface by conventional Cu CMP means. Preferably, this polishing process will have good barrier metal/copper selectivity, such that the copper line will be recessed by about 500 Å without removing the barrier metal layer 22. Certain barrier metals such as Ruthenium (Ru) can withstand conventional copper CMP and prevent erosion of the hard mask layer 14 during the Copper CMP.

[0026] FIG. 8 is a sectional schematic view of a substrate (not to scale) in a further step of the inventive process. FIG. 8 illustrates a GCIB etching, during which the exposed barrier metal layer 22 and hard mask layer 14 are removed from the upper surface. In this invention, it has been found that the GCIB provides exceptional planarity with SiCOH and SiNCH surfaces coplanar with a complex metal sandwich of multiple components that may include Ru, Ta, TaN, and Cu. Furthermore, in the invention, there are multiple dimensional shapes, all of which create unique challenges in the polishing processes. As will be appreciated by one of skill in the art, materials having different pattern densities have different polishing rates, such that when using a CMP process, the different pattern densities and polishing rates must be taken into account. In the present invention, such differences need not be taken into account, because the GCIB etching process may be selected such that it does not etch the upper surface of the Copper in the trench. In this way, the present invention can be used to smooth the upper surface—even where that surface comprises complex geometries—in order to achieve planar uniformity to within 1 nm variations in height across the wafer. This degree of tolerance is not possible using CMP.

[0027] In the GCIB process, beams composed of clusters of gas atoms, roughly 5,000 to 20,000 atoms in each cluster, can be singly ionized, accelerated, and upon impact with a surface provide superior smoothness of the upper surface. The GCIB process has many advantages over CMP and other planarization methods in several important respects. In particular, the vacuum environment of the ion-beam apparatus provides contamination control for the work piece surface that cannot be attained with any wet or atmospheric-based methods. By using the GCIB process, the ion cluster beam (dry) etches, i.e., sputters, away the surface and will reduce the roughness of the surface and within-wafer and wafer-to-wafer uniformity to a much greater extent than the CMP. Also, by employing GCIB etching, the surface will not suffer plasma damage if the inter-layer dielectric film 12 is porous and has a low dielectric constant (K).

[0028] In the present invention, the GCIB etching process will preferably be performed with an ion dose of approximately between 0.5 and 2.5 E¹⁵ ion-clusters/cm². The gas used in the GCIB process may be composed of a reactive gas, such as, for example but not limited to, Nitrogen Trifluoride (NF₃), Sulfur Hexaflouride (SF₆), Chlorine (Cl₂), in combination with a carrier gas, such as, for example but not limited to, Nitrogen (N₂), or Oxygen (O₂) and Argon (Ar). For the reactive gas, Nitrogen Triflouride may be preferred because Sulfur Hexaflouride is malodorous, and Chlorine is corrosive. The proportion of reactive and carrier gasses may be approximately 1% to 100%. In a preferred embodiment, the proportion of reactive gas may be approximately 1 to 10%, with the remaining 99 to 90% comprising the carrier gas.

[0029] FIGS. 9-11 show a structure formed by the inventive process. As will be appreciated by one skilled in the art, these figures show a scratch-free surface with smooth line edges. These structures are representative of a smoothed surface with variations of less than 1 nm in height across the chip. As can be seen from FIGS. 9-11, there is no evidence of scratches on the metal, nor of erosion of the dielectric layer, even for 25 μm wide lines having 95% pattern density. The structures shown in FIGS. 9 and 10 were created using an ion cluster dose of approximately 2.5 E¹⁵ ion-clusters/cm². The image in FIG. 11 is of a structure without Cu line recess after GCIB removal of the Ta/TaN barrier metal layer. The image in FIG. 11 was created with a scan size of 1.000 μm and a scan rate of 0.8003 Hz; 256 samples were taken. In FIG. 11, the x- and y-axes are marked in 0.200 μm segments, and the z-axis is marked in 35.00 μm segments. These atomic force microscope (AFM) images demonstrate the GCIB etch selectivity between Cu and barrier metal and hard mask material.

[0030] FIG. 12 is a graph showing the line resistance of ten chips—each having nested lines with widths of 2.5 μm, 6 μm, 15 μm, and 25 μm, and having 50% pattern density—formed using the inventive process. Along the x-axis are the wafer IDs, and along the y-axis is the line resistance (in Ohms) distribution of multiple chips in a wafer. As can be seen from the graph, the line resistance on a wafer produced by the inventive process is substantially uniform as compared to conventional processes. As will be appreciated by one skilled in the art, it is desirable to have uniformity of resistance across the chip and wafer in order to optimize performance. More specifically, this graph shows a minimal variation of resistance as measured across the wafers.

[0031] While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.