Digital power supply control

[0001] 1. Field of the Invention

[0002] The present invention generally relates to control of power supplies and voltage regulators/power converters and, more particularly, to high-resolution control of voltage regulation with digital pulse width modulation arrangements of reduced resolution and consequent reduced complexity and cost.

[0003] 2. Description of the Prior Art

[0004] Many types of electrical and electronic devices require power at a substantially constant voltage, although the tolerance for voltage variation of the power supply can vary widely. However, in general, voltage regulation within a relatively small tolerance over a wide range of current loads is highly desirable even though the current load can cause variation in the voltage supplied. Efficiency of the power supply and voltage regulation arrangement is also of high importance, along with cost and complexity of the voltage regulation arrangement.

[0005] For these reasons, switching power supplies are commonly the basic design of choice over analog voltage regulators which often rely upon a significant voltage drop across the regulator at significant currents and thus generally consume significant power, whereas switching voltage regulators control the output voltage over a wide range of current loads by variation of the duty cycle during which input power is connected to the regulator circuit. Analog pulse width modulators have provided good performance but are generally more expensive, subject to noise and often require designs to be specific to particular applications. More recently, digital control has been employed in switching voltage regulators which overcome many of the drawbacks of analog controls and provide more functions more conveniently and at generally reduced cost to improve overall system performance, such as passive component reduction, noise immunity, re-programmability, communication and the like.

[0006] However, an analog power stage (e.g. a switching regulator having analog components) with a digital control loop makes system control more complicated since two quantizers, a digital pulse width modulator (DPWM) 10 and an analog to digital (A/D) converter 20 are introduced into the control loop as shown in FIG. 1. Further, the duty cycle established by the DPWM can only assume discrete values which may or may not coincide with a desired output voltage at a particular load while the resolution of the discrete duty cycle values (ΔD) ultimately determines the resolution of the regulated output voltage (ΔV_o, depicted by the difference/space between dotted lines in FIGS. 2 and 3). That is, if the resolution of the DPWM is not sufficiently high for the desired output voltage to fall within a “zero error” value of A/D converter of resolution ΔV_ADC, depicted as a difference between solid lines, limit cycle oscillations will occur as shown in FIG. 2, as contrasted with a high resolution DPWM; the response of which is shown in FIG. 3. Such limit cycle oscillations and their amplitude and waveform, in particular, are difficult to predict but are significantly more likely to occur using a low resolution DPWM than when using a high resolution DPWM. If limit cycle oscillations occur, the amplitude of the limit cycle oscillations will exceed the resolution of the A/D converter. Thus it is clearly seen that there is a significant trade-off between cost of the A/D converter and DPWM to obtain a given degree of duty cycle resolution and the ability to reliably regulate voltage within a given voltage tolerance.

[0007] As a result of such a trade-off, many DPWM arrangements have been proposed to obtain high duty cycle resolution. For example, in a counter based DPWM, the duty cycle resolution (ΔD) is given by
ΔD=f_sw/f_clock  (1)
where f_sw is the switching frequency of the power stage (e.g. Q1 and Q2 of FIG. 1) and f_clock is the controller system clock. Taking the buck converter arrangement of FIG. 1 as an example, the output voltage resolution (ΔV₀) is given by
ΔV_o=V_IN·ΔD  (2)
where V_IN is the input voltage. Accordingly, it is seen from FIG. 4 that the system clock (f_clock) requirement to achieve a 3 mV output voltage resolution (notwithstanding limit cycle oscillations as shown in FIG. 5) under different switching frequency (f_sw) conditions generally exceed 1 GHz for common or increased f_sw which is not feasible for practical implementations.

[0008] It is therefore an object of the present invention to provide a practical digital pulse width modulation (DPWM) arrangement in a switching voltage regulator which can hold the amplitude of limit cycle oscillations to low and predictable levels.

[0009] In order to accomplish these and other objects of the invention, a power converter including a digital pulse width modulator of low resolution such that limit cycle oscillations occur is provided including a feedback control arrangement for controlling the digital pulse width modulator wherein the feedback control arrangement includes a sampling arrangement and analog to digital converter, an outer control loop for comparing an output voltage of the power converter with a reference voltage and providing an output corresponding to an average difference between the output voltage and the reference voltage, and an inner control loop including an arrangement for providing a signal corresponding to a difference between the output voltage and the output of the outer control loop.

[0010] In accordance with another aspect of the invention, a method of voltage regulation using a switched voltage regulator controlled by a digital pulse width modulator of low resolution such that limit cycle oscillations occur responsive to an output voltage of the voltage regulator wherein the method comprises steps of providing a average of the output voltage of the voltage regulator in an outer feedback loop to the digital pulse width modulator, providing a signal corresponding to a difference between an output voltage of the voltage regulator and the average of said output voltage of the voltage regulator in an inner feedback loop to the digital pulse width modulator.

[0027] Referring now to the drawings, and more particularly to FIGS. 1-4, as discussed above, it is clearly seen that high clock rates are not practical for achieving adequately high voltage resolution while using a relatively low resolution digital pulse width modulator (DPWM). As an alternative to such high system clock frequencies, use of delay lines has been proposed but requires an impractical amount of chip space. Dithering techniques have also been proposed to increase the effective resolution of the DPWM but additional voltage ripple is caused by the dithered duty cycle which limits the potential benefits of such techniques. As can be readily appreciated from the waveforms of limit cycle oscillations as illustrated in FIG. 5, not only does the voltage oscillate at a high frequency but, under load, the high-frequency voltage oscillations are effectively superimposed on a lower frequency near-sinusoidal ripple having a magnitude which is, by itself, comparable to the maximum amplitude of the voltage regulation tolerance acceptable in many applications and unacceptable in many others. Moreover, the amplitude of the voltage variation is largely unpredictable since it results from uncontrolled and unavoidable oscillations due to insufficient resolution at the DPWM.

[0028] Previous studies of this problem have been based on voltage-mode digital control structures as illustrated in FIG. 1, as discussed above. If a low resolution DPWM is used in such an arrangement, limit cycle oscillations are virtually unavoidable because a voltage-mode digital control arrangement can only control the average value of the output voltage. The actual amplitude of the limit cycle oscillations, although greater than the resolution of the A/D converter, are very difficult to predict for the same reason and it is impossible to meet tight voltage regulation specifications where the possibility of unpredictable limit cycle oscillations exists.

[0029] The invention exploits the proposition that different control structures have different characteristics and if there are bands inside the control loop to limit instantaneous output voltage, it may be possible to control or limit the amplitude of limit cycle oscillations. A number of control structures are known such as the hysteretic, constant on-time and constant off-time control structures of FIGS. 6A-6C, respectively, assuming that the output ripple is dominated by the equivalent series resistance (ESR) of the output capacitor or other filter arrangement.

[0030] While the invention will be described in terms of the constant on-time arrangement of FIG. 6B, it should be understood that any of these and other arrangements may be used for practice of the invention. It should also be appreciated from a comparison of any of FIGS. 6A-6C with the exemplary configuration of FIG. 1 (no part of which is admitted to be prior art in regard to the present invention) that the control/feedback loop of each of FIGS. 6A-6C includes a comparator H_v for comparing an output voltage with a reference voltage V_ref and providing an output voltage V_c to a further amplifier arrangement (e.g. a hysteresis or difference amplifier) which also receives a substantially triangular waveform that contains the ripple voltage of the output.

[0031] FIG. 7 is identical to FIG. 6B except that digitalization at the constant on-time control is illustrated by the generally triangular ripple waveform being sampled for digital configuration and thus having a “stepped” configuration, labeled V_0sample, FIG. 8 shows a simulation of the output voltage of the arrangement of FIG. 7 using a fixed control voltage V_c but including V_Osample. As predicted, although there are limit cycle oscillations at the output voltage, the amplitude of those oscillations is limited by the V_c band, which is determined by:
ΔV_oscillation=1/f_sample·ESR·(V_O/L)  (3)
where L is the value of the power stage inductor. In this simulation, the oscillation amplitude is only 3 mV with a sampling frequency of the output voltage of 1.2 MHZ, which is about four times the switching frequency but several orders of magnitude less than the clock frequency suggested to be required as discussed above with reference to FIG. 4. Therefore even without a high resolution DPWM (which is thus seen to be unneeded), the otherwise unpredictable limit cycle oscillation amplitude is well-controlled by use of V_osample in the control loop and is a principal meritorious effect of the invention in accordance with its most basic principles although a somewhat higher sampling frequency (but much reduced from the system clock requirements as discussed above in connection with FIG. 4) is required.

[0032] Nevertheless, use of an increased sampling frequency increases overall cost of A/D converter (ADC) and thus the cost of the controller and, in turn, overall voltage regulator/power converter cost while some oscillation remains, although well-controlled as noted above. In order to further reduce the oscillation amplitude without increasing the cost of the ADC, an additional digital ramp may be added in the control loop signal by any suitable device such as an adder, mixer or difference amplifier 90 as illustrated in FIG. 9, where S_d is the ramp slope and S_f is the output voltage ripple falling slope and S_d is preferably larger than S_f. Thus, if ΔV_ADC/S_d is smaller than the sampling period, 1/f_sample, the oscillation amplitude is determined by:
ΔV_oscillation=(ΔV_ADC/S_d)·ESR·(V_o/L).  (4)
Thus, as S_d is increased, the more the amplitude of the limit cycle oscillation is reduced for a given sampling frequency and, accordingly, the sampling frequency and consequent system cost of the ADC can be reduced. A comparison of the limit cycle oscillations without and with the ramp of FIG. 9 is illustrated in FIGS. 10A and 10B.

[0033] It should be noted that while propagation delay in the inner loop will reduce the transient response of the inner loop, the propagation delay has little influence on the limit cycle oscillation amplitude reduction. As shown in FIGS. 11A and 11B, even when the sampling frequency is reduced to equal the switching frequency, f_sw, of the power sage, oscillation amplitude can be further reduced through proper ramp design. That is, Equation (4), above, provides the oscillation amplitude calculation and a suitable ramp slope may be determined by how much oscillation can be tolerated. The ramp slope can also be determined empirically or in other ways, as well.

[0034] Thus, in summary, the arrangement of FIG. 9, in accordance with a preferred form of the invention, with the buck converter arrangement of FIG. 1, provides (at a switching and sampling frequencies of f_sampling=f_sw=300 KHz) a reduction of the necessary clock rate, f_clock, form 1.2 GHz to 1.2 MHz while holding limit cycle oscillation amplitude to under 1 mV whereas the limit cycle oscillation amplitude of the arrangement of FIG. 1, without benefit of the invention is largely unpredictable and uncontrollable.

[0035] However, it has been found that transient response is somewhat compromised in the arrangement of FIG. 9 including the additional ramp in the control loop. A comparison of the transient response of the arrangement of FIG. 9 without and with the additional ramp waveform in the control loop is illustrated in FIGS. 12A and 12B for f_sample=4f_sw and where, in the digital ramp, S_d=4S_f. This compromise of transient response may be attributed to the fact that the outer control loop compensator is principally designed for compensating the DC error of the output voltage and not for transient response. The transient response is thus principally determined by the gain of the pulse width modulator PWM (e.g. whether or not digital, although digital PWMs will also exhibit quantization effects) in the inner loop which is proportional to 1/S_f. In the control structure of FIG. 9 the gain of the PWM is proportional to 1/(S_f+S_d) (e.g. necessarily smaller than 1/S_d) which results in reduced gain and compromised transient response. (The terminology “inner loop” and “outer loop” as used herein are to be understood as used herein only for identification corresponding to the depiction in the drawings and differentiation of these portions of the control loop from each other and does not imply any particular circuit topology, layout or other electrical or mechanical characteristics thereof.)

[0036] However, to solve this compromise of transient response, a further digital ramp may be added based on the ramp design of FIG. 9 in a small range which can only cover the steady state operation range as shown in FIG. 13, allowing nonlinear modular gain to be realized such that at steady state, the PWM gain is 1/(S_f+S_d) which is good for oscillation amplitude reduction/control while at a load transient, the gain is substantial equal to 1/S_f. Thus, as shown in the graphical comparison of FIGS. 14A and 14B, the transient response on of FIG. 14B approximates the transient response of FIG. 12A, representing the transient response of the arrangement of FIG. 7, without the digital ramp of FIG. 9.

[0037] In view of the foregoing, it is seen that the invention provides for good voltage regulation with good control and limitation of amplitude of limit cycle oscillations which are unavoidable when a low resolution DPWM is used to simplify voltage regulator/power converter designs without requiring additional chip space or other design trade-offs to provide increased effective DPWM resolution and reduce voltage regulator/power converter costs. The invention may be embodied simply as shown in FIG. 7 to provide control of limit cycle oscillation amplitude or enhanced in accordance with the embodiments respectively illustrated in FIG. 9 and/or 13 to provide additional oscillation amplitude reduction as well as reduction in sampling frequency with or without limitation or substantial avoidance of compromise of transient response. The invention can be applied to other duty cycle modulation arrangements such as those of FIGS. 6A and 6C as well as other arrangements as will be evident to those skilled in the art as well as other converter topologies other than the exemplary buck converter topology illustrated. Moreover, any of those arrangements and or topologies may be implemented using as many phases as may be desired for a particular application or power requirement specification as illustrated, for example, in FIG. 15, in which the output of the control loop is distributed to each phase of the voltage regulator/power converter.

[0038] While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.