Intelligent dead time control

[0001] 1. Field of the Invention

[0002] This invention relates to converter circuits and more specifically to a control circuit for reducing the dead time between conduction of high side and low side FETs in such circuit.

[0003] 2. Description of the Related Art

[0004] In DC to DC conversion, “good converters” are measured according to the converter efficiency. Efficiency is determined in accordance with fewest power losses in the converters, such as switching losses and losses due to the Power Device's ON resistance.

[0005] Synchronous rectifiers are commonly used to reduce switching losses, despite their control complexity. In synchronous rectifiers, one of the main contributors of the power losses is the delay between the control of a high-side/control transistor and the low side/synchronous transistor.

[0006] FIG. 1 illustrates a well-known high-speed synchronous buck converter circuit 10. The circuit 10 includes a switching stage having a high side or control Power Device Q₁ and a low side or synchronous Power Device Q₂ coupled at a switching node. The switching stage receives an input D-C voltage V_IN and provides a highly controlled output D-C voltage V₀ at an output node. The circuit 10 has an input capacitor C₁ parallel connected with the switching stage, an output inductor L connected between the switching node and the output node, and an output capacitor C₂ connected to the output node having the output D-C voltage V₀. A load is parallel connected with the output capacitor C₂.

[0007] The Power Devices Q₁ and Q₂ are turned ON and OFF as usual with pulse width modulation (PWM), so the control Power Device Q₁ is ON for a given time while Power Device Q₂ is OFF and, Power Device Q₂ turns ON when Power Device Q₁ turns OFF. The pulse width modulation is controlled to maintain a predetermined output voltage V₀ at the output node even though V_IN, which may be supplied by a battery in a portable electronics device, varies with age, temperature, power demand, etc.

[0008] Care must be taken to prevent simultaneous turn ON of the Power Devices Q₁ and Q₂, which would create a short circuit across the input circuit. Thus, as illustrated in FIG. 2, a certain dead time is always provided during which both Power Devices Q₁ and Q₂ are OFF. It is desirable to reduce this dead time as much as possible, preferably to zero to increase the circuit efficiency.

[0009] Previous attempts to control the dead time include a fixed delay method illustrated in FIG. 3. Here, the optimum delay, when Power Devices Q₁ and Q₂ are OFF, can be changed depending on the load, line, and Power Device. The dead time itself cannot be adjusted to achieve the optimum delay per given conditions.

[0010] An adaptive control method, illustrated in FIG. 4, is a better control scheme than the fixed delay scheme but it does not adjust itself to the changes on load, line & temperature.

[0011] A predictive control scheme illustrated in FIG. 5, monitors a voltage V_SW at a switching node connecting the Power Devices Q₁ and Q₂ and continuously adjusts the delay until it achieves the predetermined value. In this approach, voltage V_SW must go below the ground voltage and is compared to a fixed voltage. The voltage V_SW going negative just enough to create an optimum delay for a minimum power loss. Due to V_SW comparator delay, this approach does not achieve optimum dead time.

[0012] It is an object of the present invention to provide an improved solution to providing a fixed delay for any type of rectifier/Power Device by comparing low side gate drive and switch node/high side gate drive edges to achieve optimum dead time to reduce power losses.

[0013] It is a further object of the present invention to reduce or eliminate any conduction, reverse recovery, and/or shoot through loss.

[0014] A circuit is provided for reducing switching losses in a synchronous rectifier or a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit includes a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage.

[0015] To further optimize, the circuit can be trimmed to have a fixed delay effect. This dead time control circuit can be applied to all types of power switching devices used in half bridge or synchronous buck configurations.

[0016] Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.

[0025] FIG. 1 shows a PWM input to gates of high- and low-side transistors Q₁ and Q₂. The signal to the high-side transistor Q₁ is identified as HGD and the signal to the low-side transistor Q₂ is inverted by an inverter 12 and identified as LGD, having a waveshape LGD shown in FIG. 2. The high- and low-side transistors Q₁ and Q₂ are connecting at a switching node.

[0026] FIG. 2 illustrates, rising and falling edges of the waveshape of the signal LGD aligned with rising and falling edges of a waveshape of a voltage V_SW at the switching node and/or a waveshape of the signal HGD.

[0027] Returning to FIG. 1, in accordance with the invention, in a high speed synchronous buck converter where the low-side transistor Q₂ is made to switch very fast, for example, within one nanosecond, the optimum dead time occurs when a gate signal of the low-side transistor Q₂ is aligned with the rise/fall edges of a waveform of the voltage V_SW and/or the signal HGD.

[0028] The synchronization of the waveshape edges of the voltage V_SW and/or the signal HGD and the waveshape of the signal LGD can be achieved through an analog or digital phase lock loop (PLL) to eliminate phase errors. Thus, as shown in FIG. 6, a PLL circuit 15, which is connected to the circuit of FIG. 1, each edge of the voltage V_SW and/or the signal HGD requires one set of phase detection circuits.

[0029] Using a rising edge of voltage V_SW and/or the signal HGD, for example, if there is a non-overlap between the waveshape of the signal LGD and waveshape of the voltage V_SW and/or the signal HGD in FIGS. 1 and 6, waveshape of the signal LGD, the voltage V_SW and/or the signal HGD will be adjusted by the delay circuits 11 and 13 to introduce an overlap; where there is an overlap, the waveshape of the signal LGD, the voltage V_SW and/or the signal HGD will be adjusted to introduce a non-overlap

[0030] The conduction or reverse recovery losses on the synchronous rectifier are disposed of by monitoring the two control signals, the synchronous rectifier control signal of the signal LGD and the voltage V_SW and/or the signal HGD. As illustrated in FIG. 7, both signal edges are first sensed in a sense delay portion of the circuit 20 and then calibrated in a calibration portion. First, in the sense delay portion, the voltage V_SW and/or the signal HGD and the signal LGD are sensed by edge detect circuits 22 and 24 and processed through optional sense delay circuits 26 and 28, respectfully, for finer adjustment on a delay control loop.

[0031] In the calibration portion, edge compare circuits 34 and 36 compare the signals from the edge delay circuits 26 and 28 to each other and then instruct the pre-settable up/down counter circuits 38 and 40 to advance/pull back the counter. The pre-settable up/down counter circuit 38 receiving input from a rising range select circuit 42 and the pre-settable up/down counter circuit 40 receiving input from a falling range select circuit 44.

[0032] An N-bit counter output of the pre-settable up/down counter circuits 38 and 40, which can be pre-loaded to minimize the edge adjustment operation, is forwarded to rising and falling edge DT control circuits 46 and 48. A value of this N bit counter is decoded to select a corresponding delay. Operation of the circuit 20 continues until edges of both the waveshape of the voltage V_SW and/or the signal HGD and the waveshape of the signal LGD are aligned.

[0033] The circuit 20 compares the two signals and depending on the condition of the timing, a signal to reduce or increase the delay is produced. The delay is adjusted depending on the signal produced. This operation is performed on both, the rising and falling, edges of the control signal. Additionally, a separate delay may be added to this auto calibration to correct any sensing error.

[0034] The circuit 20 finds the optimum delay independent of the output condition—load, line temperature, and/or Power Device. The delay can be adjusted by an optional delay during sensing of the edge of the waveform. There is no need for the voltage V_SW and/or the signal HGD to go below the ground level for the circuit 20 to operate properly.

Fast Control Signal Sensing for a Synchronous Converter

[0035] A capacitor dividers 80a, 80b, illustrated in FIG. 8 as having series connected capacitors C0 and C1 or coupled between nodes LGD and the ground and SW/HGD and the ground, are used to sense the fast moving edge with a different potential. While, the capacitor divider 80 may have been used in many applications, its use with a synchronous converter is novel. A delay of the signal sensing in a control loop is very critical for many time dependent controls. In a case of the synchronous converter, the sensing of the drive signal and/or the switch node voltage is very useful information for optimizing efficiency and performance of the synchronous converter. The swing of the switch node signal to the sense node may be limited by using a resistor divider or a clamp. More power is burned and/or the sensing process is slowed down by limiting the swing.

[0036] The advantages of using the capacitor divider 80 are losses in the speed and DC power. The capacitor divider 80 needs to be charged during the transient period. But, once charged the capacitor divider 80 does not consume any power. For application that require constant DC current, parallel resistor dividers 82a, 82b, having series connected resistors R0 and R1 coupled between nodes LGD and the ground and SW/HGD and the ground, can be added to the capacitor divider to hold the DC voltage value.

[0037] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.