Phase-change memory element

[0001] 1. Field of the Invention

[0002] The invention relates to a memory element, and more particularly to a phase-change memory element.

[0003] 2. Description of the Related Art

[0004] Phase-change memory is a scalable, high speed, and non-volatile memory technology. It is targeted typically for mobile devices which require low power consumption. A phase-change memory cell must therefore provide low programming current, avoidance of high voltages, smaller cell size, faster phase transformation speed, and low cost. These requirements are difficult to meet given the current state of the art.

[0005] The most straightforward way to reduce the programming current is to reduce the heating area. A benefit of this strategy is simultaneous reduction of cell size. However, reducing the area results in a higher cell resistance, which increases the required driving voltage. All other considerations being the same, the amount of Joule heating is conserved, meaning the operating voltage is inversely proportional to the programming current. This is clearly not desirable. Reducing heating area does not necessarily improve other performance features. Phase transformation speed requires good thermal uniformity within the active region of the cell.

[0006] In reality, cooling becomes significant for smaller structures, and loss to environment becomes more important with increased surface/volume ratio. As a result, temperature uniformity is degraded. In addition, the required current density must increase as heating area is reduced. This poses an electromigration concern for reliability. Hence, it is important to not only reduce the current, but also required heating. Since the amount of Joule heating input is reduced, heat loss to the environment must be reduced even further.

[0007] The heating loss is proportional to the thermal conductivity of the surrounding dielectric material. As a reference, the thermal conductivity of a commonly used phase-change chalcogenide, Ge₂Sb₂Te₅, is experimentally measured to have a range of values, averaging around a value of 0.3 W/m-K. The low conductivity is due to both low electron density and vacancies in the microstructure which enhance phonon scattering. Since it is the active material, it obviously cannot serve as the surrounding dielectric. Silicon nitride and silicon oxide are stable in contact with the chalcogenide. However, their thermal conductivities approach and sometimes exceed 1 W/m-K, which prohibits scaling down the programming current beyond the current state of the art.

[0008] One solution uses a mixture of the low thermal conductivity chalcogenide material with a stable higher thermal conductivity dielectric, such that the effective thermal conductivity of the mixture approaches that of the chalcogenide.

[0009] U.S. Pat. No. 5,933,365 “Memory element with energy control mechanism” discloses the use of thermal isolation layers which at least partially encapsulate the phase-change material. However, the selection of candidate materials far exceeds the range of materials available for state-of-the-art memory cell fabrication, and do not reflect the currently known thermal conductivities of such materials.

[0010] Therefore, it is necessary to develop a phase-change memory to solve the previously described problems.

[0011] An exemplary embodiment a phase-change memory element comprises a composite layer comprising a dielectric material and a low thermal conductivity material, a via hole within the composite layer, and a phase-change material occupying at least one portion of the via hole.

[0012] According to another embodiment of the invention, a phase-change memory element comprises a substrate, an electrode formed on the substrate, a composite layer formed on the substrate comprising a dielectric material and a low thermal conductivity material, a via hole passing through the composite layer, and a phase-change material occupying at least one portion of the via hole and contacting the electrode.

[0013] A detailed description is given in the following embodiments with reference to the accompanying drawings.

[0019] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0020] First, referring to FIG. 1a, a substrate 10 with a bottom electrode 12 formed thereon is provided, and an isolation layer 14 surrounds the bottom electrode 12 exposing the top surface 15 of the bottom electrode 12. Particularly, the substrate 10 can be a substrate employed in a semiconductor process, such as silicon substrate. The substrate 10 can be a substrate comprising a complementary metal oxide semiconductor (CMOS) circuit, isolation structure, diode, or capacitor. The accompanying drawings show the substrate 10 in a plain rectangle in order to simplify the illustration. Suitable material for the bottom electrode 12, for example, is Al, W, Mo, TiN, or TiW. The isolation layer 14 can be a silicon-containing compound, such as silicon nitride or silicon oxide.

[0021] Next, referring to FIG. 1b, a composite layer 20 is formed on the bottom electrode 12 and the isolation layer 14, wherein the composite layer 20 comprises alternating layers of the dielectric material layers 16 and the low thermal conductivity material layers 18. At least one layer of all the dielectric material layers 16 and the low thermal conductivity material layers are provided. The thickness of the dielectric material layers 16, and of the low thermal conductivity material layers 18 can be at least 3 nm. The low thermal conductivity material 18 has a thermal conductivity of 0.1 W/m-K to 1 W/m-K, such as 0.2˜0.3 W/m-K, and can be phase-change material, nitrogen-doped phase-change material, or oxygen-doped phase-change material, such as Ge₂Sb₂Te₅. The dielectric material 16 comprises silicon oxide, silicon nitride, or combinations thereof.

[0022] Next, referring to FIG. 1c, the composite layer 20 is patterned to form a via hole 22 passing therethrough by photolithography and etching, exposing the top surface 15 of the bottom electrode 12. The composite layer 20, for example, is dry etched.

[0023] Next, referring to FIG. 1d, a phase-change material layer 24 is deposited to fill the via hole 22. The phase-change material layer 24 can comprise In, Ge, Sb, Te or combinations thereof, such as GeSbTe or InGeSbTe.

[0024] Finally, referring to FIG. 1e, a top electrode 26 is formed on the composite layer 20 and contacts the phase-change material layer 24. Suitable material of the top electrode 26, for example, can be TaN, W, TiN, or TiW.

[0025] First, referring to FIG. 2a, a substrate 100 with a bottom electrode 102 formed thereon is provided, and an isolation layer 104 surrounds the bottom electrode 102 exposing the top surface 105 of the bottom electrode 102. Particularly, the substrate 100 can be a substrate employed in a semiconductor process, such as silicon substrate. The substrate 100 can be a substrate comprising a complementary metal oxide semiconductor (CMOS) circuit, isolation structure, diode, or capacitor. The accompanying drawings show the substrate 100 in a plain rectangle in order to simplify the illustration. Suitable material for the bottom electrode 102, for example, is Al, W, Mo, TiN, or TiW. The isolation layer 104 can be a silicon-containing compound, such as silicon nitride or silicon oxide.

[0026] Next, referring to FIG. 2b, a composite layer 110 is formed on the bottom electrode 102 and the isolation layer 104, wherein the composite layer 110 consists of a mixture of the dielectric material 106 and the low thermal conductivity material 108. Particularly, the weight ratio of the composite layer between the dielectric material and the low thermal conductivity material is 1:10˜1:1. The low thermal conductivity material 108 has a thermal conductivity of 0.1 W/m-K to 1 W/m-K, such as 0.2˜0.3 W/m-K, and can be phase-change material, nitrogen-doped phase-change material, or oxygen-doped phase-change material, such as Ge₂Sb₂Te₅. The dielectric material 106 comprises silicone oxide, silicone nitride, or combinations thereof.

[0027] Next, referring to FIG. 2c, the composite layer 110 is etched to form a via hole 111 passing therethrough by photolithography, exposing the top surface 105 of the bottom electrode 102. Composite layer 110, for example, is dry etched.

[0028] Next, referring to FIG. 2d, a phase-change material layer 112 is deposited to fill the via hole 1 111. The phase-change layer 112 can comprise In, Ge, Sb, Te or combinations thereof, such as GeSbTe or InGeSbTe.

[0029] Finally, referring to FIG. 2e, a top electrode 114 is formed on the composite layer 110 and contacts the phase-change material layer 112. Suitable material of the top electrode 114, for example, is TaN, W, TiN, or TiW.

[0030] First, referring to FIG. 3a, a substrate 200 with a bottom electrode 202 formed thereon is provided, and an isolation layer 204 surrounds the bottom electrode 202 exposing the top surface 205 of the bottom electrode 202. Particularly, the substrate 200 can be a substrate employed in a semiconductor process, such as silicon substrate. The substrate 200 can be a substrate comprising a complementary metal oxide semiconductor (CMOS) circuit, isolation structure, diode, or capacitor. The accompanying drawings show the substrate 200 in a plain rectangle in order to simplify the illustration. Suitable material for the bottom electrode 202, for example, is Al, W, Mo, TiN, or TiW. The isolation layer 204 can be a silicon-containing compound, such as silicon nitride or silicon oxide.

[0031] Next, referring to FIG. 3b, a phase-change material layer 212 is formed on the bottom electrode 202 and electrically connected therewith, and a top electrode 214 is formed on the phase-change material layer 212 and contacts the phase-change material layer 212. The phase-change layer 212 can comprise In, Ge, Sb, Te or combinations thereof, such as GeSbTe or InGeSbTe. Suitable material of the top electrode 214, for example, is TaN, W, TiN, or TiW. Formation of the phase-change material layer 212 and top electrode 214 can comprise: sequentially forming a phase-change material layer and a conductive layer on the substrate 200, and patterning the phase-change material layer and the conductive layer by photolithography and etching to form the phase-change material layer 212 and top electrode 214 patterns.

[0032] Next, referring to FIG. 3c, dielectric material layers 206 and low thermal conductivity material layers 208 are alternately formed on the substrate 200. Particularly, the weight ratio of the composite layer between the dielectric material and the low thermal conductivity material is 1:10˜1:1. The low thermal conductivity material 208 has a thermal conductivity of 0.1 W/m-K to 1 W/m-K, such as 0.2˜0.3 W/m-K, and can be phase-change material, nitrogen-doped phase-change material, or oxygen-doped phase-change material, such as Ge₂Sb₂Te₅. The dielectric material 206 comprises silicon oxide, silicon nitride, or combinations thereof.

[0033] Finally, referring to FIG. 3d, the substrate is etched to remove the dielectric material layers 206 and low thermal conductivity material layers 208 over the top electrode 214 and the substrate 200, exposing the top surface of the top electrode 214 and the substrate 200. FIG. 4 is a top-view of the phase-change memory element according to FIG. 3d. In this step, the dielectric material layers 206 and low thermal conductivity material layers 208 are etched to form a composite layer 210 comprising alternating concentric annular layers of the dielectric material 206a and the low thermal conductivity material 208a surrounding the phase-change material layer 212 and top electrode 214 patterns. Particularly, the dielectric material 206a directly contacts and surrounds the sidewalls of the phase-change material layer 212 and top electrode 214.

[0034] Accordingly, the disclosed phase-change memory element allows reduction of both programming current and programming voltage, since the required Joule heating is reduced. Further, since the required programming current density is reduced, reliability is also enhanced. Moreover, the fabrication process is relatively simple and can accommodate various cell designs, and low cost can be maintained.

[0035] While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.