Voltage controlled oscillator with switching bias

[0001] This application claims priority to and the benefit of Korean Patent Application No. 2007-0042003, filed Apr. 30, 2007, the disclosure of which is incorporated herein by reference in its entirety.

[0002] 1. Field of the Invention

[0003] The present invention relates to a voltage controlled oscillator with a switching bias, and more specifically, to a voltage controlled oscillator to which a switching bias technique is applied so as to enhance phase noise characteristics and stabilize the magnitude of an oscillation waveform.

[0004] The present invention is derived from a project entitled “Development of Digital RF and ADC Chips for Multi-Mode SDR Terminal [2006-S-015-01]” conducted as an IT R&D program for the Ministry of Information and Communication (Republic of Korea).

[0005] 2. Discussion of Related Art

[0006] In general, a voltage controlled oscillator means an oscillator which changes the capacitance of a variable capacitor through voltage adjustment, thereby adjusting a frequency. Such a voltage controlled oscillator is an essential part of all electric communication systems and may be used when a frequency of a predetermined signal is up-converted or down-converted.

[0007] FIG. 1 is a circuit diagram of a conventional voltage controlled oscillator, and specifically, a voltage controlled oscillator for preventing flicker noise of a bias circuit.

[0008] As shown in FIG. 1, the voltage controlled oscillator 10 includes an LC resonance circuit 12, a loss compensation circuit 14 for compensating for a loss, and a bias circuit 16 for supplying a bias current. The connection relationship between the respective circuits will be briefly described as follows.

[0009] First and second inductors L1 and L2 are respectively connected between a power supply terminal VDD, and a first node Q11 and a second node Q12. A first varactor CV1 is connected between a voltage control terminal VC and the first node Q11, and a second varactor CV2 is connected between the voltage control terminal VC and the second node Q12. Drain, gate, and source terminals of a first NMOS transistor M1 are connected to the first node Q11, the second node Q12 and a third node Q13, respectively. Drain, gate, and source terminals of a second NMOS transistor M2 are connected to the second node Q12, the first node Q11 and the third node Q13, respectively. A third inductor L3 is connected between the third node Q13 and a fourth node Q14 and a first capacitor C1 is connected between the third node Q13 and a ground terminal GND. Drain, gate, and source terminals of a third NMOS transistor M3 are connected to the fourth node Q14, a bias voltage terminal VB, and the ground terminal GND, respectively. A second capacitor C2 is connected between the fourth node Q14 and the ground terminal GND.

[0010] In the voltage controlled oscillator 10 configured in such a manner, when flicker noise of the bias circuit 16 is up-converted into an oscillation waveform, phase noise characteristics may be reduced.

[0011] To solve such a problem, a method has been disclosed in which the third inductor L3 and the first capacitor C1 are connected in parallel to each other between the loss compensation circuit 14 and the bias circuit 16, and are caused to resonate at two times greater oscillation frequency such that the third node Q13 has a high impedance value at two times greater oscillation frequency. Then, the flicker noise generated from the bias circuit 16 has a small effect on the oscillation node.

[0012] This is implemented through the result of research in which, when a parallel LC resonance circuit was provided between a loss compensation circuit and a bias circuit such that the resonance frequency thereof became two times larger than an oscillation frequency, it was possible to lower flicker noise of the bias circuit which had an effect on an oscillation waveform. The result of the research is disclosed in “A Filtering Technique to Lower LC Oscillator Phase Noise” (IEEE Journal of Solid-State Circuits, December, 2001) by Emad Hegazi.

[0013] In the above-described voltage controlled oscillator 10, however, the inductor L3 with a large volume should be used. Therefore, when an integrated circuit is designed, a chip area inevitably increases. Further, other frequency components, excluding a two times greater frequency than the oscillation frequency, are not suppressed at the third node Q13.

[0014] Further, since the magnitude of the oscillation waveform significantly changes with respect to changes in external conditions, such as frequency tuning, a process change, a temperature change, and so on, the operation of the voltage controlled oscillator is unstabilized.

[0015] The present invention is directed to a voltage controlled oscillator to which a switching bias technique is applied so as to lower flicker noise of a bias circuit and enhance phase noise characteristics, thereby reducing the overall chip area and making it possible to achieve integration.

[0016] The present invention is also directed to a voltage controlled oscillator, in which a common mode voltage applied to a bias circuit is negatively fed back to an oscillation waveform to stabilize the magnitude of the oscillation waveform of the voltage controlled oscillator with respect to a change in an external condition.

[0017] One aspect of the present invention provides a voltage controlled oscillator with a switching bias including: an LC resonance circuit which oscillates a resonance frequency depending on an input voltage; a loss compensation circuit composed of first and second transistors which amplify the oscillated resonance frequency; a bias circuit composed of third and fourth transistors for providing a bias current to the first and second transistors; and a peak detector which detects a peak value from an oscillation waveform of the LC resonance circuit and then applies the detected peak value to the third and fourth transistors of the bias circuit, the peak detector being composed of fifth and sixth transistors and third and fourth capacitors.

[0018] Another aspect of the present invention provides a voltage controlled oscillator with a switching bias including: an LC resonance circuit which oscillates a resonance frequency depending on an input voltage; a loss compensation circuit composed of first and second transistors which amplify the oscillated resonance frequency; a bias circuit composed of third and fourth transistors for providing a bias current to the first and second transistors; and a switching circuit which turns on/off the third and fourth transistors of the bias circuit depending on the oscillation waveform of the LC resonance circuit.

[0019] Still another aspect of the present invention provides a voltage controlled oscillator with a switching bias including: an LC resonance circuit which oscillates a resonance frequency depending on an input voltage; a loss compensation circuit composed of first and second transistors which amplify the oscillated resonance frequency; a bias circuit composed of third and fourth transistors for providing a bias current to the first and second transistors; a peak detector which detects a peak value from an oscillation waveform of the LC resonance circuit and then applies the detected peak value to the third and fourth transistors of the bias circuit, the peak detector being composed of fifth and sixth transistors and third and fourth capacitors; and a switching circuit which turns on/off the third and fourth transistors of the bias circuit depending on the oscillation waveform of the LC resonance circuit.

[0028] Before the present invention is described, a research result will be briefly described. In the research, when a switching bias technique was used instead of applying a constant voltage to the gate terminal of a MOS transistor through which a bias current was flowed, flicker noise was lowered by 5-7 dB. The result of the research is disclosed in “MOSFET 1/f Noise Measurement under Switched Bias Conditions” (IEEE Electron Device Letters, January, 2000) by A. P. van der Wel.

[0029] In the present invention, the switching bias technique is applied to a voltage controlled oscillator in accordance with the result of the above research. That is, an oscillation waveform of the voltage controlled oscillator is used for switching a bias circuit. Then, phase noise characteristics are enhanced, and the magnitude of the oscillation waveform is stabilized. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0030] FIGS. 2A and 2B are a block diagram and a circuit diagram of a voltage controlled oscillator according to a first exemplary embodiment of the present invention.

[0031] As shown in FIGS. 2A and 2B, the voltage controlled oscillator 100 according to the first exemplary embodiment of the present invention includes an LC resonance circuit 120 which oscillates a resonant frequency depending on an input voltage, a loss compensation circuit 140 which amplifies the resonant frequency oscillated from the LC resonance circuit 120 so as to compensate for a loss, a bias circuit 160 which provides a bias current to the loss compensation circuit 140, and a peak detector 180 which detects a peak value from an oscillation waveform of the LC resonance circuit 120 and then applies the detected peak value to the bias circuit 160.

[0032] The LC resonance circuit 120 includes a first inductor L1, a second inductor L2, a first varactor CV1, and a second varactor CV2. The loss compensation circuit 140 includes a first NMOS transistor M1 and a second NMOS transistor M2.

[0033] The bias circuit 160 includes a third NMOS transistor M3 and a fourth NMOS transistor M4, and the peak detector 180 includes a fifth NMOS transistor M5, a sixth NMOS transistor M6, a third capacitor C3, and a fourth capacitor C4.

[0034] The connection relationship between the respective circuits will be described in detail.

[0035] The first and second inductors L1 and L2 are respectively connected between a power supply terminal VDD, and a first node Q21 and a second node Q22. The first and second varactors CV1 and CV2 are respectively connected between a voltage control terminal VC, and the first node Q21 and the second node Q22. Here, the first and second nodes Q21 and Q22 mean oscillation nodes which are connected to one end and the other end of the LC resonance circuit 120.

[0036] Drain, gate, and source terminals of the first NMOS transistor M1 are connected to the first node Q21, the second node Q22, and a third node Q23, respectively. Drain, gate, and source terminals of the second NMOS transistor M2 are connected to the second node Q22, the first node 21, and the third node Q23, respectively. Here, the third node Q23 means a common node of the first and second NMOS transistors M1 and M2.

[0037] Drain, gate, and source terminals of the third NMOS transistor M3 are connected to the third node Q23, a sixth node Q26, and a ground terminal GND, respectively. Drain, gate, and source terminals of the fourth NMOS transistor M4 are connected to the third node Q23, the sixth node Q26, and the ground terminal GND, respectively. Here, the sixth node Q26 means a common node of the fifth and sixth transistors M5 and M6.

[0038] Source, gate, and drain terminals of the fifth NMOS transistor M5 are connected to the first node Q21, the second node Q22, and the sixth node Q26, respectively. Gate, source, and drain terminals of the sixth NMOS transistor M6 are connected to the first node Q21, the second node Q22, and the sixth node Q26, respectively. The third and fourth capacitors C3 and C4 are connected between the sixth node Q26 and the ground terminal GND, respectively.

[0039] The peak detector 180 detects a peak value V_K from the oscillation waveforms of the oscillation nodes Q21 and Q22 and then applies the detected peak value V_K to the bias circuit 160.

[0040] Here, two differential output waveforms of the LC resonance circuit 120 have the same magnitude and a phase difference of π in radian. Therefore, when the differential output waveforms are set to A sin(ωt+φ) and A sin(ωt+π+φ), respectively, and a DC value of the peak detector 180 and a current value of the bias circuit 160 are represented by V_K and I_OSC, respectively, the magnitude A of the oscillation waveform is proportional to the bias current I_OSC. That is, as the bias current I_OSC increases, the magnitude A of the oscillation waveform also increases, and as the bias current I_OSC decreases, the magnitude A of the oscillation waveform also decreases.

[0041] Further, when the magnitude A of the oscillation waveform increases, a positive peak value of the peak detector 180 increases and a negative peak value thereof decreases.

[0042] That is, when the bias circuit 160 is composed of NMOS transistors, the peak detector 180 should be composed of a negative peak detector which can detect a negative peak value. Referring to FIG. 3A, the negative peak detector will be described in more detail below.

[0043] FIG. 3A is a circuit diagram of the negative peak detector.

[0044] Referring to FIG. 3A, in the negative peak detector, the source, gate, and drain terminals of the fifth NMOS transistor MN5 are respectively connected to the first node Q21, the second node Q22, and the sixth node Q26. The gate, source, and drain terminals of the sixth NMOS transistors MN6 are respectively connected to the first node Q21, the second node Q22, and the sixth node Q26. The third and fourth capacitors C3 and C4 are respectively connected between the sixth node Q26 and the ground terminal GND.

[0045] In the negative peak detector configured in such a manner, the first and second nodes Q21 and Q22 are respectively connected to the oscillation nodes Q21 and Q22 of the LC resonance circuit 120 which differentially operate. Whenever a potential difference between the two differential output nodes is generated, the fifth and sixth NMOS transistors MN5 and MN6 are complementarily turned on/off so as to charge the third and fourth capacitors C3 and C4 with a negative peak value of the oscillation waveform.

[0046] Referring again to FIG. 2B, when the bias current I_OSC increases so that the magnitude of the oscillation waveform increases, the negative peak value of the oscillation waveform detected by the negative peak detector decreases. Further, as the negative peak value is applied as a common mode voltage of the bias circuit 160, the bias current I_OSC decreases again. As a result, the magnitude of the oscillation waveform decreases.

[0047] That is, as the peak value of the oscillation waveform detected by the peak detector 180 is negatively fed back to the oscillation waveform, the magnitude of the oscillation waveform can be stabilized.

[0048] Meanwhile, when the bias circuit 160 is composed of PMOS transistors, and if the magnitude A of the oscillation waveform increases, the negative peak value of the peak detector 180 increases, and the positive peak value thereof decreases. Accordingly, the peak detector 180 should be composed of a positive peak detector which can detect a positive peak value. The positive peak detector will be described in more detail below with reference to FIG. 3B.

[0049] FIG. 3B is a circuit diagram of the positive peak detector.

[0050] Referring to FIG. 3B, in the positive peak detector, the source, gate, and drain terminals of the fifth PMOS transistor MP5 are respectively connected to the first node Q21, the second node Q22, and the sixth node Q26, and the gate, source and drain terminals of the sixth PMOS transistor MP6 are respectively connected to the first node Q21, the second node Q22, and the sixth node Q26. The third and fourth capacitors C3 and C4 are respectively connected between the sixth node Q26 and the ground terminals GND.

[0051] In the positive peak detector configured in such a manner, the first and second nodes Q21 and Q22 are respectively connected to the oscillation nodes Q21 and Q22 of the LC resonance circuit 120 which differentially operate. Whenever a potential difference between the two differential output nodes is generated, the fifth and sixth PMOS transistors MP5 and MP6 are complementarily turned on/off so as to charge the third and fourth capacitors C3 and C4 with a positive peak value of the oscillation waveform.

[0052] That is, when the bias current I_OSC increases so that the magnitude of the oscillation waveform increases, the positive peak value detected by the positive peak detector 180 decreases, and as the positive peak value is applied to the bias circuit 160, the bias current I_OSC decreases again. As a result, the magnitude of the oscillation waveform decreases.

[0053] As the peak value of the oscillation waveform detected by the peak detector 180 is applied as a common mode voltage of the bias circuit 160, the peak value of the oscillation waveform is negatively fed back to the oscillation waveform. Accordingly, when the magnitude A of the oscillation waveform is controlled by a proportional relationship between the bias current value I_OSC and the magnitude A of the oscillation waveform such that the oscillation reaches a normal state, the magnitude A of the oscillation waveform can be stabilized.

[0054] FIGS. 4A and 4B are a block diagram and a circuit diagram of a voltage controlled oscillator according to a second exemplary embodiment of the present invention.

[0055] The voltage controlled oscillator according to the second exemplary embodiment of the present invention has a structure in which a switching circuit 190 is added to the structure shown in FIGS. 2A and 2B such that the switching bias technique is applied. In the voltage controlled oscillator, first and second resistors R1 and R2 are connected to an output of the peak detector 180, and first and second capacitors C1 and C2 are connected to oscillation nodes Q41 and Q42, respectively, thereby constructing the switching circuit 190.

[0056] Here, output values of the switching circuit 190 are V_K + A sin(ωt+φ) and V_K + A sin(ωt+π+φ), respectively. The output values are applied to the bias circuit 160 so as to turn on/off the transistors of the bias circuit 160.

[0057] Accordingly, flicker noise of the MOS transistor used in the bias circuit 160 is lowered, so that phase noise characteristics of the voltage controlled oscillator 100 are enhanced. This will be described in more detail below.

[0058] The oscillation waveforms of the oscillation nodes Q41 and Q42 are applied to the bias circuit 160 through the first and second capacitors C1 and C2 so as to turn on/off the third and fourth NMOS transistors M3 and M4. When the third NMOS transistor M3 is turned on during a half period of the oscillation waveform, the fourth NMOS transistor M4 is turned off. Further, when the third NMOS transistor M3 is turned off during a half period of the oscillation waveform, the fourth NMOS transistor M4 is turned on.

[0059] That is, the flicker noise of the bias circuit 160 is lowered through the switching operation of the third and fourth transistors M3 and M4 so that the phase noise characteristics are enhanced.

[0060] When the magnitude of the oscillation waveforms at the oscillation nodes Q41 and Q42 increases, the potential of an output node Q46 of the peak detector 180 decreases. Accordingly, the common mode potential of the gate terminals of the third and fourth transistors M3 and M4 composing the 20 bias circuit 160 also decreases. As a result, the current flowing through the LC resonance circuit 120 decreases, so that the oscillation waveform decreases.

[0061] That is, when the magnitude of the oscillation waveform is controlled by the negative feedback structure such that the oscillation reaches a normal state, the magnitude of the oscillation waveform is stabilized.

[0062] Meanwhile, the bias circuit 160 may be differentially configured for a smooth oscillation operation of the LC resonance circuit 120. This will be described in more detail below.

[0063] FIG. 5 is a circuit diagram of a voltage controlled oscillator according to a third exemplary embodiment of the present invention.

[0064] First and second inductors L1 and L2 are respectively connected between a power supply terminal VDD, and a first node Q51 and a second node Q52. First and second varactors CV1 and CV2 are respectively connected between a voltage control terminal VC, and the first node Q51 and the second node Q52. The drain, gate and source terminals of a first NMOS transistor M1 are respectively connected to the first node Q51, the second node Q52, and a third node Q53. The drain, gate and source terminals of a second NMOS transistor M2 are respectively connected to the second node Q52, the first node Q51, and a fourth node Q54. The drain, gate and source terminals of the third NMOS transistor M3 are respectively connected to the fourth node Q54, a fifth node Q55, and a ground terminal GND. The drain, gate and source terminals of a fourth NMOS transistor M4 are respectively connected to the third node Q53, a sixth node Q56, and the ground terminal GND. The source, gate and drain terminals of the fifth NMOS transistor M5 are respectively connected to the first node Q51, the second node Q52, and a seventh node Q57. The source, gate and drain terminals of a sixth NMOS transistor M6 are respectively connected to the second node Q52, the first node Q51, and the seventh node Q57. A first capacitor C1 is connected between the first node Q51 and the fifth node Q55, and a second capacitor C2 is connected between the second node Q52 and the sixth node Q56. Third and fourth capacitors C3 and C4 are respectively connected between the seventh node Q57 and the ground terminal GND. First and second resistors R1 and R2 are respectively connected between the seventh node Q57, and the fifth node Q55 and the sixth node Q56. A fifth capacitor C5 is connected between the third node Q53 and the fourth node Q54. Here, the fifth capacitor C5 is used to increase negative resistance which compensates for a loss.

[0065] In the voltage controlled oscillator configured in such a manner, the drain terminals of the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected to the source terminals of the second NMOS transistor M2 and the first NMOS transistor M1 so that the bias circuit 160 differentially operates.

[0066] More specifically, between the first node Q51 and the second node Q52, the third NMOS transistor M3 and the second NMOS transistor M2 are connected with a phase difference of π in radian through the first capacitor C1. Further, the fourth NMOS transistor M4 and the first NMOS transistor M1 are also connected with a phase difference of π through the second capacitor C2. Accordingly, when the third NMOS transistor M3 and the second NMOS transistor M2 are turned on during a half period of the oscillation waveform, the fourth NMOS transistor M4 and the first NMOS transistor M1 are turned off. On the contrary, when the third NMOS transistor M3 and the second NMOS transistor M2 are turned off during a half period of the oscillation waveform, the fourth NMOS transistor M4 and the first NMOS transistor M1 are turned on.

[0067] That is, smooth oscillation of the LC resonance circuit 120 can be achieved through the differential operation of the bias circuit 160, even though an external condition is changed by a process change, a temperature change and so on. Further, the magnitude of the oscillation waveform can be stabilized while maintaining a constant value.

[0068] FIGS. 6 to 8 are graphs showing the results obtained by simulating magnitude characteristics of an oscillation waveform on frequency tuning, a process variation, and a temperature change, respectively, with respect to the voltage controlled oscillator according to the present invention and the conventional voltage controlled oscillator.

[0069] To obtain results under the same condition, the voltage controlled oscillator according to the present invention and the conventional voltage controlled oscillator are designed to have the same oscillation frequency and power consumption.

[0070] As shown in FIG. 6, it can be seen that, during the frequency tuning, a change in magnitude of the oscillation waveform with respect to a frequency change in the voltage controlled oscillator according to the present invention is 2.5 times smaller than in the conventional voltage controlled oscillator.

[0071] Further, as shown in FIG. 7, it can be seen that a change in magnitude of the oscillation waveform with respect to a process variation in the voltage controlled oscillator according to the present invention is three times smaller than in the conventional voltage controlled oscillator. Furthermore, as shown in FIG. 8, it can be seen that a change in the magnitude of the oscillation waveform with respect to a temperature change in the voltage controlled oscillator according to the present invention is three times smaller than in the conventional voltage controlled oscillator.

[0072] FIG. 9 is a diagram comparatively showing phase noise characteristics of the voltage controlled oscillator according to the present invention and the conventional voltage controlled oscillator. In the voltage controlled oscillator according to the present invention to which the switching bias technique is applied, the flicker noise of the bias circuit is lowered, so that the phase noise characteristics of the voltage controlled oscillator according to the present invention are enhanced by 3.5 dBc in comparison with the conventional voltage controlled oscillator.

[0073] According to the present invention as described above, as a switching bias technique is applied to a voltage controlled oscillator, the flicker noise of a bias circuit is lowered. Therefore, while the phase noise characteristics are enhanced, the overall chip area is reduced, which makes it possible to achieve integration.

[0074] Further, a common mode voltage applied to the bias circuit is negatively fed back to the oscillation waveform. Therefore, it is possible to stabilize the magnitude of the oscillation waveform of the voltage controlled oscillator with respect to a change in an external condition.

[0075] While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.