US 7,651,905 B2Grant
Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
Issue Date:2010-01-26
•11 Claims
•6 Drawing Sheets
Abstract
An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.
Metadata
Assignee
- Semi Solutions, LLC
Inventor
- Ashok Kumar Kapoor
Application Information
Application Number:US 11/110,457
Filing Date:2005-04-19
Priority Date:2005-01-12
Art Unit:2822
Classifications
IPC:
H01L21/8234H01L21/336H01L21/8238H01L27/10H01L29/739H01L29/76H01L29/94H01L31/062H01L31/113H01L31/119
Patent Drawings (6 sheets)
Description
Cross Reference to Other Applications
[0001] This application claims priority to U.S. provisional patent application Ser. No. 60/643,071, filed Jan. 12, 2005, which application is incorporated herein its entirety by this reference thereto.
Background of the Invention
[0002] 1. Technical Field
[0003] The invention relates generally to gate leakage of MOS devices. More specifically, the invention relates to the reduction of gate leakage in MOS memory cells.
[0004] 2. Discussion of the Prior Art
[0005] In the semiconductor manufacturing world the leading manufacturing processes are based on complementary metal-oxide semiconductor (CMOS) devices. The CMOS technology is in constant advancement, particularly by scaling down line widths, i.e., the minimal feature size for a given manufacturing technology, typically referred to as a process node. The decrease in feature size allows for improved performance of a CMOS device, evidenced by increased speed, reduced area, and increased functionality contained in a single chip. As line widths shrink it is generally observed that chip sizes are actually increasing. This happens because more functionality is packed onto these chips. Power dissipation is therefore one of the most pertinent problems of CMOS technology.
[0006] As the minimum feature size of a technology node is reduced so is the thickness of the gate oxide thickness as well as the power supply. The reduction of the power supply voltage is done to reduce the electrical field that develops across the oxide. For example, a typical 0.35 micron line width requires a power supply of 3.3V and gate oxide thickness of 70 Å; while in a 0.25 micron line width requires a 2.5V power supply and a 40 Å gate oxide thickness. Further reduction of the line width, for example to 90 nano-meters, requires the reduction of the power supply voltage to less than 1.0V and a further reduction of the gate oxide thickness. At these thicknesses of the gate oxide, significant tunneling current across the oxide is recorded. With the next generation of technology scaling to 65 nano-meters, a gate oxide thickness of less than 20 Å is used and the power supply voltage is further reduced to 0.7V. At this process node there is already recorded an extremely high level of gate current, causing concern that it has the potential of limiting the functionality of the CMOS technology.
[0007] It is known in the art that many solutions for reducing the gate current leakage are being sought, including the use of high dielectric constant insulators. However, no single solution has matured to provide production worthiness. A person skilled-in-the-art would further note that the problem caused by high leakage current through the gate oxide is found to be more severe in memory cells as compared to standard CMOS logic. In view of the limitations of the prior art, it would be advantageous to provide a solution to limit the gate current of CMOS transistors. It would be further advantageous if such a solution would be useful for the transistors used in memory cells, such as SRAM cells.
Summary of the Invention
[0008] An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. The invention is further applicable in other instances where the gate leakage needs to be reduced. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.
Brief Description of the Drawings
[0009] FIG. 1 shows cross-coupled CMOS inverters forming a SRAM cell;
[0010] FIG. 2 shows a representative current—voltage characteristics of transistor drain current, gate tunneling current, and gate biasing forward and reverse biasing current;
[0011] FIG. 3 shows a circuit configuration of NMOS and PMOS transistors with the diode connected to the gate, where the diode has very low forward drop and very high reverse current;
[0012] FIG. 4 shows a SRAM cell having a diode connected in series with the gate of the NMOS transistors in the inverter to reduce gate leakage;
[0013] FIG. 5A shows a voltage waveform at the input and output of a CMOS inverter;
[0014] FIG. 5B shows a voltage waveform at the input and output of a CMOS inverter with diode coupled gate; and
[0015] FIGS. 6A-6C shows the cross sections of NMOS and PMOS transistors having diodes in accordance with an exemplary implementation of the disclosed invention.
Detailed Description of the Invention
[0016] The invention comprises a simple to implement apparatus and method for the reduction of gate leakage of deep sub-micron metal oxide semiconductor (MOS) transistors, especially those used in a cross coupled static random access memory (SRAM) cell. The invention is further applicable in other circuits where the gate leakage reduction is desirable or required. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its corresponding transistor without impacting the overall switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction, essentially performing a diode function. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across the device.
[0017] In the case of an SRAM cell, two complementary MOS (CMOS) inverters are cross-coupled, and the load on the inverter is a single transistor which is used for accessing the inverter. A typical prior-art circuit 100 configuration used for an SRAM is shown in FIG. 1 . The basic cell is comprised of two cross-coupled inverters, formed of transistors 130 and 135, and 140 and 145, respectively. Pass transistors 150 and 160 are used for accessing the inverters. By controlling the voltages on the gates of the pass transistors 150 and 160 by means of word line 110, it is possible to provide the data and its inverted value on the bit lines 120 and 125, respectively, or to read the data using the same bit lines. A person skilled-in-the-art would appreciate that in this circuit the load on transistors 130, 135, 140, 145, 150, and 160 is well defined in all instances of the design, a fact which is to be exploited to reduce the gate leakage in accordance with the principles of the disclosed invention.
[0018] The disclosed invention takes advantage of this property of the memory cell by using an active element to reduce the voltage on the gate of a transistor of the inverter, for example transistor 135, without impacting the switching speed of the circuit. An active element is formed by two materials having different Fermi potentials and is used as a rectifying junction or a diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device. Exemplary, but not limiting embodiments of this rectifying junction include diodes made with N+ and P+ polysilicon with large leakage across the junction, a rectifying contact with a metal layer and a N type polysilicon layer, or a P type polysilicon layer and a metal layer of appropriate ionization potential with a significant leakage through the junction. In accordance with an exemplary embodiment of the invention there is shown, without limitation, a use of junctions with leakage current between 1 nA/μm2 and 1 mA/μm2 with 1 V bias across the junction. An exemplary and non-limiting graph of the pseudo-rectifying characteristics of a diode configured in accordance with the invention is shown in FIG. 2 .
[0019] Reference is now made to FIG. 3 which shows an exemplary configuration of a NMOS transistor and a PMOS transistor, each with the diode connected to its respective gate in accordance with the disclosed invention. The diodes are designed to have a low forward drop (preferably less than 0.5 V) and a high reverse current (preferably greater than 1.0 mA/cm2). The diodes are connected in series with the gate of the respective transistor, in a direction depending on the type of the transistor. Specifically, for a NMOS transistor, the cathode of the diode is connected to the respective gate; for a PMOS transistor, the anode of the transistor is connected to the respective gate. As the transistor gate voltage increases, a fraction of the incident voltage drops across the diode and the rest drops across the gate-source junction of the respective transistor. This reduces the voltage at the gate of the respective transistor which, in turn, reduces the gate tunneling current. Referring to FIGS. 6A-6C , there are shown cross sections of NMOS (FIG. 6A ) and PMOS (FIG. 6B ) transistors with diodes manufactured in accordance with an exemplary implementation of the invention. A P-N diode or a Schottky diode may be created on the gate. In one embodiment (FIG. 6C ) a leaky oxide may be used as a leakage reduction mechanism.
[0020] Referring now to FIG. 4 , there is shown an exemplary and non-limiting SRAM cell with diodes connected to the gate of the NMOS transistors in accordance with the invention. In accordance with an embodiment of the invention, diodes 410 and 420 are connected to the gates of NMOS transistors 135 and 145, respectively. In accordance with an alternate embodiment of the invention, a similar arrangement (not shown) with diodes connected to the gates of PMOS transistors 130 and 135 is provided. In yet another embodiment of the invention, diodes are connected with the gate of NMOS transistors 135 and 145 and PMOS transistors 130 and 140. These exemplary embodiments should be considered as mere illustrations of the possibilities of connecting the diodes to the gates of the transistors of the inverters of SRAM cell 400, and any other possible combination of the diodes connected to the transistors is specifically included. A person skilled-in-the-art would readily recognize the advantages of this invention where the two inverters are connected in a feedback circuit. This arrangement and the circuit elements allow the operation of the SRAM cell with minimal impact of the operation of the circuit. Reduction in the gate voltage also results in reduced gate tunneling current, in accordance with the main teaching of the invention.
[0021] Reference is now made to FIGS. 5A and 5B where a voltage waveform of SRAM cells 100 and 400, respectively, is shown. The waveforms shown in FIGS. 5A and 5B are of simulation of the basic inverters formed by transistors 135 and 145. A pulse generator drives this circuit, and the output is measured at the common drain of transistors 135 and 145 as signals 510 and 520, respectively. FIG. 5B shows a voltage waveform at the input and output of a CMOS inverter with diode coupled gate. The voltage waveform at the gate of the NMOS transistor shows a reduced voltage swing. The drop in voltage across the diode is marked in the figure as ΔV.
[0022] The diode, for example diode 410, that is coupled to a gate of a transistor, for example transistor 135, may be realized by, but is not limited to, any one of the following implementations:
- [0023] (a) A layer of P+ polysilicon on top of N+ polysilicon, which forms the gate of the transistor to realize a P-N diode in polysilicon for NMOS;
- [0024] (b) A similar structure with polarities reversed to realize a diode in series with a PMOS gate;
- [0025] (c) A Schottky diode realized by metal—N-type polysilicon on top of N+ gate polysilicon for NMOS transistors;
- [0026] (d) A Schottky diode realized by metal—P-type polysilicon on top of P+ gate polysilicon for PMOS transistors;
- [0027] (e) A lateral N+ to P+ polysilicon diode, as described in provisional patent applications 60/585,582, filed 7 Jul. 2004, and 60/601,979, filed 17 Aug. 2004, both documents being incorporated herein in their entirety by this reference thereto; or
- [0028] (f) An MOS capacitor formed with the layers of salicide and gate polysilicon layers as the electrodes and a thin layer of oxide as the dielectric the conduction through which takes place by a tunneling effect.
[0029] While the application of the invention is described herein primarily in reference to a SRAM cell, this is done as an example of the invention, and further due to the fact that this circuit configuration is one of the most common building blocks in very large scale integration (VLSI) circuits and it presents a fixed load for the transistors. The invention is not limited to the exemplary application and other uses are to be considered an integral part of the invention.
[0030] Although the invention has been described herein with reference to certain preferred embodiments, one skilled in the art will readily appreciate that other applications may be substituted for those set forth herein without departing from the spirit and scope of the present invention. Accordingly, the invention should only be limited by the claims included below.
Claims
The invention claimed is:
1. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element and fabricated from abutting first material and second material, each of said first material and said second material having a different Fermi potential;
wherein for an NMOS transistor said second active element comprises a P—N diode in polysilicon fabricated by the step of:
adding a layer of a P+ polysilicon on top of an N+ polysilicon of the gate of said NMOS transistor.
2. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element and fabricated from abutting first material and second material, each of said first material and said second material having a different Fermi potential;
wherein for a PMOS transistor said second active element comprises a P—N diode in polysilicon fabricated by the step of:
adding a layer of an N+ polysilicon on top of a P+ polysilicon of the gate of said PMOS transistor.
3. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element and fabricated from abutting first material and second material, each of said first material and said second material having a different Fermi potential;
wherein for an NMOS transistor said second active element comprises a Schottky diode fabricated by the steps of:
applying an N-Type polysilicon on top of an N+ gate polysilicon of said NMOS transistor; and,
applying a metal layer on top of said N-Type polysilicon.
4. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element and fabricated from abutting first material and second material, each of said first material and said second material having a different Fermi potential;
wherein for a PMOS transistor said second active element comprises a Schottky diode fabricated by the steps of:
applying a P-Type polysilicon on top of a P+ gate polysilicon of said PMOS transistor; and,
applying a metal layer on top of said P-Type polysilicon.
5. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element and fabricated from abutting first material and second material, each of said first material and said second material having a different Fermi potential;
wherein fabrication of said second active element comprises the step of:
forming a lateral N+ to P+ polysilicon diode.
6. A method for forming a deep submicron circuit comprised of at least a plurality of metal-oxide-semiconductor (MOS) transistors, comprising the steps of:
fabricating a first active element;
fabricating a third active element coupled to said first active element;
fabricating a second active element coupled between said first active element and said third active element, said second active element enabled to reduce leakage current of said third active element, said second active element comprises a MOS capacitor fabricated by the steps of:
forming a first electrode and a second electrode from salicide layers and gate polysilicon layers; and
forming a dielectric from a thin layer of oxide between said first electrode and said second electrode.
7. A static random access memory (SRAM) cell with current leakage protection comprising:
a first inverter comprising a PMOS and NMOS transistors;
a second inverter comprising a PMOS and NMOS transistors, the input of the second inverter directly coupled to the output of said first inverter and the output of said second inverter directly coupled to the input of said first inverter;
a first element coupled between the gate of the PMOS transistor of said first inverter and the gate of the NMOS transistor of said first inverter, the first element enabled to reduce leakage current of the NMOS transistors of said first inverter; and
a second element coupled between the gate of the PMOS transistor of said second inverter and the gate of the NMOS transistor of said second inverter, the second element enabled to reduce leakage current of the NMOS transistor of said first inverter and said second inverter.
8. The SRAM cell of claim 7, wherein at least one of said first element and said second element comprises abutting first material and second material, each of said first material and said second material having a different Fermi potential.
9. The SRAM cell of claim 7, wherein at least one of said first element and said second element forms a rectifying junction.
10. The SRAM cell of claim 7, wherein at least one of said first element and said second element is formed over the gate of at least one of said first active element and said second active element.
11. The SRAM cell of claim 7, wherein at least one of said first element and said second element is a MOS capacitor having electrodes formed from salicide layers and gate polysilicon layers, and having a dielectric between the electrode formed from a thin layer of oxide.
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