Apparatus and method for high-voltage transient blocking using low voltage elements

[0001] The present application claims priority from provisional U.S. application 60/626,308 that was filed on 9 Nov. 2004 and is herein incorporated in its entirety.

[0002] This invention relates generally to apparatus and methods that employ a transient blocking unit (TBU) that uses a set of cascaded low-voltage elements to achieve high-voltage capability and thereby improve performance.

[0003] Many circuits, networks, electrical devices and data handling systems are operated in configurations and environments where external factors can impair their performance, cause failure or even result in permanent damage. Among the most common of these factors are over-voltage and over-current. Protection against these factors is important and has been addressed in the prior art in a number of ways, depending on the specific electronics and their application.

[0004] Fuses that employ thermal or magnetic elements are one common protection measure. In other cases, protection circuits are available. Some examples are described in U.S. Pat. Nos. 5,130,262; 5,625,519; 6,157,529; 6,828,842 and 6,898,060. Protection circuits are further specialized depending on conditions and application. For example, in the case of protecting batteries or rechargeable elements from overcharging and over-discharging one can refer to circuit solutions described in U.S. Pat. Nos. 5,789,900; 6,313,610; 6,331,763; 6,518,731; 6,914,416; 6,948,078; 6,958,591 and U.S. Published Application 2001/00210192. Still other protection circuits, e.g., ones associated with power converters for IC circuits and devices that need to control device parameters and electric parameters simultaneously also use these elements. Examples can be found in U.S. Pat. Nos. 5,929,665; 6,768,623; 6,855,988; 6,861,828.

[0005] When providing protection for very sensitive circuits, such as those encountered in telecommunications the performance parameters of the fuses and protection circuits are frequently insufficient. A prior art solution embodied by transient blocking units (TBUs) that satisfy a number of the constraints is taught in international publications PCT/AU94/00358; PCT/AU04/00117; PCT/AU03/00175; PCT/AU03/00848 as well as U.S. Pat. Nos. 4,533,970; 5,742,463 and related literature cited in these references.

[0006] Unfortunately, when high-voltage operation is required, traditional TBUs are frequently not an option because they require expensive, high-performance parts. Thus, it would be an advance in the art to reduce the expense while preserving or improving the high-voltage performance of TBUs.

[0007] In view of the above prior art limitations, it is an object of the invention to provide an apparatus and method to permit high-voltage transient blocking using inexpensive low-voltage elements. In particular, it is an object of the invention to allow the use of inexpensive, low-voltage MOSFETs to build high-voltage transient blocking units (TBUs).

[0008] It is another object of the invention to ensure that the apparatus is easy to make, low-cost and highly integrable, e.g., on the same die.

[0009] These and other objects and advantages of the invention will become apparent from the ensuing description.

[0010] The objects and advantages of the invention are addressed by an apparatus for high-voltage transient blocking employing a transient blocking unit (TBU). The TBU has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage V_p of the p-channel device and a bias voltage V_n of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. In accordance with the invention, at least one of the depletion mode n-channel device and the depletion mode p-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) connected source-to-drain.

[0011] Most commonly, it is the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs. Preferably, the set includes two low-voltage metal-oxide-silicon field effect transistors (MOSFETs) or junction-gate FETs also known as JFETs. Other types of FETs can also be used, as will be appreciated by those skilled in the art.

[0012] The set also has an arrangement for providing a bias to a gate of a first of the two MOSFETs. The arrangement has a resistor R and diode D selected such that a drain-to-source voltage V_dsT2 on the second of the two MOSFETs, a diode voltage V_dbD across the diode D and a current I_R flowing through the resistor R obey the relationship:
V_dsT2=−V_gsT2+V_dbD+I_R·R,
where V_gsT2 is a gate-to-source voltage on the second MOSFET. The diode is preferably an avalanche diode.

[0013] It is also preferable that the two MOSFETs have equal pinch-off voltages. In one specific embodiment the MOSFETs are stacked. In other words they are implemented in a merged structure with a top MOSFET stacked on a bottom MOSFET.

[0014] In accordance with a method of the invention, the TBU is interconnected as described above and it employs a set of cascaded low-voltage depletion mode FETs to achieve high-voltage transient blocking. The set is employed as the depletion mode n-channel device and is preferably made up of two low-voltage MOSFETs that have equal pinch-off or switch-off voltages. Furthermore, the low-voltage MOSFETs are preferably stacked on top of each other.

[0015] A bias is provided to the gate of the first MOSFET with the aid of an appropriate arrangement. The arrangement has resistor R and diode D chosen such that the drain-to-source voltage V_dsT2 on the second MOSFET, diode voltage V_dbD across the diode D and current I_R flowing through resistor R obey the relationship:
V_dsT2=−V_gsT2+V_dbD+I_R·R,
where V_gsT2 is a gate-to-source voltage on the second MOSFET.

[0016] A detailed description of the preferred embodiments of the invention is presented below in reference to the appended drawing figures.

[0025] The present invention and its principles will be best understood by first reviewing prior art uni-directional and bi-directional transient blocking units (TBUs) designed for over-voltage and over-current protection. The diagram in FIG. 1 shows a prior art TBU 10 for protecting a load 12 from voltage and/or current transients of one polarity, i.e., positive voltage spikes or surges. For this reason, TBU 10 is called uni-directional. TBU 10 uses a depletion mode n-channel device 14, typically an n-channel metal-oxide-silicon (NMOS) device implemented as a field effect transistor (FET). TBU 10 also uses a depletion mode p-channel device 16, typically a p-channel junction gate field effect-transistor (PJFET). It should be noted that PMOS, NJFET devices can also be used as devices 14, 16. In the example shown, both NMOS and PJFET 14, 16 are interconnected to take advantage of their n-channel and p-channel biasing and resistance properties to cause mutual switch off to block the transient.

[0026] More specifically, NMOS and PJFET 14, 16 have corresponding n-and p-channels 15, 17 as well as gate G, source S and drain D terminals. Resistances R_n, R_p of NMOS and PJFET 14, 16 are low when voltage differences or bias voltages V_gsn and V_gsp between their gate G and source S terminals are zero. Normally, TBU 10 is unblocked and both NMOS and PJFET 14, 16 act as small resistors that allow a load current I_load to pass to load 12. Application of negative bias V_gsn to NMOS 14 and positive bias V_gsp to PJFET 16 increases resistances R_n, R_p, as indicated by the arrows and turns NMOS and PJFET 14, 16 off. The interconnection of NMOS 14 with PJFET 16 source-to-source and gate-to-drain reinforces the biasing off process in response to excessive current from or associated with a transient. Specifically, as load current I_load increases PJFET 16 develops a larger voltage drop across it, thus increasing negative bias V_gsn applied to NMOS 14 and consequently increasing resistance R_n. Higher resistance R_n increases positive bias V_gsp on PJFET 16 thereby increasing R_p. Thus, the transient alters bias voltages V_gsn and V_gsp in concert such that NMOS and PJFET 14, 16 mutually increase their resistances R_n, R_p and switch off and thus TBU 10 blocks the transient.

[0027] The above principle of interconnection of n- and p-channel devices to achieve mutual switch off (sometimes also referred to as mutual pinch-off) is extended to bi-directional TBUs by using two uni-directional TBUs with one configured in reverse to block negative spikes. A simpler, bi-directional TBU 20 that protects load 12 from negative and positive spikes, is shown in FIG. 2. TBU 20 has two n-channel devices 22, 24 and one p-channel device 26. Devices 22, 24, 26 are interconnected between their gate G, source S and drain D terminals as shown. Two current limiters 28, 30 are used to ensure appropriate routing of current between devices 22, 24, 26. It should be noted that current limiters 28, 30 can be implemented by diodes, transistors, current sources or combinations thereof. TBU 20 causes mutual switch off of devices 22, 24, 26 in response to a negative or positive spike by employing the principles of controlling resistances by biasing in response to transients as explained above.

[0028] In fact, the prior art teaches a number of variants of TBUs based on the above principles. These include, among other, TBUs that use p-channel devices at inputs, a larger number of n-channel or p-channel devices as well as TBUs that employ high-voltage depletion devices. More detailed information about prior art TBUs and associated applications and methods can be found in published literature including, in particular, PCT/AU94/00358, PCT/AU04/00117; PCT/AU03/00175; PCT/AU03/00848 and U.S. Pat. No. 5,742,463 that are herein incorporated by reference.

[0029] In accordance with the invention, high-voltage capability in transient blocking is achieved by an apparatus 100, as shown in FIG. 3. Apparatus 100 uses a uni-directional TBU 102 in which the depletion mode n-channel device is no longer a single enhancement mode n-channel FET, but rather a set 104 of two cascaded low-voltage depletion mode n-channel field effect transistors (FETs) 106, 108 connected source-to-drain. Preferably, low-voltage FETs 106, 108 are MOSFETs. TBU 102 also has a depletion mode p-channel device 110, in the form of a PJFET with a p-channel 112. The interconnections between PJFET 110 and set 104 of cascaded MOSFETs 106, 108 are source-to-source and gate-to-drain to retain the switch-off characteristics of standard TBU.

[0030] Set 104 has an arrangement 114 for providing a bias to gate G terminal of first MOSFET 106. Arrangement 114 has a resistor R and a diode D selected such that a drain-to-source voltage V_dsT2 on second MOSFET 108, a diode voltage V_dbD across diode D and a current I_R flowing through resistor R obey the relationship:
V_dsT2=−V_gsT2+V_dbD+I_R·R,
where V_gsT2 is a gate-to-source voltage on second MOSFET 108. The diode is preferably an avalanche diode.

[0031] In some embodiments MOSFETs 106, 108 have equal pinch-off or switch-off voltages. This may be most practical when MOSFETs 106, 108 come from the same wafer and thus can be made in higher volume. It should be noted, however, that set 104 can just as well us cascaded MOSFETs 106, 108 that have vastly different pinch-off voltages. Such situation only requires adjustment of the breakdown voltage of avalanche diode D.

[0032] During operation, TBU 102 of apparatus 100 achieves high-voltage transient blocking of positive surges (over-current or over-voltage). That is because set 104 of low-voltage MOSFETs 106, 108 employed as the depletion mode n-channel device behaves like a high-voltage n-channel device sufficiently well for the purposes of TBU 102. In particular, TBU 102 current leakage requirements are not stringent, and thus permit cascaded set 104 of low-voltage MOSFETs 106, 108. That is because despite their considerable current leakage, on the order of milliamps in the off state, cascaded MOSFETs 106, 108 can block large voltages. As a result, set 104 of cascaded MOSFETs 106, 108 operates as an effective single cascade transistor with source terminal S of MOSFET 108 acting as the source of entire set 104 and gate terminal G of MOSFET 108 acting as the gate of entire set 104. A critical condition of operation is that the avalanche voltage of diode D be less than the breakdown voltage of MOSFET 108.

[0033] MOSFET 108 is controlled by bias voltage V_gsT2 applied to its gate terminal G. If, during operation the drain-to-source voltage V_dsT2 across second MOSFET 108 rises to a point where diode D begins to conduct through resistor R, then a voltage will be generated across R. This voltage will provide a bias voltage to gate terminal G of first MOSFET 106. This bias voltage will effectively hold the voltage at source terminal S of first MOSFET 106 in accordance with the following relationships:
V_dsT2=−V_gsT2+V_dbD+I_R·R, as
I_R·R<V_poT2; and V_gsT2<V_poT2, then
V_dsT2<−V_poT2+V_dbD+V_poT1,
where the subscript po denotes pinch-off and subscripts T1, T2 stand for first and second MOSFETs 106, 108, respectively. Now, if both MOSFETs 106, 108 have the same pinch-off voltage, as is reasonable if both FETs are of the same design, then:
V_dsT2<V_dbD.
Therefore, as long as V_dbD of diode D is selected correctly, then arrangement 114 will ensure that V_dsT2 across second MOSFET 108 never exceeds the breakdown voltage of second MOSFET 108. Therefore, the total breakdown strength of the cascade of set 104 is the breakdown strength of first MOSFET 106 plus V_dbD of diode D. As such, set 104 operates as a single 3 terminal device with characteristics equivalent to those of second MOSFET 108 except with improved breakdown voltage. In this manner, the advantage of high-voltage transient blocking operation of TBU 102 is secured with inexpensive, low-voltage MOSFETs 106, 108. This is also because the maximum gate voltage that can now be applied to PJFET 110 is higher. In addition, set 104 is easy to make, low-cost and highly integrable, since it is placed on the same die and simply replaces the former single depletion mode n-channel device.

[0034] Now, set 104 can also be used in a bi-directional TBU 120, as illustrated in FIG. 4. TBU 120 has first and second depletion mode n-channel devices 122, 124, as well as a depletion mode p-channel device 126. Devices 122, 124, 126 are interconnected as described above to achieve switch-off to either positive or negative transients. TBU 120 also employs two current limiters 128, 138, here in the form of diodes, to ensure proper current flow.

[0035] In accordance with the invention, first depletion mode n-channel device 122 is replaced by set 104 of cascaded MOSFETs 106, 108 as indicated by the arrow. It should be noted that set 104 can also be used to replace second depletion mode n-channel device 124 if desired. The operation of TBU 120 is analogous to a prior art bi-directional TBU, except that it now has a high-voltage capability it did not possess before afforded by low-cost, low-voltage MOSFETS 106, 108.

[0036] FIG. 5 is a diagram of an alternative set 130 of two cascaded NMOS devices 132, 134 according to the invention that can be employed in the above uni-directional TBU 102 or bi-directional TBU 120, or still other uni- and bi-directional TBUs requiring low-cost, high-voltage operation. In contrast to the previous embodiment, a resistor R2 is used in place of the avalanche diode D in a bias arrangement 136. Also, the pinch-off of the second device 132 is raised to a level just below the breakdown voltage of first device 134. In this way the action of the avalanche diode D from the last embodiment, i.e., that of offsetting the gate drive of device 132 to a level that permits it to act only when the breakdown voltage of inner device 134 is approached, can be imitated and a cascade of low voltage devices can be used to make a device which performs as a high voltage device. Of course, set 130 can be used in any of the above TBUs or still other TBUs to replace one or more depletion mode n-channel devices.

[0037] FIG. 6 is a diagram of still another alternative set 140, which uses first and second NMOS devices 142, 144 and a bias arrangement 146 that is analogous to bias arrangement 114. As before set 140 can be used in any TBU. It should also be understood, that the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs can take advantage of various specific types of FETs. This is true for any of the above embodiments. For example, the set can include low-voltage MOSFETs or junction-gate FETs also known as JFETs or still other of FETs, as will be appreciated by those skilled in the art.

[0038] When implementing any of the above embodiments in practice, it is preferred, for reasons of size and efficiency to integrate sets of cascaded FETs. For example, as shown in FIG. 7, two MOSFETs 106, 108 of set 104 can be stacked on top of each other in a merged structure 150. First MOSFET 106 is the top MOSFET and it is stacked on second MOSFET 108, which becomes the bottom MOSFET.

[0039] Stacked device or merged structure 150, as shown in FIG. 7, is obtained through vertical integration of devices 106, 108. A bottom N-epi layer 152 is the outer high-voltage contact with the n+ connected to the input/output of the TBU. The p-channel of the device is the p-layer between the upper and lower N-epi layers. The source of the outer device or bottom device 108 is a N+ thin buried layer 154 which is also the drain contact of the top (inner part of the cascade) device 106. A top surface 156 is the standard source, channel and gate region of device 106.

[0040] Note that the channel region of outer device 108 can be formed from lateral trenches 158, 160. Lateral doping of the channel can be obtained by partially filling trenches 158, 160 on each side and applying lateral doping techniques such as, for example, tilted implants or vapor phase doping, or diffusion from solid or gas sources.

[0041] Top MOSFET 106 can have a low pinch-off voltage (V_po), by using special depletion implant in its gate oxide. The special implant can be Cs, K, Na or other implants familiar to those skilled in the art. The purpose of implantation is to add charge to the oxide. Other techniques involve using shallow N-type dopants to form a conductive channel in the silicon under the gate oxide, which can be depleted as the gate voltage becomes more and more negative (for an NMOS device).

[0042] Bottom MOSFET 108 has a very thick gate oxide, and uses an implanted dopant to form the conductive n-channel (at V_gs=0V). For example, the N-type dopant can be arsenic, phosphorus or antimony. The gate of bottom MOSFET 108 is connected with deep trenches 158, 160 that may have more than one level, and can be connected at different portions. Advantageously, bias arrangement 114 can be integrated in merged structure 150 by using the available doped junctions. Structure 150 can be made by using multiple epi depositions.

[0043] Stacked devices 106, 108 can be formed by a multiple growth on an N+ substrate 162. The layers and their associated parameters can chosen as follows:

• [0044] 1) N+ substrate;
• [0045] 2) N− epi 1 for outer high-voltage device thickness and doping dependent on breakdown voltage;
• [0046] 3) p-channel region (1-5 μm, P-type, 1×10¹⁶ to 1×10¹⁸ depending on pinch-off, punch-through and other requirements);
• [0047] 4) N+ source of bottom FET 108, between 1×10¹⁷ to 1×10¹⁹, 0.2 to 2 μm thick, N-type arsenic or antimony for low diffusion rate; and
• [0048] 5) N− epi 2 for inner high-voltage device.

[0049] Top processing is a standard VDMOS process, with a self-aligned channel formed by implanting and diffusion of boron after the poly gate is patterned. The channel of the outer (lower) FET 108 can be formed by filling to the trench to the top of the bottom epi. Then, the sidewall is doped to form the N− region on the desired side of the P-type channel epi layer. One then proceeds by:

• [0050] 1) growing or depositing the thick gate oxide of the outer (bottom) FET;
• [0051] 2) refilling with poly to protect that region;
• [0052] 3) etching the sidewall of the trench to form the gate of the bottom FET;
• [0053] 4) (optional) etchback of the poly up to the N+ buried layer of the top FET;
• [0054] 5) (optional) etch to remove the sidewall N-type doping;
• [0055] 6) oxidation of the trench sidewall again followed by filling of the trench.

[0056] FIG. 8 illustrates another set of two cascaded FETs 172, 174 stacked on top of each other in a merged structure 170. Merged structure 170 has an integrated Schottky diode formed in the trench region surrounding the vertically arranged FETs 172, 174. FIG. 8 also shows that it is possible to terminate the partial fill of the trenches to have access to some of the layers grown in the epi “stack”, as may be useful for integrating the various possible biasing arrangements into the set of cascaded FETs 172, 174. For example, a contact to the drain of the top NMOS can be made using a partial trench fill, sidewall etching and poly deposition to contact the desired layer.

[0057] Many other embodiments of the apparatus as well as the method are possible, as will be evident to those skilled in the art. Therefore, the scope of the invention should be judged by the appended claims and their legal equivalents.