US 7,645,696 B1Grant

Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer

Issue Date:2010-01-12

•24 Claims

•10 Drawing Sheets

Abstract

Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.

Metadata

Assignee

Novellus Systems, Inc.

Inventors

Alexander Dulkin
Anil Vijayendran
Tom Yu
Daniel R. Juliano

Application Information

Application Number:US 11/473,618

Filing Date:2006-06-22

Priority Date:2006-06-22

Art Unit:2829

Classifications

IPC:

H01L21/00

Patent Drawings (10 sheets)

Description

Field of the Invention

[0001] The present invention pertains to methods for forming a metal seed layer on a barrier layer of a partially fabricated integrated circuit.

Background of the Invention

[0002] Damascene processing is a method for forming interconnections on integrated circuits that involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). The metal conductive lines are formed by an electroplating process. Because copper or other mobile conductive material provides the conductive paths of the integrated circuit, the underlying silicon devices must be protected from metal ions (e.g., Cu²⁺) that might otherwise diffuse or drift into the silicon. Suitable materials for diffusion barrier include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and the like.

[0003] After diffusion barrier is deposited and prior to electroplating, a seed layer of copper or other metal is typically applied by a physical vapor deposition (PVD) process to enable subsequent electrofilling of the features with copper inlay. In order to serve as a seed for electroplating, the seed layer should be continuous, stable and have good adhesion to the barrier layer.

[0004] One difficulty with depositing seed layers is that the copper (or other metal) may agglomerate on the barrier layer surface. This phenomenon occurs because of the weak chemical bond between seed and the barrier as a result of the absence of an intermetallic reaction between the two. High oxidation ability of the barrier aggravates this phenomenon. Because of this agglomeration, the copper may not cover the surface in a conformal manner. The thickness of the seed layer coverage is thus uneven, thicker in some places than others, and the layer may include gaps. Such seed layers do not provide a uniform layer for electroplating, which leads to voiding defects in the electroplated copper. Another difficulty is the formation of “overhang” material on the edges of the features. Diffusion barrier overhang, for example, can prevent seed metal deposition flux from reaching the top sidewalls of the features. This phenomenon also leads to seed layers having poor continuity. Defects, poor continuity and poor adhesion of the seed layer all may adversely affect performance of the fabricated device. For example, defects in the seed layer may result in electromigration and stress migration at the seed-barrier interface. Void formation in the electrofilled copper features and subsequent post CMP defects are other consequences of poor seed layer formation that may also lead to device failure.

[0005] What are therefore needed are methods of depositing metal seed layers on diffusion barriers that provide seed layers having improved continuity and adhesion to the underlying diffusion barrier.

Summary of the Invention

[0006] The present invention meets these needs by providing methods of depositing seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer. According to various embodiments, the methods involve performing a sputter etch in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. In some embodiments, a small deposition flux accompanies the sputter etch flux, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.

[0007] One aspect of the invention relates to a method of depositing a metal conductive seed layer on a substrate that involves the operations of a) providing a substrate having a barrier layer deposited thereon to a seed layer deposition chamber; b) performing an inert gas sputter etch of the barrier layer in the seed layer deposition chamber; and c) depositing the metal conductive seed layer over the surface of the wafer substrate in the seed layer deposition chamber.

[0008] According to various embodiments, the sputter etch operation may remove barrier material that overhangs a recessed feature (e.g., a trench or via) on the substrate and/or remove oxide that has formed on the barrier layer. In some embodiments, the method involves simultaneously sputtering metal from a target while performing the sputter etch of the barrier material. The metal atoms may then become embedded in the barrier layer surface to provide nucleation sites for the seed layer deposition in (c). In certain embodiments performing operation (b) involves applying a DC power of between about 0 and 10 kW to the target and a RF power of at least about 100 W, e.g. between about 100 and 3000 W, to the substrate.

[0009] Another aspect of the invention relates to a method of depositing a metal seed layer on a semiconductor substrate having recessed features that involves a) providing the substrate with a barrier layer deposited thereon to the seed layer deposition chamber; b) applying a DC power to a metal target within the chamber and a RF bias to the substrate to simultaneously etch barrier layer oxide and implant metal atoms into the barrier layer; and c) applying a DC power to the metal target to deposit a metal seed layer that substantially coats the sidewalls of the features, wherein the implanted atoms are nucleation sites for the deposition of the metal.

[0010] These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.

Brief Description of the Drawings

[0011] FIGS. 1A-1H show cross sectional depictions of device structures created during a dual Damascene fabrication process.

[0012] FIGS. 2A-D shows cross sectional depictions of barrier layer overhang of a feature and resulting metal seed film and electrofilled feature. FIG. 2A depicts the cross sectional depiction of barrier layer overhang; FIG. 2B depicts the subsequently deposited metal seed layer; and FIGS. 2C and 2D depicts the electrofilled feature containing various types of voids.

[0013] FIG. 3 is a process flow diagram illustrating relevant operations employed to form conductive lines by Damascene processing according to various embodiments of the present invention.

[0014] FIG. 4 is a cross-sectional depiction of a hollow cathode magnetron (HCM) apparatus suitable for practicing the current invention.

[0015] FIGS. 5A and 5B are images of a structure having a barrier layer deposited thereon. FIG. 5A shows the structure prior to barrier layer etchback, and FIG. 5B shows the structure after an etchback was performed.

Detailed Description

[0016] In the following detailed description of the present invention, numerous specific embodiments are set forth in order to provide a thorough understanding of the invention. However, as will be apparent to those skilled in the art, the present invention may be practiced without these specific details or by using alternate elements or processes. In other instances well-known processes, procedures and components have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

[0017] In this application, the term “wafer” will be used interchangeably with “partially fabricated integrated circuit.” One skilled in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. The term “substrate” is also used and includes wafers.

[0018] This invention relates to deposition of metal seed layers on diffusion barrier layers. Methods of the invention involve performing a sputter etch operation (also referred to as an etchback operation) in the seed deposition module prior to deposition of the seed layer. According to various embodiments, the sputter etch operation results in one or more of the following: 1) reduction or elimination of oxide formed on the barrier, 2) reduction or elimination of barrier layer overhang at the tops of features, and 3) activation of the barrier surface before seed deposition (e.g., by creating nucleation sites).

[0019] Advantages of reducing barrier layer overhang include reduction or elimination of subsequent seed overhang, decrease of preplating aspect ratio, reduction of barrier layer thickness variation within the features and between features, and reduction of copper seed thickness variation within the features and between features. This leads to void free electroplating and reduction in post CMP defects. Advantages of reducing barrier oxide include improved seed-barrier adhesion and reducing line and contact resistance. Advantages of creation of nucleation sites in the barrier layer include increased nucleation density, improved seed layer morphology, improved seed layer continuity and improved seed-barrier adhesion. Improved film continuity and adhesion reduces electromigration along the barrier/seed interface, as well as stress migration. This in turn improves device reliability. The sputter etch or etchback operation also decreases barrier layer roughness, especially on sidewalls, which in turn improves the continuity and smoothness of the seed layer.

[0020] As mentioned, the invention finds particular use in Damascene processing. FIGS. 1A-1F show cross sectional depictions of device structures created at various stages of a dual Damascene fabrication process, with the cross sectional depiction of a completed structure created by the dual Damascene process is shown in FIG. 1H. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual Damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as fluorine or carbon doped silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which a diffusion barrier 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive material provides the conductive paths of the integrated circuit, the underlying silicon devices must be protected from metal ions (e.g., Cu²⁺) that might otherwise diffuse or drift into the silicon. For purposes of discussion, this application may refer to copper conductive lines and seed layers; however one of skill in the art will understand that methods of the invention may be applied to seed layer deposition of other types of conductive materials (e.g., aluminum).

[0021] Suitable materials for diffusion barrier 105 include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and the like. In a typical process, barrier 105 is formed by a physical vapor deposition (PVD) process such as sputtering, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in Damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit 100 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1H.

[0022] As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual Damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.

[0023] The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual Damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.

[0024] The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.

[0025] Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a diffusion barrier 123. As mentioned above, barrier 123 is made of tantalum, or other materials that effectively block diffusion of copper atoms into the dielectric layers.

[0026] After diffusion barrier 123 is deposited, a seed layer of copper is deposited to enable subsequent electrofilling of the features with copper inlay 125 as shown on FIG. 1G. The blanket layer of electrodeposited copper is removed by chemical mechanical polishing (CMP) leaving the conductive material only inside the features. FIG. 1H shows the completed dual Damascene process, in which copper conductive routes 125 are inlayed (seed layer not depicted) into the via and trench surfaces over barrier 123.

[0027] Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated only by diffusion barrier 123, which is also somewhat conductive.

[0028] As indicated above, the present invention relates to deposition of seed layers on diffusion barriers. Although FIGS. 1A-1H illustrate a dual Damascene process, one of skill in the art will recognize that the methods of the present invention may be used with other process flows, including single Damascene processes.

[0029] Diffusion barriers may be deposited by PVD, CVD or ALD methods. PVD methods result in high quality films, though conformal methods, including ionized-PVD (iPVD), CVD and ALD methods may be used to improve step coverage of the recessed features and reduce overhang of barrier material on the top edges of the features. Regardless of the method used to deposit the diffusion barrier, subsequent barrier oxide formation may significantly and adversely affect copper seed deposition. Barriers, such as tantalum-based barriers, readily oxidize. Even in a high vacuum environment, the time it takes to move the barrier-coated wafer from one module to another (e.g., from a PVD barrier module to a PVD copper seed module) is enough for oxygen to attach itself to the any free Ta bonds (or other barrier material) on the barrier layer surface. The barrier oxide bonds may be strong, thereby making the barrier less attractive to the metal seed layer. The resulting poor adhesion and film discontinuities may result in instability of the seed layer in the plating bath.

[0030] As indicated, barrier deposition, especially PVD barrier deposition, may result in barrier material overhang. FIG. 2A shows an example of a diffusion barrier 203 in which material overhangs a recessed feature. Diffusion barrier overhang results in poor sidewall coverage for the subsequent metal seed layer deposition, because it effectively filters the deposition flux having incident angles that reach the sidewall. This overhang results in metal seed layer overhang and prevents metal seed deposition on the sidewall from the beginning of the deposition process. An example of this is shown in FIG. 2B, in which seed layer 205 also overhangs the feature and is thin and/or has gaps in coverage along the sidewall due to the barrier layer overhang. Overhang of the seed layer can lead to void formation as the electroplated metal closes off the feature at the opening before the feature is filled. FIG. 2C illustrates this, showing void 207 in the electroplated metal 209 (barrier and seed layers are not depicted in FIG. 2C). Voids may lead to improper operation and/or device breakdown. The smaller the feature opening is before electrofilling, the more likely that voids will be present. The other highly probable place for void formation is immediately underneath the barrier overhang, where seed to barrier adhesion is compromised due to lack of seed coverage. FIG. 2D shows voids 211 under barrier layer 203. These voids might serve as the nucleation sites for stress migration failures and/or post CMP defects.

[0031] The methods of the present invention provide improved methods of forming metal seed layers on diffusion barriers. FIG. 3 is a process flow diagram illustrating relevant operations employed to form conductive lines by Damascene processing according to various embodiments of the present invention.

[0032] The process begins at operation 301 in which a barrier layer is formed on features on the partially fabricated semiconductor substrate. Various processing operations, as described above in the context of FIGS. 1A-1H, may have been performed prior to barrier layer formation. As discussed above, the barrier layer may be formed by any suitable method including PVD, CVD and ALD methods. In a particular example, the barrier layer is deposited by a PVD process. As discussed above, PVD processes may be preferred in some applications to deposit high quality, low-resistance films. Suitable barrier layer materials include, but are not limited to, tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and combinations of these.

[0033] In operation 303, the substrate is transferred to the metal seed deposition module or chamber. The metal seed deposition module is a vacuum chamber that is capable of depositing the metal seed layer. In some embodiments, a suitable PVD apparatus employs a magnetic array for electron confinement to generate a high density plasma. The magnetic array may be implemented as one or more electromagnets, permanent magnets, or some combination of electromagnets and permanent magnets. The apparatus may include other magnets located proximate the substrate region for promoting process uniformity.

[0034] Examples of suitable apparatuses include hollow cathode magnetron (HCM) sputtering modules. Such apparatuses are described in further below as well as in U.S. Pat. Nos. 5,482,611; 6,179,973; 6,193,854; and 6,217,716, each of which is incorporated herein by reference for all purposes. Other types of sputtering apparatuses that may be used in accordance with the invention include planar magnetron sputtering modules. If the seed layer to be deposited is copper, a copper target source is used. Also, as described below, the apparatus typically employs a RF biased electrostatic chuck pedestal, which secures the wafer and applies an RF bias on the wafer, if needed.

[0035] After transfer to the metal seed deposition module, a sputter etch is performed to remove oxide and/or overhang from the diffusion barrier in operation 305, prior to the main metal seed deposition operation, which occurs in operation 307.

[0036] In conventional PVD processes, metal seed layer deposition occurs directly after the substrate is transferred to the copper PVD chamber. An inert gas is introduced to the chamber to form a plasma, the energetic ions of which bombard and eject copper atoms from the target to deposit on the substrate. In the method shown in FIG. 3, sputter etch is performed in the metal seed PVD module, prior to the main seed deposition. In certain embodiments, the sputter etch removes barrier layer oxide, which as explained above improves metal seed-barrier layer adhesion. Performing the sputter etch in the metal seed PVD module (rather than, for example, in a barrier layer PVD module) ensures that oxide formation will not occur between the sputter etch and metal seed layer deposition.

[0037] As indicated above, the sputter etch removes barrier oxide that has formed prior to the etchback. This improves the continuity and adhesion of the seed layer. If diffusion barrier overhang is present, the sputter etch also removes the overhang material. As indicated above, PVD deposition of diffusion barrier tends to produce films with overhang. The etch operation decreases the preplating aspect ratio, thereby decreasing the likelihood of void formation during electroplating. The etchback operation also reduces feature roughness, particularly on the sidewalls.

[0038] Process conditions during the sputter etch and metal seed deposition (operations 305 and 307, respectively, in FIG. 3) are such that there is a net etch in operation 305 and net deposition in operation 307. Etch/deposition (E/D) ratios for every step may be controlled by tuning the power to the source as well as the RF bias that may be applied to the substrate, as E/D ratio depends predominantly on the ratio of RF power (pedestal) to DC power (source).

[0039] In general, etch rate is most strongly related to the RF power, while the deposition rate is most strongly related to the DC source power. Higher RF/DC power ratios correspond to higher E/D ratios on the wafer, which can go to infinity if no DC power is applied to the target. Pure etching is achieved in this case. The etch rate is largely dependent on RF power and pressure since these parameters control the energy of argon ions near the wafer. The deposition rate is largely dependent on DC power since this parameter affects the flux and energy of argon ions near the sputter target.

[0040] As indicated, during the etchback step the combination of DC power applied to the target and RF power applied to the wafer has to ensure the net material removal from the wafer. For example, for HCM modules having target areas of between about 1000-6000 cm². DC power should be in the range from 1 kW to 10 kW or as low as 0 as indicated above for the pure etching. One of skill in the art will understand that this range depends on the target area, and can be different for smaller or bigger targets especially if the method is used with the different source/target design. The RF power may be between about 100 W to 3000 W for a typical substrate (e.g., a 300 mm wafer). This range depends on the wafer area and can be much greater for applications that deal with big substrates. In terms of power density (independent of the target area or substrate area), examples of suitable DC power ranges for the sputter etch operation are range from about 0 W/(cm²target) to 5 W/(cm²target) and for the RF power, from about 0.1 W/(cm²substrate) to 5 W/(cm²substrate).

[0041] After the sputter etch in operation 305, the metal seed layer is deposited in operation 307. Process conditions in operation 307 are such that there is a net deposition, rather than a net etch as in operation 305. Examples of suitable DC power ranges for the seed layer deposition operation are range from about 5 W/(cm²target) to 25 W/(cm²target), and, for the RF power, from about 0 W/(cm²substrate) to 0.5 W/(cm²substrate). PVD deposition of metal seed layers is described in U.S. Pat. Nos. 6,905,959; 6,773,571; and 6,642,146, which patents are hereby incorporated by reference and for all purposes. After the seed layer is deposited, the recessed features are filled with the conductive metal by electroplating in an operation 309.

[0042] In certain embodiments, it is desirable for the inert gas sputter flux in operation 307 to be accompanied by a small deposition flux. In typical HCM operation mode the pedestal capacitive RF discharge feeds on electrons created by the source at relatively low DC power (e.g., 0.1 W/(cm²target)−5 W/(cm²target)). Thus, the strong flux of argon or other inert gas ions to the wafer is accompanied by the small flux of copper (or other metal) species to the wafer. As a result, copper atoms are embedded into the barrier surface. These embedded atoms create nucleation centers for the subsequent seed layer deposition in operation 307. The copper atoms may be embedded to the depth of a few lattice constants from the surface into the barrier, depending on their energy. These nucleation centers promote seed film growth, film stability and improve the seed-barrier adhesion. Nucleation density during seed layer deposition also increases. The increased nucleation density results in film having less stress and better crystallographic orientation and texture. The feature edge roughness decreases.

[0043] It should be noted that while the sputter etch and metal seed layer deposition operations occur in the same chamber in the process illustrated in FIG. 3 (so that oxide will not form between the operations and/or to activate the barrier layer surface), in certain embodiments, the etchback operation may be performed outside the copper deposition module to remove overhang.

[0044] In a particular embodiment, tantalum-based barriers are used for copper metallization (e.g., a TaN/Ta/Cu stack). Tantalum-based barriers are particularly useful as barriers in copper metallization due to the absence of tantalum-copper intermetallic reactions, which means that the copper-tantalum interface is stable. However, this lack of chemical bonds in the interface also means that copper-tantalum adhesion may be a problem under conventional deposition processes described above (although copper does have relatively better adhesion to tantalum compared to many other materials considered for their barrier properties).

[0045] As a result copper agglomerates on the tantalum surface at elevated temperatures (as the copper-copper bond is stronger than the tantalum-copper bond). Because of this, the copper seed deposition is typically conducted at low substrate temperatures to suppress agglomeration by “freezing” the deposited copper atoms in place where they are adsorbed. Low temperature deposition reduces adsorbed atom mobility, thereby decreasing agglomeration and increasing nucleation density. However, the film quality is not as good as it would be if the film is grown at thermodynamic equilibrium conditions. As a result film grown at low temperature conditions is stressed. Copper dewetting at the interface and void formation usually accompanies the subsequent stress relaxation at higher temperature anneal processes. Seed layer deposition on tantalum by conventional methods may also present difficulties because tantalum oxidizes very easily. The tantalum oxide bond is strong, making the surface less attractive to subsequent copper seed deposition.

[0046] As indicated, the methods of the present invention may be used to improve copper seed deposition on tantalum-based barriers by allowing the copper seed to be deposited on an oxide-free surface thereby improving adhesion, and increasing nucleation density, thereby improving film continuity, reducing film stress, and as a result reducing post CMP defects as well as stress migration and electromigration at the Ta—Cu interface. In certain embodiments, the temperature at which the copper seed layer is deposited may be higher than the low temperatures at which the seed deposition typically occurs, resulting in improved adhesion and reduced stress in the film. For example, deposition temperatures ranging from about 2° C. to about 100 Cmay be used. One of skill in the art will recognize that the various benefits discussed above with regard to Ta-based/Cu stacks may also apply to various other barrier layer-seed layer combinations.

Apparatus

[0047] As indicated above, any suitable deposition apparatus appropriate for performing the sputter etch and metal seed deposition operations may be used, including PVD apparatuses that use hollow cathode magnetron (HCM) or planar magnetron targets.

[0048] FIG. 4 presents a simple cross sectional view of one type of HCM sputtering apparatus that can be used in accordance with the invention. The HCM apparatus has two main components, the source 401, in which plasma is created and maintained, and the RF bias electrostatic chuck (ESC) pedestal 403, which secures the wafer and applies an RF bias on the wafer, if needed. In this specific example, the source 401 contains four electromagnets 405a-405d, a cathode target 407 and an anode 409. The cathode target 407 generally has a hollow cup-like shape so that plasma formed in the source can be concentrated within this hollow region. The cathode target 407 also serves as a sputter target and is, therefore, made of a metal material such as copper or aluminum, which is to be deposited onto a substrate.

[0049] An inert gas, such as argon, is introduced to into the hollow region of the cathode target 407 to form plasma. An intense magnetic field is produced by electromagnets 405a-405d within the cathode target region. Additional electromagnets are arranged downstream of the cathode target so that different currents can be applied to each electromagnet, thereby producing an ion flux and a controlled deposition and/or etch rate and uniformity. A metal spacer 409, typically held at plasma floating potential, is used, in conjunction with the source electromagnets to shape the plasma distribution at the target mouth. The RF bias ESC pedestal 403 holds the wafer substrate in place and can apply a RF bias to the wafer substrate. The ion energy, and therefore the deposition and/or etch rate can also be controlled by the pedestal RF bias. Typically, the amount of sputtering is controlled by the RF power at fixed RF frequency. Various RF frequencies can be used to achieve this effect. One preferred RF frequency is 13.56 MHz. An additional function of the ESC pedestal is to provide wafer temperature control during sputter etch and deposition. Typically, argon backside gas is used to provide thermal coupling between the substrate and the ESC. In many cases, the ESC is cooled during deposition.

[0050] As well, various aspects of process flows involve deposition of barrier materials (by ALD, CVD or PVD) as well as precleaning, and degassing operations. In these embodiments all these process steps are done in the same processing tool. Tools that allow degas, ALD or CVD deposition, and PVD deposition all under the same vacuum are the INOVA and INOVA NExT deposition systems available from Novellus Systems of San Jose, Calif. These systems are comprised of processing modules, e.g. for Degas, Cool, Preclean, PVD, CVD or ALD processes, mounted to the same wafer handling module. Therefore, once a wafer is in the tool and a vacuum is established, all of the above described process aspects are performed. In particular embodiments, the barrier layer deposition occurs in a tantalum (or other barrier material) PVD deposition module, with the wafer then transferred to the metal seed PVD deposition module for sputter etch and metal seed deposition.

Process Conditions

[0051] As discussed above with regard to FIG. 3, the RF bias power and DC source power are important process conditions to control sputter etch and metal seed deposition operations.

[0052] During the sputter etch operation, DC power typically ranges from about 0.5 W/(cm²target) to 5 W/(cm²target), but it could be as low as 0 for the pure etching , and RF power, from about 0.1 W/(cm²substrate) to 5 W/(cm²substrate). DC power is typically higher during the deposition operation than for the sputter etch operation. DC power typically ranges from about 15 W/(cm²target) to 25 W/(cm²target), and RF power, from about 0 W/(cm²substrate) to 0.5 W/(cm²substrate) for the deposition step.

[0053] Plasma reactors that allow fine control of the plasma conditions can be tuned to provide the E/D variations over substrate topology as may be desired. For example, the INOVA HCM reactors provided by Novellus Systems have eight or more separate electromagnetic coils. Fine tuning the E/D profile from via bottom to field region and from the center to edge across of the wafer by independently controlling each of these coils is described in U.S. Pat. No. 6,764,940, which is hereby incorporated by reference.

[0054] Other process conditions include temperature, pressure and inert gas flow rate. Temperatures typically range from about −40 C to 50 C for both the sputter etch operation and for the deposition operation. As discussed above, conventional copper seed deposition operations use very low substrate temperatures (e.g., less than about 50 C) in order to reduce adsorbed atom mobility. In certain embodiments, methods of the present invention may use higher substrate temperatures during seed deposition, thereby decreasing film stress. Pressures typically range from about 1E−3 Torr to 1E−2 Torr for the sputter etch operation and about 5E−5 Torr to 5E−3 Torr for the deposition operation, and argon flow rates range from about 10 sccm to 200 sccm for the sputter etch operation and about 0 sccm (gas-free operation) to 20 sccm for the deposition operation. One of skill in the art will understand that these are exemplary ranges that may be need to be adjusted depending on the substrate and apparatus used.

Experimental

[0055] TaN/Ta barriers were deposited by PVD on wafers using INOVA xT deposition systems available from Novellus Systems of San Jose. The barriers were deposited in trenches of 100 nm. After barrier deposition the wafers were transferred to the copper deposition PVD module. An etchback process was performed in the copper deposition module, prior to deposition of the copper seed layer.

Resistivity

[0056] Resistivity drift of the deposited Cu film over time is an indication that the film undergoes a re-crystallization process. The more the drift the more stressed film was deposited. Such a film is more likely to relieve the stress over time, which leads to microvoid formation and subsequently failures related to stress-migration or electro-migration mechanisms. Film deposited on the barrier without an air break has a relatively small resistivity drift of 4% over a long time. If there is an air break after Ta deposition, the barrier oxidizes and subsequently deposited Cu film has a resistivity drift of 14% over time.

[0057] Such an oxidized barrier was subjected to the etchback step in the copper module before copper deposition. Resistivity drift of the Cu film was reduced back to 4%-showing that the effects of barrier oxidation were eliminated and the barrier-seed interface became stable again. The etchback step was performed using a DC power of 0.6 W/cm²and a RF power of 1.2 W/cm²for 10 s.

Elimination of Overhang

[0058] FIG. 5A is an image showing the barrier layer formation 501 observed on the wafer after barrier deposition (prior to any etchback process). As can be seen from the figure, barrier layer overhang is present and notches the tops of the feature, creating an umbrella-like shape. FIG. 5B shows the barrier layer observed after the proposed etchback. As can be seen from the figure, the barrier overhang notch is eliminated. Barrier material at the corners of the top of the features is clipped. The bottom of the barrier is intact after the etchback.

[0059] Process conditions for the sputter etch are given below. For comparison, process conditions used for subsequent copper seed layer deposition are also shown.

[0060]


	DC Power	RF Power	Ar Flow	Pressure	Temperature
	(kW)	(W)	(sccm)	(Torr)	(° C.)


Etch	1.5	900	130	4.00E−3	−40
Deposition	70	0	4	1.00E−4	−40

As discussed above, the etch step uses a significantly higher RF power and lower DC power as compared to the etch step. In addition, pressure is significantly higher. Both these factors lead to the higher plasma density in vicinity of the wafer compare to the target area and controlled bias on the wafer to achieve high E/D ratio.

[0061] Although various details have been omitted for clarity's sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.

Claims

What is claimed is:

1. A method of depositing a metal conductive seed layer on a substrate comprising:

a) providing a substrate having a barrier layer in a recessed feature deposited thereon to a seed layer deposition chamber;

b) performing an inert gas sputter etch of at least the sidewalls of the barrier layer in the seed layer deposition chamber;

c) depositing the metal conductive seed layer over the surface of the wafer substrate in the seed layer deposition chamber.

2. The method of claim 1 wherein the sputter etch removes barrier material that overhangs the recessed feature on the substrate.

3. The method of claim 1 wherein the seed layer is a copper seed layer.

4. The method of claim 1 wherein the barrier layer comprises tantalum.

5. The method of claim 1 further comprising simultaneously sputtering metal atoms from a target while performing the sputter etch of the barrier material.

6. The method of claim 5 wherein the metal atoms become embedded within the barrier layer during the sputtering process.

7. The method of claim 6 wherein the embedded metal atoms are nucleation sites for the seed layer deposition in (c).

8. The method of claim 1 wherein (b) comprises sputtering a metal from target having an applied DC power of between about 0 and 10 kW while applying a RF bias to the wafer substrate.

9. The method of claim 1 wherein (b) comprises applying a RF bias of at least about 100 W to the substrate.

10. The method of claim 1 wherein the seed layer deposition chamber comprises a HCM.

11. The method of claim 1 wherein the seed layer deposition chamber comprises a planar magnetron.

12. The method of claim 1 wherein further comprising, prior to (a), depositing the barrier layer on the substrate.

13. The method of claim 1 further comprising electroplating metal on the seed layer.

14. The method of claim 1 wherein the barrier layer provided in (a) has oxide formed thereon and wherein at least some of said oxide is removed during (b).

15. A method of depositing a metal seed layer on a semiconductor substrate having recessed features; the method comprising:

a) providing the substrate with a barrier layer in a recessed feature deposited thereon to the seed layer deposition chamber;

b) applying a DC power to a metal target within the chamber and an applied RF bias to the substrate to simultaneously etch at least the sidewalls of the barrier layer oxide and implant metal atoms into the barrier layer;

c) applying a DC power to the metal target to deposit a metal seed layer that substantially coats the sidewalls of the features, wherein the implanted seeds are nucleation sites for the deposition of the metal seed layer.

16. The method of claim 15 wherein (b) further comprises sputtering excess barrier material from the tops of the features.

17. The method of claim 15 wherein the substrate undergoes a vacuum break between deposition of the barrier layer and deposition of the seed layer.

18. The method of claim 15 wherein the DC power applied in (b) is between about 0 and 5 W/cm2.

19. The method of claim 15 wherein the RF power applied in (b) is between about 0.1 and 5 W/cm2.

20. The method of claim 15 further comprising, prior to (a), depositing the barrier layer by a sputtering process.

21. The method of claim 20 wherein therein the substrate undergoes a vacuum break between deposition of the barrier layer and providing the substrate to the deposition chamber.

22. The method of claim 20 wherein therein the substrate does not undergo a vacuum break between deposition of the barrier layer and providing the substrate to the deposition chamber.

23. The method of claim 15 wherein the pressure during b) ranges from 1e−3 to 1e−2 Torr and the pressure during c) ranges from 5e−5 to 5e−3 Torr.

24. The method of claim 1 wherein the seed layer deposition chamber comprises a wafer support to support a wafer and a metal seed target located in proximity to the wafer support such that when sputtered from the target, metal seed material is deposited on a wafer supported by the wafer support.

Patent Citations (156)

Patent	Date	Inventor	Cited By
US4058430(A)	1977-11-01	Suntola et al.	Applicant
US4492620(A)	1985-01-01	Matsuo et al.	Applicant
US4588490(A)	1986-05-01	Cuomo et al.	Applicant
US4609903(A)	1986-09-01	Toyokura et al.	Applicant
US4622121(A)	1986-11-01	Wegmann et al.	Applicant
US4737384(A)	1988-04-01	Murthy et al.	Applicant
US4874493(A)	1989-10-01	Pan	Applicant
US4999096(A)	1991-03-01	Nihei et al.	Applicant
US5009963(A)	1991-04-01	Ohmi et al.	Applicant
US5084412(A)	1992-01-01	Nakasaki	Applicant
US5139825(A)	1992-08-01	Gordon et al.	Applicant
US5178739(A)	1993-01-01	Barnes et al.	Applicant
US5194398(A)	1993-03-01	Miyachi et al.	Applicant
US5221449(A)	1993-06-01	Colgan et al.	Applicant
US5281485(A)	1994-01-01	Colgan et al.	Applicant
US5298091(A)	1994-03-01	Edwards, III et al.	Applicant
US5378506(A)	1995-01-01	Imai et al.	Applicant
US5482611(A)	1996-01-01	Helmer et al.	Applicant
US5622608(A)	1997-04-01	Lanford et al.	Applicant
US5629221(A)	1997-05-01	Chao et al.	Applicant
US5654233(A)	1997-08-01	Yu	Applicant
US5656860(A)	1997-08-01	Lee	Applicant
US5766379(A)	1998-06-01	Lanford et al.	Applicant
US5789027(A)	1998-08-01	Watkins et al.	Applicant
US5801089(A)	1998-09-01	Kenney	Examiner
US5904565(A)	1999-05-01	Nguyen et al.	Applicant
US5969422(A)	1999-10-01	Ting et al.	Applicant
US5985762(A)	1999-11-01	Geffken et al.	Examiner
US6037257(A)	2000-03-01	Chiang et al.	Applicant
US6037258(A)	2000-03-01	Liu et al.	Examiner
US6046108(A)	2000-04-01	Liu et al.	Applicant
US6074544(A)	2000-06-01	Reid et al.	Applicant
US6077780(A)	2000-06-01	Dubin	Applicant
US6080285(A)	2000-06-01	Liu et al.	Applicant
US6093966(A)	2000-07-01	Venkatraman et al.	Applicant
US6099702(A)	2000-08-01	Reid et al.	Applicant
US6100200(A)	2000-08-01	Van Buskirk et al.	Applicant
US6110346(A)	2000-08-01	Reid et al.	Applicant
US6114238(A)	2000-09-01	Liao	Applicant
US6120641(A)	2000-09-01	Stevens et al.	Applicant
US6124203(A)	2000-09-01	Joo et al.	Applicant
US6126798(A)	2000-10-01	Reid et al.	Applicant
US6139712(A)	2000-10-01	Patton et al.	Applicant
US6147000(A)	2000-11-01	You et al.	Applicant
US6156167(A)	2000-12-01	Patton et al.	Applicant
US6159354(A)	2000-12-01	Contolini et al.	Applicant
US6159857(A)	2000-12-01	Liu et al.	Applicant
US6162344(A)	2000-12-01	Reid et al.	Applicant
US6179973(B1)	2001-01-01	Lai et al.	Applicant
US6179983(B1)	2001-01-01	Reid et al.	Applicant
US6193854(B1)	2001-02-01	Lai et al.	Applicant
US6200893(B1)	2001-03-01	Sneh	Applicant
US6203613(B1)	2001-03-01	Gates et al.	Applicant
US6217716(B1)	2001-04-01	Fai Lai	Applicant
US6221757(B1)	2001-04-01	Schmidbauer et al.	Applicant
US6228754(B1)	2001-05-01	Iacoponi et al.	Applicant
US6235163(B1)	2001-05-01	Angelo et al.	Applicant
US6249055(B1)	2001-06-01	Dubin	Applicant
US6251242(B1)	2001-06-01	Fu et al.	Applicant
US6271591(B1)	2001-08-01	Dubin et al.	Applicant
US6274008(B1)	2001-08-01	Gopalraja et al.	Applicant
US6277249(B1)	2001-08-01	Gopalraja et al.	Applicant
US6280597(B1)	2001-08-01	Kashiwada et al.	Applicant
US6287977(B1)	2001-09-01	Hashim et al.	Applicant
US6333547(B1)	2001-12-01	Tanaka et al.	Applicant
US6340435(B1)	2002-01-01	Bjorkman et al.	Examiner
US6342133(B2)	2002-01-01	D'Couto et al.	Applicant
US6342448(B1)	2002-01-01	Lin et al.	Applicant
US6350353(B2)	2002-02-01	Gopalraja et al.	Applicant
US6387805(B2)	2002-05-01	Ding et al.	Applicant
US6391785(B1)	2002-05-01	Satta et al.	Applicant
US6395642(B1)	2002-05-01	Liu et al.	Applicant
US6402907(B1)	2002-06-01	Rich	Applicant
US6417094(B1)	2002-07-01	Zhao et al.	Applicant
US6423200(B1)	2002-07-01	Hymes	Examiner
US6440854(B1)	2002-08-01	Rozbicki	Applicant
US6448176(B1)	2002-09-01	Grill et al.	Applicant
US6451177(B1)	2002-09-01	Gopalraja et al.	Examiner
US6492262(B2)	2002-12-01	Uzoh	Applicant
US6498091(B1)	2002-12-01	Chen et al.	Applicant
US6500762(B2)	2002-12-01	Hashim et al.	Applicant
US6509267(B1)	2003-01-01	Woo et al.	Examiner
US6518668(B2)	2003-02-01	Cohen	Examiner
US6538324(B1)	2003-03-01	Tagami et al.	Applicant
US6541374(B1)	2003-04-01	de Felipe et al.	Applicant
US6554914(B1)	2003-04-01	Rozbicki et al.	Applicant
US6559061(B2)	2003-05-01	Hashim et al.	Examiner
US6562715(B1)	2003-05-01	Chen et al.	Examiner
US6566246(B1)	2003-05-01	de Felipe et al.	Applicant
US6589887(B1)	2003-07-01	Dalton et al.	Applicant
US6605534(B1)	2003-08-01	Chung et al.	Applicant
US6607977(B1)	2003-08-01	Rozbicki et al.	Applicant
US6607982(B1)	2003-08-01	Powell et al.	Applicant
US6613199(B1)	2003-09-01	Tobin et al.	Applicant
US6642146(B1)	2003-11-01	Rozbicki et al.	Applicant
US6652718(B1)	2003-11-01	D'Couto et al.	Applicant
US6656841(B1)	2003-12-01	Kim	Applicant
US6660622(B2)	2003-12-01	Chen et al.	Examiner
US6673716(B1)	2004-01-01	D'Couto et al.	Applicant
US6706155(B2)	2004-03-01	Morimoto et al.	Applicant
US6709987(B2)	2004-03-01	Hashim et al.	Examiner
US6755945(B2)	2004-06-01	Yasar et al.	Applicant
US6758947(B2)	2004-07-01	Chiang et al.	Applicant
US6764940(B1)	2004-07-01	Rozbicki et al.	Examiner
US6784096(B2)	2004-08-01	Chen et al.	Examiner
US6790776(B2)	2004-09-01	Ding et al.	Examiner
US6841044(B1)	2005-01-01	Ruzic	Applicant
US6893541(B2)	2005-05-01	Chiang et al.	Applicant
US6905965(B2)	2005-06-01	Subrahmanyan et al.	Applicant
US6919275(B2)	2005-07-01	Chiang et al.	Applicant
US6943111(B2)	2005-09-01	Lin et al.	Applicant
US6949457(B1)	2005-09-01	Fiordalice et al.	Applicant
US6969448(B1)	2005-11-01	Lau	Applicant
US6992012(B2)	2006-01-01	Haskim et al.	Applicant
US7030031(B2)	2006-04-01	Wille et al.	Applicant
US7037830(B1)	2006-05-01	Rumer et al.	Applicant
US7048837(B2)	2006-05-01	Somekh et al.	Applicant
US7070687(B2)	2006-07-01	Chikarmane et al.	Examiner
US7074714(B2)	2006-07-01	Chiang et al.	Applicant
US7135402(B2)	2006-11-01	Lin et al.	Applicant
US7186648(B1)	2007-03-01	Rozbicki et al.	Applicant
US7253109(B2)	2007-08-01	Ding et al.	Applicant
US7294574(B2)	2007-11-01	Ding et al.	Applicant
US7365001(B2)	2008-04-01	Yang et al.	Applicant
US2002/0000382(A1)	2002-01-01	Morrissey et al.	Applicant
US2002/0041028(A1)	2002-04-01	Choi et al.	Applicant
US2002/0110999(A1)	2002-08-01	Lu et al.	Applicant
US2003/0034244(A1)	2003-02-01	Yasar et al.	Applicant
US2003/0116427(A1)	2003-06-01	Ding et al.	Applicant
US2003/0129828(A1)	2003-07-01	Cohen	Examiner
US2004/0007325(A1)	2004-01-01	Pan et al.	Examiner
US2004/0048461(A1)	2004-03-01	Chen et al.	Examiner
US2004/0171250(A1)	2004-09-01	Chiang et al.	Applicant
US2004/0188239(A1)	2004-09-01	Robison et al.	Applicant
US2004/0211661(A1)	2004-10-01	Zhang et al.	Applicant
US2005/0006222(A1)	2005-01-01	Ding et al.	Applicant
US2005/0020080(A1)	2005-01-01	Chiang et al.	Applicant
US2005/0032382(A1)	2005-02-01	Rossman	Applicant
US2005/0085068(A1)	2005-04-01	Chiang et al.	Applicant
US2005/0173239(A1)	2005-08-01	Somekh et al.	Applicant
US2005/0211545(A1)	2005-09-01	Cerio, Jr. et al.	Applicant
US2005/0252765(A1)	2005-11-01	Zhang et al.	Applicant
US2005/0255690(A1)	2005-11-01	Chen et al.	Applicant
US2005/0255691(A1)	2005-11-01	Ding et al.	Applicant
US2005/0266682(A1)	2005-12-01	Chen et al.	Applicant
US2005/0272254(A1)	2005-12-01	Ding et al.	Applicant
US2006/0014378(A1)	2006-01-01	Aggrawal et al.	Applicant
US2006/0024953(A1)	2006-02-01	Rao et al.	Applicant
US2006/0030151(A1)	2006-02-01	Ding et al.	Applicant
US2006/0057843(A1)	2006-03-01	Chen et al.	Applicant
US2006/0207873(A1)	2006-09-01	Fu	Applicant
US2007/0178682(A1)	2007-08-01	Chiang et al.	Applicant
US2008/0190760(A1)	2008-08-01	Tang et al.	Applicant
US2008/0310005(A1)	2008-12-01	Tonar et al.	Applicant
EP692551(A1)	1996-01-01		Applicant
JP11-186273	1999-09-01		Applicant

Non-Patent Literature (78)

Schumacher Products, TDEAT (Tetrakis-diethylamino Titanium), Electronic Grade, www.schumacher.com/tdeat.html, printed Jun. 5, 2001, 1 page.Applicant
Sun et al., Suppression of Cobalt Silicide Agglomeration Using Nitrogen (N2+) Implantation, IEEE Electron Device Letters, vol. 19, No. 5, May 1998, pp. 163-166.Applicant
Ashanti et al., “A New Hollow-Cathode Magnetron Source for 0.10.mu.m Copper Applications”, Journal of Vacuum Science and Technology, A 18(4) Jul./Aug. 2000 p. 1546.Applicant
Cohen et al., “Reactive Preclean Technology for Nonphysical Copper Oxide Reduction for Advanced CU Interconnect”, Jun. 16-18, 1998, VMIC Conference, pp. 91 and 93.Applicant
Jian Li and J. W. Mayer and E. G. Colgan, “Oxidation and Protection in Copper and Copper Alloy Thin Films”, J. Appl. Phys. 70 (5), Sep. 1, 1991, pp. 2820-2827.Applicant
Ding et al., “Observation of Reduced Oxidation Rates for Plasma-Assisted CVD Copper Films”, Mat. Res. Soc. Symp. Proc., vol. 309, 1993 pp. 445-460.Applicant
Klawuhn et al., “Ionized Physical-vapor deposition Using a Hollow-Cathode Magnetron Source for Advanced Metallization”, J. Vac, Sci, Technol. A18(4), Jul./Aug. 2000, pp. 1546-1549.Applicant
M. Zinke-Allmang, “Phase Separation on Solid Surfaces: Nucleation, Coarsening and Coalescence Kinetics”.Applicant
Peijun Ding, et al., “Copper Barrier, Seed Layer and Planarization Technologies,” VMIC Conference, Jun. 10-12, 1997, pp. 87-92.Applicant
Tarek Suwwan de Felipe, et al., “Electrical Stability and Microstructual Evolution in Thin Films of High Conductivity Copper Alloys,” IEEE, Jun. 1999, pp. 293-295.Applicant
Cho et al., “Factors Affecting Passivation and Resistivity of Cu(Mg) Alloy Film,” Materials Research Society Symposium Proc. vol. 564, 1999, pp. 353-358.Applicant
Murarka et al., “Copper Metallization for ULSI and Beyond,” Critical Reviews in Solid State and Materials Sciences, 1995, pp. 87-124.Applicant
Braeckelmann et al. “Integration and Reliability of Copper Magnesium Alloys for Multilevel Interconnects,” IEEE, Feb. 2000, pp. 236-238.Applicant
Arcot et al., “Intermetallic Formation in Copper/Magnesium Thin Films—kinetics, Nucleation and Growth, and Effect of Interfacial Oxygen,” J. Appl. Phys. 76(9), Nov. 1, 1994, pp. 5161-5170.Applicant
Ding et al., “Effects of the addition of small amounts of A1 to copper: Corrosion, resistivity, adhesion, morphology, and diffusion,” J. Appl. Phys. 75(7), Apr. 1994, pp. 3627-3631.Applicant
T. Suwwan de Felipe et al., “Bias-temperature stability of the Cu(Mg)/SiO.sub.2/p-Si metal-oxide-semiconductor capacitors,” J. Vac. Sci. Technol. B 15(6), Nov./Dec. 1997, pp. 1987-1986.Applicant
Chen et al. “Low Temperature Plasma-Assisted Chemical Vapor Deposition of Tantalum Nitride form Tantalum Pentabromide for Copper Metallization,” Jan./Feb. 1999, J. Vac. Sci. Technol., B 17(1), pp. 182-185.Applicant
Cheng et al., “Directional Deposition of Cu into Semiconductor Trench Structures Using Ionized Magnetron Sputtering,” Mar./Apr. 1995, J. Vac. Sci. Technol., B 13(2), pp. 203-208.Applicant
Cho et al., “Remote Plasma-Assisted Metal Organic Chemical Vapor Deposition of Tantalum Nitride Thin Films with Different Radicals,” Dec. 1998, Jpn. J. Appl. Phys., vol. 37.Applicant
Endle et al., “X-Ray Photoelectron Spectroscopy Study on TiN Films Produced with Tetrakis (dimethylamido)Titanium and Selected N-Containing Precusors on SiO.sub.2,” May/Jun. 1998, J. Vac. Sci. Technol., A 16(3), pp. 1262-1267.Applicant
Green et al., “Determination of Flux Ionization Fraction Using a Quartz Crystal Microbalance and a Gridded Energy Analyzer in an Ionized Magnetron Sputtering System,” Dec. 1997, Rev. Sci. Instrum., 68 (12), pp. 4555-4560.Applicant
Han et al., “Barrier Metal Properties of Amorphous Tantalum Nitride Thin Films Between Platnium and Silicon Deposited Using Remote Plasma Metal Organic Chemical Vapor Method,” May 1998, Jpn. J. Appl. Phys., vol. 37 (1998), Pt. 1, No. 5A, pp. 2646-2651.Applicant
Hayden et al., “Characterization of Magnetron-Sputtered Partially Ionized Aluminum Deposition,” Mar./Apr. 1998, J. Vac. Sci. Technol., A 16(2), pp. 624-627.Applicant
Hayden et al., “Helion Plasma Source for Ionized Physical Vapor Deposition,” 1999, Surface and Coatings Technology, 120-121 (1999), pp. 401-404.Applicant
Lee et al., “The Failure Mechanism of MOCVD TiN Diffusion Barrier at High Temperature,” 1996, Mat. Res. Soc. Symp. Proc., vol. 324, pp. 279-284.Applicant
Lucovsky et al., “Formation of Thin Fims by Remote Plasma Enhanced Chemical Vapor Deposition (Remote PECVD),” Feb. 1990, in Handbook of Plasma Processing Technology, eds. Rossnagel, Cuomo and Westwood, Noyes Publications, pp. 387-408.Applicant
Musher et al., Atmospheric Pressure Chemical Vapor Deposition of Titanium Nitride from Tetrakis (diethylamido) Titanium and Ammonia, Feb. 1996, J. Electochem. Soc., vol. 143, No. 2, pp. 736-744.Applicant
Peng et al., “Structural and Electrical Properties of Chemical Vapor Deposition Tungsten Overgrowth on Physical Vapor Deposited and Metalorganic Chemical Vapor Deposited TiNAdhesion Layers,” Jul./Aug. 1998, J. Vac. Sci. Technol., B 16(4), pp. 2013-2018.Applicant
Reif, Rafael, Plasma Enhanced Chemical Vapor Deposition of Thin Films for Microelectronics, Feb. 1990, in Handbook of Plasma Processing Technology, eds: Rossnagel, Cuomo and Westwood, Noyes Publications, pp. 260-284.Applicant
Truong, C.M.; Chen, P.J.; Corneille, J.S.; Oh, W.S. and Goodman, D.W., “Low-Pressure Deposition of TiN Thin Films from a Tetrakis (diethylamido) Titanium Precursor,” 1995, J. Phys. Chem., 1995, 99, pp. 8831-8842.Applicant
Tsai et al., “Comparison of the Diffusion Barrier Properties of Chemical-Vapor-Deposited TaN and Sputtered TaN Between Cu and Si,” May 1996, J. Appl. Phys., 79 (9), pp. 6932-6938.Applicant
Danek et al., “Barrier First Method for Single Damascene Trench Applications,” Novellus Systems, Inc., U.S. Appl. No. 11/714,465, filed Mar. 5, 2007.Applicant
U.S. Office Action mailed Jul. 31, 2002, from U.S. Appl. No. 09/862,539.Applicant
U.S. Office Action mailed Sep. 16, 2002, from U.S. Appl. No. 09/776,704.Applicant
U.S. Office Action mailed Apr. 22, 2002, from U.S. Appl. No. 09/776,704.Applicant
U.S. Final Office Action mailed Apr. 3, 2003, from U.S. Appl. No. 09/816,847.Applicant
U.S. Office Action mailed Oct. 4, 2002, from U.S. Appl. No. 09/816,847.Applicant
U.S. Office Action mailed Oct. 23, 2002, from U.S. Appl. No. 09/965,472.Applicant
U.S. Office Action mailed Oct. 3, 2003, from U.S. Appl. No. 10/412,562.Applicant
U.S. Final Office Action mailed Mar. 23, 2006, from U.S. Appl. No. 10/804,353.Applicant
U.S. Office Action mailed Oct. 3, 2006, from U.S. Appl. No. 10/804,353.Applicant
U.S. Office Action mailed Aug. 28, 2002, from U.S. Appl. No. 09/975,612.Applicant
U.S. Office Action mailed Jun. 15, 2004, from U.S. Appl. No. 10/289,237.Applicant
U.S. Office Action mailed Dec. 19, 2002, from U.S. Appl. No. 10/121,949.Applicant
Klawuhn et al., “Apparatus and Methods for Deposition and/or Etch Selectivity,” Novellus Systems, Inc., U.S. Appl. No. 11/558,693, filed Nov. 10, 2006.Applicant
Dulkin et al., “Method and Apparatus for Controlling Sputtered Flux in PVD Sources,” Novellus Systems, Inc., U.S. Appl. No. 11/564,222, filed Nov. 28, 2006.Applicant
Kailasam et al., “Resputtering Process for Eliminating Dielectric Damage,” Novellus Systems, Inc., U.S. Appl. No. 11/588,586, filed Oct. 26, 2006.Applicant
Lu et al., “An Integrated Plasma Equipment-feature Scale Model for Ionized Metal Physical Vapor Deposition”, Jun. 2000, University of Illinois (16 pages).Applicant
Font et al., “Scaling of Hollow Cathode Magnetrons for Metal Deposition”, Oct. 1999, University of Illinois (20 pages).Applicant
Rozbicki, R., “Methods and Apparatus for Resputtering Process that Improves Barrier Coverage,” Novellus Systems, Inc., U.S. Appl. No. 11/830,777, filed Jul. 30, 2007.Applicant
Rozbicki et al., “Multistep Method of Depositing Metal Seed Layers,” Novellus Systems, Inc., U.S. Appl. No. 11/701,984, filed Feb. 1, 2007.Applicant
Pradhan et al., “Atomic Layer Profiling of Diffusion Barrier and Metal See Layers,” Novellus Systems, Inc., U.S. Appl. No. 11/807,179, filed May 24, 2007.Applicant
Juliano, D., “Selective Resputtering of Metal Seed Layers,” Novellus Systems, Inc., U.S. Appl. No. 11/903,487, filed Sep. 21, 2007.Applicant
Vijayendran et al., “Gas Treatment Method and Apparatus to Improve Copper Gap Fill,” U.S. Appl. No. 11/131,599, filed May 18, 2005.Applicant
Vyvoda et al., “Role of sidewall scattering in featuring profile evolution during CI2 and HBr plasma etching of silicon,” J.Vac. Sci. Technol. B 18(2), Mar./Apr. 2000, pp. 820-833.Applicant
Hoekstra et al., “Microtenching resulting from specular reflection during chlorine etching of silicon,” J.Vac. Sci. Technol. B 16(4), Jul./Aug. 1998, pp. 2102-2104.Applicant
Lane et al., “Feature evolution during plasma etching. II. Polycrystalline silicone etching,” J.Vac. Sci. Technol. A 18(1), Jan./Feb. 2000, pp. 188-196.Applicant
Rozbicki R., “A Method of Enhancing Selectivity of Resputtering Process,” Novellus Systems, Inc., U.S. Appl. No. 11/977,355, filed Oct. 23, 2007.Applicant
Pradhan et al., “Method and Apparatus for Increasing Local Plasma Density in Magnetically Confined Plasma,” Novellus Systems, Inc., U.S. Appl. No. 11/807,182, filed May 24, 2007.Applicant
Kinder et al., “The Use of a Ultra-High Magnetic Fields in Resputter and Plasma Etching,” Novellus Systems, Inc., U.S. Appl. No. 11/807,183, filed May 24, 2007.Applicant
Dulkin et al., “Methods and Apparatus for Engineering and Interface Between A Diffusion Barrier Layer and A Seed Layer,” Novellus Systems, Inc., U.S. Appl. No. 11/807,178, filed May 24, 2007.Applicant
U.S. Office Action mailed Dec. 12, 2008, from U.S. Appl. No. 11/714,465.Applicant
Notice of Allowance and Fee Due mailed Nov. 24, 2008, from U.S. Appl. No. 11/558,693.Applicant
Allowed Claims from U.S. Appl. No. 11/558,693.Applicant
U.S. Office Action mailed Nov. 14, 2008, from U.S. Appl. No. 11/701,984.Applicant
Notice of Allowance and Fee Due mailed Apr. 13, 2004, from U.S. Appl. No. 10/412,562.Applicant
Allowed Claims from U.S. Appl. No. 10/412,562.Applicant
Notice of Allowance and Fee Due mailed Oct. 3, 2006, from U.S. Appl. No. 10/804,353.Applicant
Allowed Claims from U.S. Appl. No. 10/804,353.Applicant
Wu et al., “Methods and Apparatus for Depositing Titanium Based Diffusion Barrier Films,” Novellus Systems, Inc., U.S. Appl. No. 12/154,984, filed May 28, 2008.Applicant
U.S. Office Action mailed on Mar. 6, 2009 for U.S. Appl. No. 11/903,487.Applicant
U.S. Office Action mailed on Feb. 23, 2009 for U.S. Appl. No. 11/701,984.Applicant
U.S. Office Action mailed on Mar. 24, 2009 for U.S. Appl. No. 11/473,618.Applicant
U.S. Office Action mailed on May 5, 2009 for U.S. Appl. No. 11/588,586.Applicant
Notice of Allowance and Fee Due mailed Jun. 17, 2009 for U.S. Appl. No. 11/888,323.Applicant
U.S. Final Office Action mailed Jun. 17, 2009 for U.S. Appl. No. 11/701,984.Applicant
Wu et al., “Deposition of Doped Copper Seed Layers Having Improved Reliability,” Novellus Systems, Inc., U.S. Appl. No. 12/122,118, filed May 16, 2008.Applicant
U.S. Office Action mailed May 2, 2008, from U.S. Appl. No. 11/558,693.Applicant