Apparatus and method for hysteretic boost DC-DC converter

[0001] The invention is related to power converters, and in particular but not exclusively, to a circuit and method for a boost hysteretic DC-DC converter.

[0002] Three basic switching power supply topologies commonly used are buck converter, boost converter, and buck-boost converter. Of these, the simplest and most common is the buck converter. Various methods have been used to control buck converters in order to maintain an accurate and stable output voltage. Three of the most common methods to control buck converters are hysteretic control, pulse width modulation (PWM), and constant on-time (COT).

[0003] For buck converters, single-phase voltage-mode hysteretic control, also called “bang-bang” control or ripple regulator control, typically maintains an output voltage within a hysteresis band centered about an internal reference voltage. If the output voltage reaches or exceeds the reference voltage plus one-half of the hysteresis band, the controller turns OFF the high-side switch, typically a Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), and turns ON the low-side switch, to block energy from being transferred from an input to an output. This latter condition is a power stage OFF-state, and causes the output voltage to decrease.

[0004] When the output voltage is at or below the level of the reference minus one-half of the hysteresis band, the power stage goes into ON-stage, and the controller turns ON the high-side switch, and turns OFF the low-side switch to allow energy transfer from the input to the output, which causes the output voltage to increase. This hysteretic method of control keeps the output voltage within the hysteresis band around the reference voltage.

[0005] The two most common control methods for switching boost converters are: 1) fixed-frequency voltage-mode or current-mode; and 2) gated-oscillator. Hysteretic control for boost converters has typically not been possible.

[0011] Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

[0012] Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based, in part, on”, “based, at least in part, on”, or “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (FET) or a bipolar junction transistor (BJT) may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa.

[0013] Briefly stated, the invention is related to a boost hysteretic DC-DC converter. The converter includes a power switch, a hysteretic comparator, an inductor, an output capacitor, and a resistive device. The resistive device is coupled to the bottom of the output capacitor, so that the output voltage is equal to the sum of the capacitor voltage and the voltage across the resistive device. The resistance of the resistance device is sufficiently large that the output voltage ripple is in phase with the inductor current.

[0014] FIG. 1 shows a block diagram of an embodiment of boost hysteretic converter 100 and load 140. Boost DC-DC converter 100 includes resistive device 130, power switch 120, inductor L1, diode D1, capacitor C_O, and hysteretic comparator 110.

[0015] Hysteretic comparator 110 has a first input that is coupled to output node N1, a second input that is coupled to node N2, and an output that is coupled to node N3. Power switch 120 is coupled between switch node N6 and another node N4, and has a control input that is coupled to node N3. Resistive device 130 is coupled between node N4 and node N5.

[0016] Further, hysteretic comparator 110, resistive device 130, and power switch 120 together operate as boost converter circuitry that is arranged to operate in conjunction with external components output capacitor C_O and inductor L1 to convert input voltage Vin at node N7 to output voltage V_O at node N1 (the phrase “boost converter circuitry”, as used herein refers to a portion of the boost converter, specifically, a portion of the boost converter that excludes certain external components, such as the inductor, the output capacitor, and the load that the boost converter circuitry is designed to operate in conjunction with). Resistive device 130 has a resistance R_s that is sufficiently large that an output voltage ripple of output voltage V_O at the output node N1 is out of phase with an output capacitor voltage ripple of voltage v_C, where v_C is the voltage across output capacitor C_O.

[0017] Additionally, power switch 120, when turned on by switch control signal SCTL, transfers energy from input voltage Vin to inductor L1. When power switch 120 turns off, this energy is transferred to output capacitor C_O through diode D1.

[0018] In one embodiment, hysteretic comparator 120 is arranged to provide switch control signal SCTL based on a comparison of output voltage V_O at node N1 with reference voltage V_ref at node N2. In one embodiment, when the output voltage is at or below the level of the reference minus a hysteresis value (e.g. one-half of the hysteresis band in one embodiment), signal SCTL is asserted, which turns off power switch 120 to allow energy transfer from the input to the output, which causes output voltage V_O to increase. In one embodiment, this hysteretic method of control keeps output voltage V_O within the hysteresis band around reference voltage V_ref. Load 140 is driven by output voltage V_O.

[0019] In one embodiment, hysteretic comparator 110, resistive device 130, and power switch 120 are on-chip, and the other circuit elements illustrated in FIG. 1 are off-chip. In other embodiments, power switch 120 and/or resistive device 130 may be off-chip. In some embodiments, some of the other components may be on-chip. In some embodiments, diode D1 may be replaced with a synchronous switch, which may be off-chip or on-chip in various embodiments. Also, although not shown in FIG. 1, boost hysteretic converter 100 may have more features than shown, which may be on-chip, such as current limiting, de-glitching, and/or the like. For example, in one embodiment, a de-glitcher (not shown) is coupled between the output of the hysteretic comparator at node N3 and the control input of power switch 120. Further, boost hysteretic converter 100 may also include still other circuitry not shown, such as a reference voltage circuit that provides voltage V_ref; the voltage reference circuit may be on-chip or off-chip. Some embodiments include a voltage divider that provides a feedback voltage from the output voltage, and provides the feedback voltage to the hysteretic comparator rather than providing the output voltage directly, so that the output voltage is coupled to the first input of the hysteretic comparator via the voltage divider, rather than being connected directly. These variations and others are within the scope and spirit of the invention.

[0020] FIG. 2 illustrates a block diagram of an embodiment of boost hysteretic converter 200, which may be employed as an embodiment of boost hysteretic converter 100 of FIG. 1. Power switch 220 includes power transistor Q1. Resistive device 230 may include resistor R_s. The load (e.g. load 140 of FIG. 1) is represented by resistor R_O.

[0021] In a conventional hysteretic converter, the voltage across the output capacitor is the output voltage. However, in boost hysteretic converter 200, the output voltage V_O is given by v_C+v_S, where v_C is the voltage across output capacitor C_O, and v_S is the voltage across resistor R_s. The ripple of capacitor voltage v_C is out of phase with inductor current i_L. That is, the ripple of capacitor voltage v_C decreases when inductor current i_L increases, and the ripple of capacitor voltage v_C increases when inductor current i_L decreases. However, resistor R_s is sufficiently large that the ripple of output voltage V_O is in phase with inductor current i_L. That is, the ripple of output voltage V_O rises when inductor current i_L rises, and the ripple of output voltage V_O falls when inductor current i_L falls.

[0022] When signal SCTL is asserted, power switch Q1 turns on and the inductor current i_L flows through R_s. At the same time, the capacitor current i_C also flows through R_s. The total current flowing through R_s during ON time is
i_s=i_L+i_C  (1)

[0023] And i_C during ON time is
i_C=−I_o  (2)

[0024] Substituting (2) into (1) to obtain i_s, the current flowing through the sense resistor R_s during ON time:
i_s=i_L−I_o  (3)

[0025] Next, when signal SCTL is de-asserted, Q1 turns off, and substantially no current flows through transistor Q1. At this time, only the capacitor current i_C flows through the R_s. Accordingly, the current flowing through the sense resistor R_s during OFF time is
i_s=i_C  (4)

[0026] And i_C during OFF time is
i_C=i_L−I_o  (5)

[0027] Substituting (5) into (4) to obtain i_S, the current flowing through R_s during OFF time:
i_s=i_L−I_o  (6)

[0028] Accordingly, i_s=i_L−I_o regardless of whether switch Q1 is on or off, so that the current flowing through sense resistor R_s is always equal to the inductor current i_L minus the output current I_o. The output voltage, V_O, is the sum of two voltages: the output capacitor voltage and the voltage across the sense resistor, or v_C and v_S respectively. The ripple voltage across the capacitor is out of phase with the inductor current ripple i_L, but the ripple voltage across the sense resistor R_s is in phase with the inductor current because v_s=i_s·R_s. To ensure the total ripple voltage is in phase with the inductor current, a minimum resistor value R_s is employed. Accordingly, the voltage ripple of the output capacitor is:

[0029] $\begin{array}{cc}\frac{I_O}{C}·\mathrm{DF}·\Delta T=\frac{V_O}{R_O·C}·\mathrm{DF}·\Delta T,& \left(7\right)\end{array}$

[0030] where I_o is the output current, V_O is the output voltage, R_o is the equivalent output load resistance, C is the capacitance of output capacitor C_O, DF is the duty factor, and where ΔT is the period of switching frequency. To ensure the total ripple voltage is in phase with the inductor current, this ripple voltage must be no greater than that of the sense resistor, which is:

[0031] $\begin{array}{cc}\mathrm{Rs}·\frac{\mathrm{VIN}}{L}·\mathrm{DF}·\Delta T.& \left(8\right)\end{array}$

[0032] where L is the inductance of inductor L1. Applying the aforementioned inequality,

[0033] $\begin{array}{cc}C>\frac{V_o}{V_{\mathrm{in}}}·\frac{1}{R_o}·\frac{L}{R_s}& \left(9\right)\end{array}$

[0034] Expressed in terms of R_s,

[0035] $\begin{array}{cc}{R}_s>\frac{V_o}{V_{\mathrm{in}}}·\frac{C}{R_o}·L& \left(10\right)\end{array}$

[0036] When this inequality is obeyed, the overall output voltage ripple is in phase with the inductor current ripple. By doing so, power switch Q1 in a boost converter can be controlled by a simple hysteretic comparator like that of a buck hysteretic converter. The output voltage and its ripple can be sensed and controlled by a fixed reference voltage and the hysteresis of the comparator.

[0037] Although resistor R_s is shown as a resistor in FIG. 2, virtually any resistive device may be used for resistive R_s, such as a transistor biased as a resistive device, a printed circuit board trace, or the like, as long as R_s is sufficiently large that inequality (10) above is met.

[0038] The circuit of FIG. 2 provides a boost hysteretic converter that is relatively simply, stable, easy to integrate, and easy to use. In low power and portable applications (such as cells phones, Personal Desktop Assistants (PDAs), and digital cameras), an integrated boost DC-DC converter offers advantages in terms of cost, size, and design complexity. For example, a boost DC-DC converter may be needed to convert a single-cell or dual-cell battery voltage into a 3.3V or 5V voltage in such applications. Gated-oscillator boost converters typically have very high output ripple voltage, poor transient performance, and restricted range of operating points. PWM-control boost converters have better performance than gated-oscillator boost converters, but the dependence of frequency compensation on external components limits the applications of integrated PWM-Control boost converters to only very narrow cases. Frequency compensation adds cost while limiting the range of off-chip components such as the inductor and output capacitor, and does not allow users to optimize the performance because the frequency compensation is fixed inside the chip, which limits the inductor and output capacitor selection. When left off-chip, the frequency compensation components often take up more printed circuit board area than the boost converter chip itself, and tends to be difficult to design. In contrast, the circuit of FIG. 2 allows an integrated boost DC-DC converter that does not need frequency compensation and that can keep the converter stable over wide L-C component values.

[0039] FIGS. 3A-3F show timing diagrams of waveforms of embodiments of signals i_L, v_C, i_L*R_s, V_O, SCTL, and SW, respectively, for an embodiment of the circuit 200 of FIG. 2.

[0040] FIG. 4 illustrates a block diagram of an embodiment of boost hysteric converter 400, which may be employed as an embodiment of circuit of FIG. 2. In circuit 400, diode D1 is replaced with synchronous switch transistor Q2, which is controlled based, at least in part, on signal SCTL.

[0041] The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.