US 7,606,263 B1Grant

Packet parser

Issue Date:2009-10-20

•33 Claims

•27 Drawing Sheets

Abstract

A packet parser is described that parses a packet by identifying the locations of respective packet layers. A staged approach to parsing the packet is employed whereby a first stage tests the packet data units within a first window for the presence of a first packet layer, and a second stage, at least partly in parallel with the first stage, tests the packet data units within a second overlapping window for the presence of a second packet layer. In response to an embedded packet comprising a first packet forming the payload portion of a second packet, the parser produces a data structure comprising first data that identifies the location of the first packet, second data that identifies the location of the second packet, third data that identifies one or more layers of the first packet, and fourth data that identifies one or more layers of the second packet.

Metadata

Assignee

Extreme Networks, Inc.

Inventor

David K. Parker

Application Information

Application Number:US 10/835,272

Filing Date:2004-04-28

Priority Date:2004-03-30

Art Unit:2614

Classifications

IPC:

H04J3/24

Patent Drawings (27 sheets)

Description

[0001] This application claims the benefit of U.S. Provisional Application Ser. No. 60/558,039, filed Mar. 30, 2004, which is hereby fully incorporated herein by reference as though set forth in full.

FIELD OF THE INVENTION

[0002] This invention relates to the field of packet processing, and more specifically, to the parsing of packets into their constituent layers.

RELATED ART

[0003] Current packet parsers are under increasing pressure to handle higher and higher data throughputs of, e.g., 10 GB/s or more, and more complex and diverse data packet formats, e.g., embedded packet formats. However, these parsers are subject to various bottlenecks and constraints that limit the data throughput that is achievable and the packet formats that can be handled. Hence, there is a need for a packet parser that overcomes the problems of the prior art.

SUMMARY OF THE INVENTION

[0004] A first aspect of the invention comprises a method of parsing a packet. The packet has a plurality of packet data units and a plurality of packet layers, each having locations within the packet. In this method, one or more of the packet data units within a first window are tested for the presence of a first packet layer. If the first packet layer is detected within the first window, the location of the first layer within the packet is identified.

[0005] One or more of the packet data units within a second window are also tested for the presence of a second packet layer. This testing occurs at least partly in parallel with the testing for the presence of the first packet layer. This second window at least partially overlaps the first window. If the second packet layer is detected within the second window, the location of the second layer within the packet is identified.

[0006] A second aspect of the invention comprises a data structure representing an embedded packet. This embedded packet comprises a first packet forming the payload portion of a second packet. These first and second packets have locations within the embedded packet. Moreover, each of the first and second packets has one or more packet layers, each having a location within the respective packet. The data structure is stored on a processor readable medium. This data structure has first data identifying the location of the first packet within the embedded packet, and second data identifying the location of the second packet within the embedded packet. It also has third data identifying the location of one or more layers within the first packet, and fourth data identifying the location of one or more layers within the second packet.

[0007] Related systems, methods, features and advantages of the invention or combinations of the foregoing will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, advantages and combinations be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.

[0009] FIG. 1 is a block diagram of an embodiment of a packet processing system that comprises a receive-side packet classification system and a transmit-side packet modification system.

[0010] FIG. 2 illustrates an example of the format of a packet header as produced by an embodiment of a packet classification system in a packet processing system.

[0011] FIG. 3 is a block diagram of an embodiment of a receive-side packet classification system.

[0012] FIGS. 4A-4B are a block diagram of an embodiment of a transmit-side packet modification system.

[0013] FIG. 5 is a block diagram of an embodiment of a cascade of multiple packet processing systems.

[0014] FIG. 6 is a flowchart of an embodiment of method of processing a packet which comprises multiple parsing steps.

[0015] FIG. 7 is a flowchart of an embodiment of a method of performing egress mirroring of a packet.

[0016] FIG. 8 is a flowchart of an embodiment of a method of performing egress marking of a packet.

[0017] FIG. 9 is a flowchart of an embodiment of a method of resolving a plurality of quality of service (QoS) indicators for a packet utilizing a configurable priority resolution scheme.

[0018] FIG. 10 is a flowchart of an embodiment of a method of classifying a packet in which sliced packet data is provided to a packet classification engine over a wide data path.

[0019] FIG. 11 is a flowchart of an embodiment of a method of modifying a packet in which sliced packet data is provided to a packet modification engine over a wide data path.

[0020] FIG. 12 is a flowchart of an embodiment of a method of controlling packet classification processing of a packet through first and second stacks.

[0021] FIG. 13 is a flowchart of an embodiment of a method of maintaining packet statistics which involves allocating a packet size determiner to a packet from a pool of packet size determiners.

[0022] FIG. 14 is a flowchart of an embodiment of a method of classifying a packet which involves buffering the packet in a buffer upon or after ingress thereof, and associating packet classification data with the packet as retrieved directly from the buffer to form a classified packet on an egress data path.

[0023] FIG. 15 is a flowchart of an embodiment of a method of modifying a packet which involves buffering the packet in a buffer upon or after ingress thereof, and assembling a packet on an egress data path from one or more modified portions of the packet, and one or more unmodified portions as retrieved directly from the buffer.

[0024] FIG. 16 is a flowchart of an embodiment of a method of performing classification processing of a packet in a cascaded combination of multiple, replicated packet classification systems.

[0025] FIG. 17 is a flowchart of an embodiment of a method of preventing re-ordering of packets in a packet processing system.

[0026] FIG. 18 is an embodiment of a method of parsing a packet, in which first and second testing steps occur at least partly in parallel, and utilize respectively utilize first and second windows that overlap at least in part.

[0027] FIG. 19 illustrates an example of the packet data units (PDUs) forming a packet, and the windows utilized in the various testing steps occurring during the parsing of the packet.

[0028] FIG. 20 is a block diagram of a system for parsing a packet, comprising a buffer for buffering the PDUs of the packet, and first and second stages for testing the packet for the presence of packet layers.

[0029] FIG. 21 is a block diagram illustrating the stages in one implementation of the system of FIG. 20.

[0030] FIG. 22 illustrates one implementation of the process of detecting tunneling conditions.

[0031] FIG. 23 illustrates an overview of the process of parsing a packet in a paged mode of operation.

[0032] FIG. 24 illustrates the context pointers produced in one embodiment of a parsing method or system according to the invention.

[0033] FIG. 25 illustrates a detailed example of the data structure produced for a page in one embodiment of a parsing method or system according to the invention.

[0034] FIG. 26 illustrates the differing usage of the data structure of FIG. 25 by the three instantiations of the parser illustrated in FIG. 1.

RELATED APPLICATIONS

[0035] The following applications are commonly owned by the assignee hereof, and are each incorporated by reference herein as though set forth in full:

[0036]


	Extreme
	Dkt.
Howrey Dkt. No.	No.	Title	Filing date

02453.0025.NPUS00	P111	PACKET	Mar. 30,
		PROCESSING	2004
		SYSTEM
		ARCHITECTURE
		AND METHOD
02453.0025.NPUS01	P153	PACKET	Mar. 30,
		PROCESSING	2004
		SYSTEM
		ARCHITECTURE
		AND METHOD
02453.0026.NPUS00	P122	PACKET DATA	Mar. 30,
		MODIFICATION	2004
		PROCESSOR
02453.0027.NPUS00	P124	SYSTEM AND	Mar. 30,
		METHOD FOR	2004
		PACKET
		PROCESSOR
		STATUS
		MONITORING
02453.0028.NPUS00	P126	METHOD AND	Mar. 30,
		SYSTEM FOR	2004
		INCREMENTALLY
		UPDATING A
		CHECKSUM IN A
		NETWORK DATA
		PACKET
02453.0029.NPUS00	P127	SYSTEM AND	Mar. 30,
		METHOD FOR	2004
		EGRESS PACKET
		MARKING
02453.0030.NPUS00	P128	SYSTEM AND	Mar. 30,
		METHOD FOR	2004
		ASSEMBLING A
		DATA PACKET
02453.0032.NPUS00	P125	PACKET DATA	Mar. 30,
		MODIFICATION	2004
		PROCESSOR
		COMMAND
		INSTRUCTION SET
02453.0033.NPUS00	P123	DATA	Mar. 30,
		STRUCTURES	2004
		FOR SUPPORTING
		PACKET DATA
		MODIFICATION
		OPERATIONS
02453.0035.NPUS00	P144	SYSTEM FOR	Concurrently
		DERIVING PACKET	herewith
		QUALITY OF
		SERVICE
		INDICATOR
02453.0037.NPUS00	P146	PIPELINE	Concurrently
		PACKET	herewith
		PROCESSOR
02453.0038.NPUS00	P147	SYSTEM FOR	Concurrently
		DERIVING HASH	herewith
		VALUES FOR
		PACKETS IN A
		PACKET
		PROCESSING
		SYSTEM
02453.0039.NPUS00	P148	SYSTEMS FOR	Concurrently
		SUPPORTING	herewith
		PACKET
		PROCESSING
		OPERATIONS
02453.0040.NPUS00	P149	SYSTEM FOR	Concurrently
		ACCESSING	herewith
		CONTENT-
		ADDRESSABLE
		MEMORY IN A
		PACKET
		PROCESSOR
02453.0041.NPUS00	P150	SYSTEM FOR	Concurrently
		STATISTICS	herewith
		GATHERING AND
		SAMPLING IN A
		PACKET
		PROCESSING
		SYSTEM
02453.0042.NPUS00	P151	EXCEPTION	Concurrently
		HANDLING SYSTEM	herewith
		FOR PACKET
		PROCESSOR

DETAILED DESCRIPTION

[0037] As utilized herein, terms such as “about” and “substantially” and “near” are intended to allow some leeway in mathematical exactness to account for tolerances that are acceptable in the trade. Accordingly, any deviations upward or downward from the value modified by the terms “about” or “substantially” or “near” in the range of 1% to 20% or less should be considered to be explicitly within the scope of the stated value.

[0038] As used herein, the terms “software” or “instructions” or commands” include source code, assembly language code, binary code, firmware, macro-instructions, micro-instructions, or the like, or any combination of two or more of the foregoing.

[0039] The term “memory” refers to any processor-readable physical or logical medium, including but not limited to RAM, ROM, EPROM, PROM, EEPROM, disk, floppy disk, hard disk, CD-ROM, DVD, queue, FIFO or the like, or any combination of two or more of the foregoing, on which may be stored one or more instructions or commands executable by a processor, data, or packets in whole or in part.

[0040] The terms “processor” or “CPU” or “engine” refer to any device capable of executing one or more commands or instructions and includes, without limitation, a general- or special-purpose microprocessor, finite state machine, controller, computer, digital signal processor (DSP), or the like.

[0041] The term “logic” refers to implementations in hardware, software, or combinations of hardware and software.

[0042] The term “stack” may be implemented through a first-in-first-out memory such as a FIFO.

[0043] The term “packet” means (1) a group of binary digits including data and control elements which is switched and transmitted as a composite whole, wherein the data and control elements and possibly error control information are arranged in a specified format; (2) a block of information that is transmitted within a single transfer operation; (3) a collection of symbols that contains addressing information and possibly error detection or correction information; (4) a sequence of characters with a specific order and format, such as destination followed by a payload; (5) a grouping of data of some finite size that is transmitted as a unit; (6) a frame; (7) the logical organization of control and data fields defined for any of the layers or sub-layers of an applicable reference model, including the OSI or TCP/IP reference models, e.g., MAC sub-layer; or (8) a unit of transmission for any of the layers or sub-layers of an applicable reference model, including the OSI or TCP/IP reference models.

[0044] The term “layer two of the OSI reference model” includes the MAC sub-layer.

[0045] The term “port” or “channel” refers to any point of ingress or egress to or from a switch or other entity, including any port channel or sub-channel, or any channel or sub-channel of a bus coupled to the port.

[0046] The term “packet processing state data” in relation to a packet refers to data representative of at least a portion of the packet, data representative of at least a portion of the state of processing of the packet, or both.

Example Environment

[0047] An example environment for the subject invention will now be described. Many others examples are possible, so nothing in this example should be taken as limiting.

[0048] FIG. 1 illustrates an embodiment 100 of a packet processing system comprising a packet classification system 102 and a packet modification system 104. The packet classification system 102 has an ingress portion 106 and an egress portion 108. Similarly, the packet modification system 104 has an ingress portion 110 and an egress portion 112. The ingress portion 106 of the packet classification system 102 is coupled, through interface 118, to one or more network-side devices 114, and the egress portion 108 of the packet classification system 102 is coupled, through interface 120, to one or more switch-side devices 116. The ingress portion 110 of the packet modification system 104 is coupled, through interface 122, to the one or more switch-side devices 116, and the egress portion 124 of the packet modification system 104 is coupled, through interface 112, to the one or more network-side devices 114.

[0049] The packet classification system 102 comprises an ingress portion 106, a first packet parser 126 for parsing a packet and providing first data representative thereof, and a packet classification engine 128 for classifying the packet responsive to the first data. The packet modification system 104 comprises a second packet parser 130 for parsing the classified packet (after a round trip through the one or more switch-side devices 116) or a packet derived there-from and providing second data representative thereof, a packet modification engine 132 for modifying some or all of the packet responsive to the second data, a third packet parser 134 for parsing the modified packet and providing third data representative thereof, and a packet post-processor 136 for post-processing the modified packet responsive to the third data.

[0050] In one embodiment, the packet undergoing processing by the system has a plurality of encapsulated layers, and each of the first, second and third parsers 126, 130, 134 is configured to parse the packet by providing context pointers pointing to the start of one or more of the encapsulated layers. In a second embodiment, the packet undergoing processing by the system comprises a first packet forming the payload portion of a second packet, each of the first and second packets having a plurality of encapsulated layers, and each of the first, second and third parsers 126, 130, 134 is configured to parse the packet by providing context pointers pointing to the start of one or more of the encapsulated layers of the first packet and one or more of the encapsulated layers of the second packet.

[0051] In one implementation, the packet post-processor 136 is configured to compute a checksum for a modified packet responsive to the third data provided by parser 134. In one embodiment, the packet post-processor 136 is configured to independently calculate a layer three (IP) and layer four (TCP/UDP) checksum.

[0052] In one embodiment, packet post-processor 136 comprises Egress Access Control List (ACL) logic 136a and Packet Marking logic 136b. The Egress ACL logic 136a is configured to arrive at an ACL decision with respect to a packet. In one implementation, four ACL decisions can be independently performed: 1) default ACL action; 2) CPU copy; 3) mirror copy; and 4) kill. The default ACL action may be set to kill or allow. The CPU copy action forwards a copy of the packet to a host 138 coupled to the system. The mirror copy action implements an egress mirroring function (to be discussed in more detail later), in which a copy of the packet is forwarded to mirror FIFO 140 and then on to the egress portion 108 of the packet classification system 102. The kill action either kills the packet or marks it for killing by a downstream Medium Access Control (MAC) processor.

[0053] The Packet Marking logic 136b is configured to implement a packet egress marking function in which certain packet marking control information for a packet generated by the packet classification system 102 is used to selectively modify one or more quality of service (QoS) fields in the packet.

[0054] In one embodiment, Content Addressable Memory (CAM) 142 is used by the packet classification system 102 to perform packet searches to arrive at a classification decision for a packet. In one implementation, the CAM searches are ternary in that all entries of the CAM have a data and mask field allowing don't care setting of any bit position in the data field. In another implementation, the CAM searches are binary, or combinations of binary and ternary.

[0055] The associated RAM (ARAM) 144 provides associated data for each entry in the CAM 142. The ARAM 144 is accessed using the match address returned by the CAM 142 as a result of a search operation. The ARAM 144 entry data is used to supply intermediate classification information for the packet that is used by the classification engine 128 in making a final classification decision for the packet.

[0056] The statistics RAM 146 is used to maintain various packet statistics, including, for each CAM entry, the cumulative number and size of packets which hit or matched that entry.

[0057] The modification RAM 148 provides data and control structures for packet modification operations performed by the modification engine 132.

[0058] In one implementation, the interfaces 150, 152, 154, and 156 with any of the RAMs or CAMs may be a QDR- or DDR-type interface as described in U.S. patent application Ser. No. 10/655,742, filed Sep. 4, 2003, which is hereby fully incorporated by reference herein as though set forth in full.

[0059] FIG. 2 illustrates the format of classification data 200 for a packet as produced by one embodiment of packet classification system 102. The classification data 200 in this embodiment has first and second portions, identified respectively with numerals 202 and 204. The first portion 202 is a 64 bit Address Filtering Header (AFH) which is pre-pended to the packet. The second portion 204 is a 20 bit grouping of flags which are encoded as control bits maintained by the system 100.

[0060] In one embodiment, the Port Tag Index (PTI) field is an identifier of the port or list of ports within interface 118 over which the packet will be sent by the packet modification engine. (The assumption in this embodiment is that the interface 118 is a multi-port interface).

[0061] The Egress Quality of Service (EQOS) field may be used to perform an egress queue selection function in a device encountering the packet. In one embodiment, this field also encodes one of the following functions: nothing, preemptive kill, normal kill, thermonuclear kill, egress mirror copy, pre-emptive intercept to host, and normal intercept to host.

[0062] The Link Aggregation Index (LAI) field may be used to implement physical link selection, ingress alias, echo kill alias, or equal cost multi-path functions in a device encountering the packet.

[0063] The JUMBO flag, if asserted, directs a device encountering the packet to perform a JUMBO-allowed check. In one embodiment, the flag is used to implement the policy that the only valid JUMBO packets are IP packets. Therefore, if the packet is a non-IP JUMBO packet, the device either sends it to a host, fragments it, or kills it.

[0064] The DON'T FRAG flag, if asserted, directs a device encountering the packet not to fragment it in the course of implementing a JUMBO-allowed check.

[0065] The IF TYPE flag indicates whether the ingress interface over which the packet was received is an Ethernet or Packet Over Sonet (POS) interface.

[0066] The ROUTE flag, if asserted, indicates that the packet is being bridged not routed, and may be used by devices encountering the packet to implement an echo kill suppress function.

[0067] The RANDOM EARLY DROP (RED) flag may be used to implement a random early drop function in devices encountering the packet.

[0068] The CTL flag indicates the format of the AFH. FIG. 2 illustrates the format of the header for packets exiting the packet classification system 102 and destined for the one or more switch-side devices 116. Another format applies for packets exiting the one or more switch-side devices 116 and destined for the packet modification system 104. The CTL flag indicates which of these two formats is applicable.

[0069] The Transmit Modification Index (TXMI) field is used by the modification engine 132 to retrieve control and data structures from Modification RAM 148 for use in performing any necessary modifications to the packet.

[0070] The CPU Quality of Service (CQoS) field may be used to perform an ingress queue select function in a host coupled to the packet processing system.

[0071] In one embodiment, the CPU Copy flag, if asserted, directs one or more of the switch-side devices 116 to forward a copy of the packet to a host coupled to the packet processing system. In another embodiment, the CPU Copy flag, if asserted, directs a copy of a packet to be forwarded to the host through a host bus or another PBUS.

[0072] The Redirect flag, if asserted, directs one or more of the switch-side devices 116 to forward a copy of the packet to the host for redirect processing. In redirect processing, the host receives the packet copy and redirects it to the sender, with an indication that the sender should switch the packet, not route it.

[0073] The Statistical Sample (SSAMPLE) flag, if asserted, indicates to one or more of the switch-side devices 116 that the packet is a candidate for statistical sampling. If the packet is ultimately selected for statistical sampling, a copy of the packet is directed to the host, which performs a statistical analysis of the packet for the purpose of accurately characterizing the network traffic of which the packet is a part.

[0074] The LEARN flag, if asserted, directs one or more of the switch-side devices 116 to forward a copy of the packet to the host so the host can perform learn processing. In learn processing, the host analyzes the packet to “learn” the sender's MAC address for future packet switching of packets to that address.

[0075] The Egress Mirror (EMIRROR) flag, if asserted, implements egress mirroring by directing one or more of the switch-side devices 116 to send a copy of the packet to mirror FIFO 140. From mirror FIFO 140, the packet passes through the egress portion 108 of the packet classification system 102 en route to the one or more switch-side devices 116.

[0076] The Ingress Quality of Service (IQoS) field may be used to perform an ingress queue selection function in a device encountering the packet.

[0077] The Egress Mark Select (EMRK SEL) field selects one of several possible egress mark functions. The Egress Mask (EMRK MASK) field selects one of several possible egress masks. Together, the EMRK SEL and EMRK MASK fields forms an embodiment of packet egress marking control information which may be used by packet marking logic 136b to mark the packet, i.e., selectively modify one or more QoS fields within the packet.

[0078] The Ingress Mirror (IMIRROR) flag, if asserted, directs one or more of the switch-side devices 116 to forward a copy of the packet to the designated ingress mirror port on the switch.

[0079] The Parity Error Kill (PERR KILL) flag, if asserted, directs the interface 120 to kill the packet due to detection of an ARAM parity error.

[0080] In one embodiment, the EMIRROR bit is normally in an unasserted state. If the packet classification system 102, after analyzing the packet, determines that egress mirroring of the packet is appropriate, the packet classification system 102 changes the state of the EMIRROR bit to place it in the asserted state.

[0081] The packet, along with a pre-pended AFH containing the EMIRROR bit, is then forwarded to the one or more switch-side devices 116. After processing the packet, the one or more devices transmit the packet, with the EMIRROR bit preserved in a pre-pended packet header, back to the packet modification system 104 over interface 122. In response, the packet modification system 104 is configured to detect the state of the EMIRROR bit to determine if egress mirroring of the modified packet is activated, and if so, provide a copy of the modified packet to the egress portion 108 of the packet classification system 102 through the mirror FIFO 140.

[0082] In one embodiment, the EQoS, CQoS, IQoS, EMRK SEL and EMRK MASK fields define a multi-dimensional quality of service indicator for the packet. In this embodiment, the EMRK SEL and EMRK MASK fields form packet egress marking control information which is utilized by packet modification system 104 to selectively modify one or more quality of service fields within the packet, or a packet derived there-from.

[0083] The quality of service indicator for a packet may be derived from a plurality of candidate quality of service indicators derived from diverse sources. In one embodiment, a plurality of candidate quality of service indicators are derived for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the plurality of quality of service indicators for assigning to the packet. In one embodiment, one or more of the candidate quality of service indicators, and associated priorities, are derived by mapping one or more fields of the packet into one or more candidate quality of service indicators for the packet and associated priorities. In a second embodiment, one or more searches are conducted to obtain one or more candidate quality of service indicators for the packet and associated priorities. In a third embodiment, a combination of these two approaches is utilized.

[0084] In one example, candidate quality of service indicators, and associated priorities, are derived from three sources. The first is a VLAN mapping, scheme in which a VLAN from the packet is mapped into a candidate quality of service indicator and associated priority using a VLAN state table (VST). The VLAN from the packet may represent a subnet or traffic type, and the associated priority may vary based on the subnet or traffic type. The second is a CAM-based search that yields an associated ARAM entry which in turn yields a candidate quality of service indicator. A field of an entry in a Sequence Control Table (SCT) RAM, which provides the sequence of commands controlling the operation of one embodiment of the packet classification engine 102, provides the associated priority. The third is a QoS mapping scheme, which operates in one of three modes, as determined by a field in a SCT RAM entry.

[0085] In the first mode, the .1p mapping mode, the VST provides the four QSEGment bits. The QSEG and the .1p bits are mapped into a candidate quality of service indicator, and the VLAN itself is mapped into an associated priority using the VST. In the second mode, the MPLS mapping mode, the EXP/QOS fields from the packet are mapped into a candidate quality of service indicator, and a VLAN from the packet is mapped into the associated priority using the VST. In the third mode, the ToS mapping mode, the IPv4ToS, IPv6 Traffic Class, or Ipv6 Flow Label based QoS fields are mapped into a candidate quality of service indicator, and a VLAN from the packet is mapped into an associated priority using the VST.

[0086] In this example, the candidate quality of service indicator with the highest priority is assigned to the packet. Moreover, a candidate from one of the sources can be established as the default, which may be overridden by a candidate obtained from one of the other sources, at least a candidate that has a higher priority than the default selection. For example, the candidate quality of service indicator resulting from the .1p mapping mode can be established as the default selection, and this default overridden only by a candidate quality of service indicator resulting from an ARAM entry in turn resulting from a CAM-based search.

[0087] FIG. 3 illustrates an embodiment 300 of a packet classification system. In this embodiment, the packet classification system is coupled to one or more network-side devices through a multi-port packet bus (PBUS) 302, as described in U.S. patent application Ser. Nos. 10/405,960 and 10/405,961, filed Apr. 1, 2003, which are both hereby fully incorporated herein by reference. PBUS ingress logic 304 is configured to detect a start of packet (SOP) condition for packets arriving at the packet classification system over the PBUS.

[0088] Upon or after detection of the SOP condition, the packet, or a portion thereof, is stored in slicer 306. Slicer 306 is configured to slice some or all of a packet into portions and provide the portions in parallel over first data path 308 having a first width to classification engine 310. In one embodiment, the slicer 306 is a FIFO which stores the first 128 bytes of a packet (or the entirety of the packet if less than 128 bytes), and provides the 1024 bits thereof in parallel to the packet classification engine 310 over the first data path 308.

[0089] Upon or after detection of the SOP condition, parser 312 parses the packet in the manner described previously, and stores the resultant context pointers (and other flags resulting from the parsing process) in parser result RAM 314. Concurrently with this parsing process, the packet is stored in buffer 318, which in one embodiment, is a FIFO buffer.

[0090] The packet classification engine 310 is configured to classify the packet responsive to the packet portions received over the first data path 308 and the parser results as stored in the parser result RAM 314, and store data representative of the packet classification in classification RAM 316. In one embodiment, the classification data is the AF header illustrated in FIG. 2.

[0091] An associator 320 is configured to associate the data representative of the packet classification with some or all of the packet, and provide the associated packet over a second data path 322 having a second width less than the first width.

[0092] The packet classification system is coupled to one or more switch-side devices over a multi-port PBUS 326, and PBUS egress logic 324 is configured to transmit the associated packet over the PBUS 326.

[0093] In one embodiment, slicer 306 comprises a plurality of memories configured to store some or all of the packet, and provide the portions thereof in parallel over the first data path 308 to the classification engine 310. In one example, the slicer 306 is configured as eight (8) memories configured to provide the first 1024 bits of the bits of the packet (or less if the packet is less than 128 bytes) in parallel over the first data path 308 to classification engine 310.

[0094] In one embodiment, the associator 320 comprises a multiplexor configured to multiplex onto the second data path 322 the data representative of the packet classification as stored in classification RAM 316 and some or all of the packet as stored in buffer 318. In one implementation, the multiplexor multiplexes the first 8 byte portion 202 of the AF data illustrated in FIG. 2 (which may be referred to as the AF header) onto the second data path followed by the packet as stored in buffer 318, thereby effectively pre-pending the AF header to the packet. In this implementation, control logic 328 controls the operation of the multiplexor through one or more signals provided over control data path 334.

[0095] More specifically, the multiplexor in this implementation is configured to select one of three inputs and output the selected input to the second data path 322 under the control of the control logic 328. The first input is the classification data as stored in classification RAM 316. The second input is the packet as stored in buffer 318. The third input is the output of the mirror FIFO 140. This third input is selected when the egress mirroring function, discussed previously, is activated.

[0096] In one embodiment, the control logic 328 is also configured to maintain first and second FIFO buffers, identified respectively with numerals 330 and 332, the first FIFO buffer 330 for identifying those packets which are awaiting classification by the packet classification system, and the second FIFO buffer 332 for identifying those packets which are undergoing classification by the classification system.

[0097] In this embodiment, the control logic 328 is configured to place an identifier of a packet on the first FIFO buffer 330 upon or after receipt of the packet by the packet classification system, pop the identifier off the first FIFO buffer 330 and place it on the second FIFO buffer 332 upon or after initiation of classification processing of the packet by the packet classification system, and pop the identifier off the second FIFO buffer 332 upon or after completion of classification processing of the packet by the packet classification system.

[0098] The control logic 328 is configured to prevent the packet classification system from outputting a packet onto PBUS 326 while an identifier of the same is placed on either the first or second FIFO buffers 330, 332, and allows the packet classification system to output the packet onto PBUS 326 upon or after the identifier of the packet has been popped off the second FIFO buffer 332. In one implementation, the control logic 328 prevents the associator 320 from outputting data on the second data path 322 through one or more signals provided over control data path 334. In one implementation, the control logic 328 is a state machine.

[0099] In one embodiment, the control logic 328 forms the basis of a packet statistics maintaining system within the packet classification system. In this embodiment, the control logic 328 is configured to maintain a pool of packet size determiners, and allocate a packet size determiner to a packet from the pool upon or after receipt thereof by the packet classification system.

[0100] In one implementation, the control logic 328 allocates a packet size determiner to a packet upon or after the PBUS ingress logic 304 signals a SOP condition for the packet. The packet size determiner is configured to determine the size of the packet, and the control logic 328 is configured to return the packet size determiner to the pool upon or after the same has determined the size of the packet. In one implementation example, the packet size determiners are counters.

[0101] Statistics RAM 330 in this embodiment maintains packet statistics, and statistics update logic 336 is configured to update the packet statistics responsive to the determined size of the packet. In one implementation, the statistics update logic 336 includes a queue for queuing statistics update requests issued by the control logic 328.

[0102] In one configuration, the packet statistics maintaining system is configured to maintain packet statistics indicating the cumulative size of packets which have met specified processing conditions or hits, and the statistics update logic 336, upon or after a packet size determiner has determined the size of a packet, is configured to increment a cumulative size statistic for a particular processing condition or hit by the determined size of the packet if the packet satisfies that particular processing condition or hit. In one example, the system maintains statistics indicating the cumulative size and number of packets which have resulted in each of a plurality of ternary CAM 142 hits.

[0103] FIGS. 4A-4B illustrate an embodiment 400 of a packet modification system having PBUS ingress logic 404 which is coupled to one or more switch-side devices through PBUS 402. In this embodiment, the packets are received over the PBUS channels in bursts. The PBUS ingress logic 404 is configured to monitor the PBUS channels in a round robin fashion. When the PBUS ingress logic 404 detects a SOP condition on one of the channels, the Transmit Modification Index (TXMI) is extracted from the AF header of the packet, and it, along with the length of the initial packet burst, and an end of packet (EOP) marker if the packet length is less than or equal to the burst length, is placed on Transmit In Control FIFO 406. The packet or packet burst is stored in Transmit In Data FIFO 428, and a pointer to the start of the packet or packet burst (SOP pointer) is stored in Transmit Engine FIFO 408, along with an identifier of the PBUS channel over which the packet or packet burst was received. In one implementation, the packet bursts are 128 bytes in length.

[0104] Transmit In Data FIFO 428 stores the packet data such that portions of the packet can be passed in parallel over a first data path 402 having a first width to a modification engine 422. In one implementation, the Transmit In Data FIFO 428 comprises a plurality of FIFOs, with the outputs of the FIFOs coupled in parallel to the modification engine 422 and collectively forming the first data path 402. Incoming packet or packet bursts are copied into each of the plurality of FIFOs, thereby providing the modification engine with sliced portions of the packets or packet bursts in parallel.

[0105] The incoming packets or packet bursts are also input to the second packet parser 424, which parses the packets or packet bursts in the manner described previously. The context pointers and status bits resulting from the parsing process are stored in parser result RAM 426.

[0106] The Transmit Command Sequencer 410 is configured to read a SOP pointer and channel from the Transmit Engine FIFO 408, and utilize this information to locate the packet or packet bursts in the Transmit In Control FIFO 406. The Transmit Modification Index (TXMI) within the AF header of this packet or packet burst is then located and used to access a TXMI link in External Transmit SRAM 412, an SRAM located off-chip in relation to modification engine 422. The TXMI link may either be 1) an internal recipe link to a recipe of modification commands stored in Internal Recipe RAM 414, an on-chip RAM in relation to modification engine 422, and related data structures stored in External Transmit SRAM 412, or 2) an external recipe link to a recipe of modification commands stored in External Transmit SRAM 412 and related data structures also stored in External Transmit SRAM 412.

[0107] The sequencer 410 also assigns a sequence number to the packet to prevent packet re-ordering. It then directs the Transmit RAM arbiter 416 to read the recipe of modification commands stored in the External Transmit SRAM 412 (assuming the TXMI link is an external recipe link) or Internal Recipe RAM 414 (assuming the TXMI link is an internal recipe link) and store the same in Recipe RAM 418, an on-chip RAM in relation to modification engine 422. It further directs the arbiter 416 to read the data structures associated with the specified internal or external recipe command sequence, and store the same in Data RAM 420, another on-chip RAM in relation to modification engine 422.

[0108] The sequencer 410 then awaits an available slot in the pipeline of the modification engine 422. When such is available, the sequencer 410 passes to the engine 422 for placement in the slot a pointer to the recipe as stored in Recipe RAM 418 and other related information.

[0109] The sequencer 410 assigns a fragment buffer to the packet. The fragment buffer is a buffer within a plurality of fragment buffers which collectively may be referred to as TX work buffer 436. The modification engine then executes the recipe for the packet or packet burst, through one or more passes through the modification engine pipeline. In one embodiment, the recipe comprises one or more entries, and one or more passes through the pipeline are performed to execute each entry of the recipe.

[0110] In the process of executing the recipe, the modification engine 422 stores the modified fragments of the packet in the fragment buffer allocated to the packet in TX work buffer 436. At the same time, the modification engine 422 stores, in ascending order in fragment format RAM 438, pointers to the modified fragments of the packet as stored in the fragment buffer and pointers to the unmodified fragments of the packet as stored in Transmit In Data FIFO 428.

[0111] When all the recipe entries have been executed, the modification engine 422 writes an entry to the fragment CAM 440, the entry comprising the PBUS channel over which the packet was received, the sequence number for the packet, the SOP pointer to the packet (as stored in the Transmit In Data FIFO 428), a packet to be filled flag, a packet offset in the Transmit In Data FIFO 428, and the total length of the list of fragments as stored in the fragment format RAM 438. This completes the processing of the packet by the modification engine 422.

[0112] Fragment/burst processor 442 assembles the packets for ultimate egress from the system. To prevent packet re-ordering, the fragment/burst processor 442 processes, for each PBUS channel, the packets in the order in which they were received by the modification system 400. More specifically, the fragment/burst processor 442 maintains an expected next sequence number for each PBUS channel, and then performs, in round robin fashion, CAM searches in fragment CAM 440 for an entry bearing the expected next sequence number for the channel. If an entry is found with that sequence number, the fragment/burst processor 442 processes it. If such an entry is not found, the fragment/burst processor 442 takes no action with respect to the channel at that time, and proceeds to process the next channel.

[0113] When a fragment CAM entry with the expected next sequence number is located, the fragment/burst processor 442 directs assembler 446 to assemble the packet responsive to the fragment list for the packet as stored in the fragment format RAM 438. In one embodiment, the assembler 446 is a multiplexor, which is directed to multiplex between outputting on second data path 444, responsive to the fragment list, the modified packet fragments as stored in the TX work buffer 436 and the unmodified packet fragments as stored in the Transmit In Data FIFO 428 (as provided to the multiplexor 446 over data path 434). Through this process, the packet is assembled in ascending order on second data path 444. In one embodiment, the second data path 444 has a width less than the width of the first data path 402. In one implementation, the fragment/burst processor 442 outputs the packets over data path 444 in the form of bursts.

[0114] The assembled packet is parsed by the third packet parser 448 in the manner described previously. The resultant context pointers and status flags are then passed, along with the packet, for concurrent processing by Transmit Processor Block 452 and Transmit ACL Logic 454.

[0115] The Transmit Processor Block 452 performs two main functions. First, it performs egress mark processing by selectively modifying one or more QoS fields in the packet responsive to the egress mark control information from the packet stored by the modification engine in Transmit Post Processor RAM 456. In one example, any of the VLAN VPRI, MPLS EXP, and IPv4/IPv6 TOS fields may be modified through this process utilizing the VPRI/EXP/IPToS RAMs 458 as appropriate. The egress mark control information may be derived from one or more egress mark commands specified by an AFH pre-pended to the packet, or from one or more egress mark commands within a recipe for the packet. Second, it performs OSI Layer 3/Layer 4 checksum calculation or modification.

[0116] The Transmit ACL logic 454 conducts a CAM search for the packet in Egress ACL CAM 460 to determine if the packet should be killed, a copy sent to the host, or mirrored to the egress mirror FIFO 140. The packet then exits the packet modification system 400 through the egress portion 462 of the system 400, and is output onto PBUS 464.

[0117] FIG. 5 illustrates a cascaded combination 500 of multiple, replicated packet systems, each of which is either a packet classification system or a packet modification system. In one embodiment, the cascaded combination comprises a first one 502 of the replicated packet systems having ingress and egress portions, identified respectively with numerals 504 and 506, and a second one 508 of the replicated packet systems having ingress and egress portions, identified respectively with numerals 510 and 512.

[0118] In this embodiment, the egress portion 506 of the first packet system 502 is coupled to the ingress portion 510 of the second packet system 508. Moreover, the first one 502 of the replicated packet systems is configured to perform partial processing of a packet, either classification or modification processing as the case may be, and the second one 508 of the replicated packet systems is configured to complete processing of the packet.

[0119] In one configuration, packet system 508 forms the last one of a plurality of systems in the cascaded combination, and packet system 502 forms either the first or the next to last one of the systems in the cascaded combination.

[0120] In one example, each of the replicated systems performs a limited number of processing cycles, and the number of replicated systems is chosen to increase the number of processing cycles to a desired level beyond that achievable with a single system.

[0121] In a second example, a complete set of processing functions or tasks is allocated amongst the replicated systems. In one configuration, a first replicated system is allocated ACL and QoS classification processing tasks, and a second replicated system is allocated PTI/TXMI classification processing tasks.

[0122] FIG. 6 is a flowchart of one embodiment 600 of a method of processing a packet. In this embodiment, the method comprises step 602, parsing a packet and providing first data representative thereof, and step 604, classifying the packet responsive to the first data.

[0123] In step 606, the packet is forwarded to and received from switching fabric, which may perform additional processing of the packet. Step 608 comprises parsing the packet received from the switching fabric (which may be the packet forwarded to the switching fabric, or a packet derived there-from), and providing second data representative thereof.

[0124] Step 610 comprises modifying the packet responsive to the second data, and step 612 comprises parsing the modified packet and providing third data representative thereof. Step 614 comprises post-processing the modified packet responsive to the third data.

[0125] In one embodiment, the packet undergoing processing has a plurality of encapsulation layers, and each of the first, second and third parsing steps 602, 608, 612 comprising providing context pointers pointing to the start of one or more of the encapsulated layers of the packet.

[0126] In a second embodiment, the packet undergoing processing comprises a first packet forming the payload portion of a second packet, each of the first and second packets having a plurality of encapsulation layers, and each of the first, second and third parsing steps 602, 608, 612 comprises providing context pointers pointing to the start of one or more of the encapsulated layers of the first packet and one or more of the encapsulated layers of the second packet.

[0127] In one implementation, the post-processing step comprises computing a checksum for the modified packet. In a second implementation, the post-processing step comprises egress marking of the packet. In a third implementation, the post-processing step comprises the combination of the foregoing two implementations.

[0128] FIG. 7 is a flowchart of a second embodiment 700 of a method of processing a packet. In this embodiment, step 702 comprises analyzing a packet in a packet classification system and, responsive thereto, selectively changing the state of a control bit from a first state to a second state. Step 704 comprises forwarding the packet to and from switching fabric. Step 706 comprises modifying, in a packet modification system, the packet received from the switching fabric (either the packet forwarded to the switching fabric, or a packet derived there-from), detecting the control bit to determine if egress mirroring of the modified packet is activated, and if so, providing a copy of the modified packet to the packet classification system.

[0129] In one implementation, the control bit is associated with the packet received from the switching fabric. In one example, the control bit is in a packet header pre-pended to the packet received from the switching fabric.

[0130] FIG. 8 is a flowchart of a third embodiment 800 of a method of processing a packet. Step 802 comprises providing a multi-dimensional quality of service (QoS) indicator for a packet. Step 804 comprises forwarding the packet to and from switching fabric. Step 806 comprises egress marking of the packet received from the switching fabric (either the packet forwarded to the switching fabric, or a packet derived there-from), responsive to at least a portion of the multi-dimensional QoS indicator.

[0131] In one implementation, step 806 comprises selectively modifying one or more quality of service fields within the packet received from the switching fabric responsive to at least a portion of the multi-dimensional quality of service indicator.

[0132] In one configuration, the multi-dimensional quality of service indicator comprises an ingress quality of service indicator, an egress quality of service indicator, and packet marking control information, and step 806 comprises selectively modifying one or more quality of service fields within the packet received from the switching fabric responsive to the packet marking control information. In one example, the multi-dimensional quality of service indicator further comprises a host quality of service indicator.

[0133] In one embodiment, the method further comprises utilizing the ingress quality of service indicator as an ingress queue select. In a second embodiment, the method further comprises utilizing the egress quality of service indicator as an egress queue select. In a third embodiment, the method further comprises utilizing the host quality of service indicator as an ingress queue select for a host.

[0134] FIG. 9 is a flowchart of an embodiment 900 of assigning a quality of service indicator to a packet. In this embodiment, step 902 comprises providing a plurality of quality of service indicators for a packet, each with an assigned priority, and step 904 comprises utilizing a configurable priority resolution scheme to select one of the plurality of quality of service indicators for assigning to the packet.

[0135] In one implementation, step 902 comprises mapping one or more fields of the packet into a quality of service indicator for the packet and an associated priority. In a second implementation, step 902 comprises performing a search to obtain a quality of service indicator for the packet and an associated priority. A third implementation comprises a combination of the foregoing two implementations.

[0136] FIG. 10 is a flowchart of an embodiment 1000 of a method of classifying a packet. In this embodiment, step 1002 comprises slicing some or all of a packet into portions and providing the portions in parallel over a first data path having a first width to a classification engine. Step 1004 comprises classifying, in the packet classification engine, the packet responsive to the packet portions received over the first data path and providing data representative of the packet classification. Step 1006 comprises associating the data representative of the packet classification with the packet to form an associated packet, and providing the associated packet over a second data path having a second width less than the first width.

[0137] In one implementation, the step of providing the packet portions over the first data path comprises providing each of the bits of some or all of the packet in parallel over the first data path to the classification engine.

[0138] In a second implementation, the associating step comprises multiplexing the data representative of the packet classification and some or all of the packet onto the second data path.

[0139] FIG. 11 is a flowchart of an embodiment 1100 of a method of modifying a packet. Step 1102 comprises providing some or all of a packet as packet portions and providing the portions in parallel over a first data path having a first width to a modification engine. Step 1104 comprises modifying, in the modification engine, one or more of the packet portions. Step 1106 comprises assembling a packet from the one or more modified and one or more unmodified packet portions, and providing the assembled packet over a second data path having a second width less than the first width.

[0140] FIG. 12 is a flowchart 1200 of an embodiment of a method of classifying a packet. Step 1202 comprises placing an identifier of a packet on a first FIFO buffer. Step 1204 comprises popping the identifier off the first FIFO buffer and placing it on a second FIFO buffer upon or after initiation of classification processing of the packet. Step 1206 comprises avoiding outputting the packet while an identifier of the same is placed on either the first or second FIFO buffers. Step 1208 comprises outputting the packet upon or after the identifier of the packet has been popped off the second FIFO buffer.

[0141] FIG. 13 is a flowchart illustrating an embodiment 1300 of a method of maintaining packet statistics. Step 1302 comprises allocating a packet size determiner to a packet from a pool of packet size determiners. Step 1304 comprises using the packet size determiner to determine the size of the packet. Step 1306 comprises updating one or more packet statistics responsive to the determined size of the packet. Step 1308 comprises returning the packet size determiner to the pool upon or after the same has determined the size of the packet.

[0142] In one implementation, the packet size determiner is a counter that counts the size of the packet. In a second implementation, the method further comprises queuing one or more statistics update requests.

[0143] In one implementation example, the one or more packet statistics indicate the cumulative size of packets which have met specified processing conditions or hits, and step 1306 comprises incrementing a cumulative size statistic for a particular processing condition or hit by the determined size of the packet if the packet meets that particular processing condition or hit.

[0144] FIG. 14 illustrates an embodiment 1400 of a method of classifying a packet. Step 1402 comprises buffering a packet in a buffer upon or after ingress thereof. Step 1404 comprises classifying the packet and providing data representative of the packet classification. Step 1406 comprises associating the data representative of the packet classification with some or all of the packet as directly retrieved from the buffer to form a packet on an egress data path.

[0145] In one implementation, step 1406 comprises multiplexing the data representative of the packet classification onto a data path followed by some or all of the packet as directly retrieved from the buffer.

[0146] FIG. 15 illustrates an embodiment 1500 of a method of modifying a packet. Step 1502 comprises buffering the packet in a buffer upon ingress thereof. Step 1504 comprises modifying one or more portions of the packet. Step 1506 comprises assembling the one or more modified portions of the packet with one or more unmodified portions of the packet as retrieved directly from the buffer to form an assembled packet on an egress data path.

[0147] In one implementation, the method comprises providing a list indicating which portions of the assembled packet are to comprise modified portions of an ingress packet, and which portions are to comprise unmodified portions of the ingress packet, and step 1506 comprises assembling the assembled packet responsive to the list.

[0148] FIG. 16 illustrates an embodiment 1600 of a method of processing a packet in a cascaded combination of multiple, replicated packet processing systems. In one implementation, each of systems is either a packet classification system or a packet modification system, and the processing which is performed by each system is either classification processing or modification processing as the case may be. Step 1602 comprises performing partial processing of a packet in a first of the replicated packet processing systems, and step 1604 comprises completing processing of the packet in a second of the replicated packet processing systems.

[0149] In one implementation, the second packet processing system is the last of a plurality of replicated packet processing systems, and the first packet processing system is either the first or next to last packet processing system in the plurality of packet processing systems, wherein partial processing of a packet is performed in the first replicated packet processing system, and processing is completed in the second replicated packet processing system.

[0150] FIG. 17 illustrates an embodiment 1700 of a method of preventing re-ordering of packets in a packet processing system. Step 1702 comprises assigning a sequence number to a packet upon or after ingress thereof to the system. Step 1704 comprises processing the packet. Step 1706 comprises storing data representative of the packet in a buffer. Step 1708 comprises checking the buffer for an entry matching an expected next sequence number. Inquiry step 1710 comprises determining if a match is present. If so, steps 1712 and 1714 are performed. Step 1712 comprises outputting the corresponding packet, and step 1714 comprises updating the expected next sequence number to reflect the outputting of the packet. If not, the method loops back to step 1708, thus deferring outputting a packet if a match is not present.

[0151] In one implementation, steps 1708-1714 comprise maintaining an expected next sequence number for each of a plurality of output channels, checking the buffer for a match for each of the channels, outputting the corresponding packet on a channel if a match for that channel is present and updating the expected next sequence number for that channel, and deferring outputting a packet on a channel if a match for that channel is not present.

Preferred Embodiments of the Invention

[0152] FIG. 18 is a flowchart of an embodiment comprising a method 1800 of parsing a packet. In this method, the packet is assumed to comprise a plurality of packet data units (PDUs) and a plurality of packet layers, each having locations with the packet. The method begins with step 1802, which comprises testing one or more of the packet data units within a first window for the presence of a first packet layer. In one implementation, this testing comprises comparing the data of the PDUs with predetermined headers or tags characteristic of the first packet layer. Thus, in FIG. 19, referring to the PDUs of packet 1900 as a, b, c, etc., an example of this step comprises testing the three PDUs a, b, and c (the three PDUs within the window W₁) for the presence of a first packet layer.

[0153] Turning back to FIG. 18, testing step 1810 is performed at least partially in parallel with testing step 1802. In testing step 1810, one or more of the packet data units within a second window are tested for the presence of a second packet layer. This second window at least partially overlaps the first window to account for the uncertainty in the location of the second packet layer and to ensure that it is not missed. In one implementation, as with testing step 1802, testing step 1810 comprises comparing the data in the PDUs within the second window with predetermined headers or tags characteristic of the second layer. In one example, illustrated in FIG. 19, testing step 1810 comprises testing the three PDUs c, d, e within the second window W₂for the presence of the second layer. As illustrated, in this example, this second window W₂overlaps the first window W₁at the PDU c.

[0154] Turning back to FIG. 18, in query step 1804, the method queries whether the first packet layer has been detected within the first window. If so, step 1806 is performed. If not, step 1808 is performed. In step 1806, the method identifies the location of the first packet layer within the packet. In step 1808, the method sets a flag indicating that the first layer is not present within the packet.

[0155] In one implementation, step 1806 comprises identifying the location of the first packet by forming a pointer pointing to the location of the first layer within the packet. In one example, the pointer is configured to point to the beginning of the first layer in the packet. Also, the pointer may be expressed in absolute or relative terms, e.g., relative to the beginning of the packet.

[0156] In query step 1814, the method queries whether the second layer has been detected in the second window. If so, a branch is made to AND node 1815. If not, a branch is made to AND node 1817. The AND nodes 1815 and 1817 defer final identification of the second layer within the packet (or final determination that the second layer is absent from the packet) until final identification of the first layer within the packet has occurred (or final determination that the first layer is absent from the packet). These actions are deferred because accurate identification of the location of the second layer (or accurate determination that the second layer is absent) sometimes depends on accurate identification of the location of the first layer (or accurate determination that the second layer is absent). For example, the second layer may begin a predetermined number of bytes after the first layer, and deferring final identification of the location of the second layer in this embodiment (or final determination that the second layer is absent in this embodiment) allows a more accurate identification of the location of that layer (or more accurate determination that the second layer is absent).

[0157] The AND node 1815 ensures that the final identification of the location of the second layer within the packet is deferred until the location of the first layer within the packet has been finally identified (or it has been finally determined that the first layer is absent from the packet). Once either of these events has occurred, step 1816 is performed. In step 1816, the location of the second layer within the packet is finally identified. In one implementation, the location of the second layer within the packet is identified through formation of a pointer pointing to the second layer. In one example, the pointer points to the beginning of the second layer. As with the pointer to the first layer, the pointer may be expressed in absolute or relative terms.

[0158] The AND node 1817 ensures that the final determination that the second layer is absent from the packet is deferred until the location of the first layer within the packet has been finally identified (or it has been finally determined that the first layer is absent from the packet). Once either of these events has occurred, step 1818 is performed. In step 1818, a final determination is made that the second layer is absent from the packet.

[0159] The PDUs making up the packet may be of uniform or varying size. In one implementation, they are of a predetermined, uniform size, e.g., 64 bits. Also, the manner of identifying the first and second layers in the packet may comprise forming data identifying, respectively, the first and second layers. In one example, the data represents pointers pointing, respectively, to the first and second layers. In a more specific example, the pointers identify, respectively, the beginning of the first and second layers.

[0160] The method may also comprise testing for the presence of (and identifying if present) additional layers in the packet beyond the first and second layers. For example, in one embodiment, the method comprises testing for the presence of a third packet layer. In this embodiment, this testing occurs at least partially in parallel with either or both testing steps 1802, 1810, and involves the testing of PDUs within a third window that at least partially overlaps the second window. For example, in FIG. 19, this third testing step may comprise testing the three PDUs e, f and g within the third window W₃that overlaps the second window W₂at PDU e. If testing for the presence of the third layer is performed, the final identification of the location of the third layer in this embodiment (or final determination that the third layer is absent from the packet) is deferred until the location of the second layer has been finally identified (or it has been finally determined that the second layer is absent). One of skill in the art would appreciate that the method may also be extended to the testing of four or more packet layers.

[0161] The windows utilized for the various testing steps may be of uniform or varying sizes. Moreover, these windows may overlap adjacent windows on one or both sides. These windows may also overlap adjacent windows in fixed or varying amounts. In one implementation, the windows are of a fixed, uniform size, and overlap adjacent windows by a uniform, fixed amount. The windows also need not be an integral multiple of PDUs. In one example, in which a PDU is 8 bytes in length, each window is 15 bytes in width, and overlaps the adjacent window on the right by 7 bytes. In this example, the first testing step comprises testing for the presence of a first layer in a first PDU and the seven bytes of the immediately adjacent second PDU to its right, and the second testing step comprises testing for the presence of a second layer in this second PDU and the seven bytes of the immediately adjacent third PDU to its right. A third testing step, if present, comprises testing for the presence of a third layer in a third PDU and the seven bytes of the immediately adjacent fourth PDU to its right.

[0162] In one application, the packet is the outer packet of an embedded packet comprising a first inner packet forming the payload portion of a second outer packet. In this application, data identifying the presence of the layer in the packet may be expressed in relation to the beginning of the outer packet. In a second application, the packet is the inner packet of such an embedded packet. In this application, data identifying the presence of the layer in the packet may be expressed in relation to the beginning of the inner packet.

[0163] The foregoing method, or any of the variants, implementations, or examples thereof that have been discussed, may be tangibly embodied as a sequence of software instructions stored on a processor readable medium.

[0164] FIG. 20 illustrates an embodiment of a system 2000 for parsing a packet. In this system, the packet comprises a plurality of PDUs and a plurality of packet layers, each having locations within the packet. In this embodiment, the system comprises a buffer 2002 for buffering a plurality of the PDUs, identified in the figure with a, b, c, etc., a first stage 2004 for testing one or more of the buffered PDUs within a first window for the presence of a first packet layer, and a second stage 2014 for testing one or more of the buffered PDUs within a second window for the presence of a second packet layer.

[0165] In this embodiment, the first stage 2004 is configured to identify the location of the first packet layer within the packet if the first packet layer is detected within the first window; and a second stage 2014 is configured to identify the location of the second packet layer within the packet if the second packet layer is detected within the second window.

[0166] Moreover, the second stage 2014 in this embodiment is configured to operate at least partly in parallel with the first stage 2004. In one example, the second stage 2014 tests for the presence of the second layer within the second window while the first stage 2004 tests for the presence of the first layer within the first window.

[0167] Also, the second window in this embodiment at least partly overlaps the first window. Given the uncertainty in the location of the second layer (at least until the first layer has been located), this overlap helps ensure that the second layer is not inadvertently missed.

[0168] In one embodiment, the first stage 2004 is configured to test for the presence of the first layer by comparing the PDUs within the first window with one or more headers or tags characteristic of the first layer. These one or more headers or tags are input to the first stage over one or more signal lines, identified in the figure with numeral 2006.

[0169] As a result of this comparison, the first stage 2004 makes a determination that the first layer is either present in the packet or absent from the packet. If it is determined that the first layer is present in the packet, the first stage 2004 identifies the location of the first layer within the packet. If it is determined that the first layer is absent from the packet, the first stage 2004 sets a flag to indicate this.

[0170] After a suitable settling time, a clock pulse is received over signal line 2008, signaling the first stage 2004 to latch the results of this process. If the first layer is present in the packet, the location of the first layer within the packet is latched. If the first layer is absent from the packet, a flag indicating this is latched. The latched information in the first stage 2004 is presented over the one or more signal lines 2010. Moreover, a signal indicating that a final determination has been made regarding the presence or absence of the first layer in the packet is provided over signal line 2012, which forms the latching clock input to second stage 2014. That bars the second stage 2014 from making a final determination regarding the presence or absence of a second layer within the packet until the first stage 2004 has completed this task in relation to the first layer.

[0171] In one embodiment, the second stage 2014 is configured to test for the presence of the second layer by comparing the PDUs within the second window with one or more headers or tags characteristic of the second layer. These one or more headers or tags are input to the second stage over one or more signal lines, identified in the figure with numeral 2016.

[0172] As a result of this comparison, the second stage 2014 determines that the second layer is either present in the packet or absent from the packet. If it is determined that the second layer is present in the packet, the second stage 2014 identifies the location of the second layer within the packet. If it is determined that the second layer is absent from the packet, the second stage 2014 sets a flag to indicate this.

[0173] Once a final determination has been made by the first stage that the first layer is present in or absent from the packet, a clock pulse is received over signal line 2012, signaling the second stage 2014 to latch the results of the process of testing for the presence of the second layer. If the second layer is present in the packet, the location of the second layer within the packet is latched. If the second layer is absent from the packet, a flag indicating this is latched. The latched information in the second stage 2014 is presented over the one or more signal lines 2018. Moreover, a signal indicating that a final determination has been made regarding the presence or absence of the second layer in the packet is provided over signal line 2020, which may form the latching clock input to subsequent stages.

[0174] In one implementation, each of the first and second stages 2004, 2014 are implemented as software executing on a processor. In a second implementation, each of these stages is implemented as hardware. In a third implementation, each of these stages is implemented as a combination of hardware and software.

[0175] In one embodiment, the first stage 2004 is configured to identify the location of the first packet layer by forming first data identifying the location of that packet layer, and the second stage 2014 is configured to identify the location of the second packet layer by forming second data identifying the location of that packet layer. In one example, the first data identifies the beginning of the first packet layer, and the second data identifies the beginning of the second packet layer.

[0176] In one application, the packet is the outer packet of an embedded packet comprising a first inner packet forming the payload portion of a second outer packet, and the first and second stages are respectively configured to test for the presence of the first and second packet layers in, respectively, the outer packet. In a second application, the packet is the inner packet of an embedded packet, and the first and second stages are respectively configured to test for the presence of the first and second packet layers in, respectively, the inner packet.

[0177] In the particular example illustrated, the first stage 2004 is shown testing for the presence of the first layer in three PDUs a, b, and c within a first window W₁, and the second stage 2014 is shown testing for the presence of the second layer is three PDUs c, d, and e within a second window W₂overlapping the first window W₁at PDU c, but it should be appreciated that nothing in this particular example should be taken as limiting. In particular, as one of skill in the art would appreciate, examples are possible where the size of the PDUs making up the packet is a fixed, uniform value or alternatively is a value that varies by PDU; where the windows are expressed in terms of integral or fractional multiples of PDUs; where the windows are fixed, uniform sizes or varying sizes; where the windows overlap adjacent windows by fixed amounts or varying amounts; or where the windows overlap either or both adjacent windows on the right and left.

[0178] In one embodiment, the system 2000 further comprises one or more additional stages configured to test for the presence of additional layers within the packet. One of skill in the art would appreciate how to incorporate these stages into the system based on the foregoing discussion. In one example, the system 2000 comprises the following five stages as illustrated in FIG. 21:

- [0179] MAC Stage 2102
- [0180] VLAN Detection Stage 2104
- [0181] Encapsulation Set Extraction Stage 2106
- [0182] MPLS Stage 2108
- [0183] IP Stage 2110

[0184] In this example, the system 2000 is configured to parse a packet comprising a plurality of 64 bit PDUs as received over the receive side PBUS interface 118, or the transmit side PBUS interface 122, as illustrated in FIG. 1. In this example, each of the three instantiations of a parser illustrated in FIG. 1, parsers 126, 130, and 134, comprises the system 2000.

[0185] In each of these instantiations, the system 2000 is configured to begin operation upon the receipt of a start-of-packet (SOP) condition. In this particular example, the system 2000 is limited to testing the first 128 bytes of the packet, i.e., the first 16 PDUs. If an end of packet (EOP) condition is encountered prior to completion of processing of these 128 bytes, the system 2000 will terminate operation upon encountering the EOP condition.

[0186] Upon detecting the SOP condition, the system 2000 in this example first skips over 8 bytes, representing the AFH pre-pended to the packet. As received by parser 126, this AFH is an 8 byte null value pre-pended to the packet by the ingress MAC. As received by parsers 130 and 134, this AFH is populated by various items of packet classification or forwarding information.

[0187] Next, the system 2000 skips over pad and control information to locate the beginning of the MAC header. Since the size of this pad and control information varies depending on the type of interface involved, the system 2000 is provided with information indicating whether the ingress PBUS sub-channel is an Ethernet or Packet-Over-Sonet (POS) interface. If a POS interface, the system 2000 checks the PPID field to determine if the packet requires Bridged or Routed POS services. Based on this information, the system 2000 determines a programmable offset, and uses this programmable offset to skip over the pad and control information and locate the start of the MAC header.

[0188] In the MAC Stage 2102, the system 2000 extracts the MAC DA field and then decodes this MAC DA field to provide a Router Address, and Multicast and Broadcast flags. The system 2000 determines the Router Address by comparing the MAC DA field with one of eight possible Router Addresses, and, if a hit occurs, translating it into the Router Address.

[0189] In the VLAN Detection Stage 2104, the system 2000 tests the EtherType field for the presence of up to two nested VLAN headers, VLAN 0 and VLAN 1. To accomplish this, the system 2000 compares the EtherType field with each of two programmable probe values, Probe 0 and Probe 1, representing possible VLAN headers, and returns a 4 bit matrix representing the match status of the possible combinations of the two probes, i.e., Probe 0:VLAN 0, Probe 0:VLAN 1, Probe 1:VLAN 0, and Probe 1:VLAN 1.

[0190] In the Encapsulation Set Extraction Stage 2106, the system 2000 determines whether the packet is an Ethernet II, LLC or SNAP packet. It also extracts the relevant MAC control field to identify the payload, and to generate several flags identifying required packet services, such as IP v4, IP v6, MPLS, and IPX services.

[0191] In the MPLS Stage 2108, the system 2000 tests for the presence of an MPLS stack, and, if detected, an MPLS header walker is activated to determine the number of MPLS headers that are present in the stack. The MPLS header walker terminates its search upon detection of a Bottom-Of-Stack (S) bit.

[0192] In the case of a packet requiring Routed POS services, the processing performed by stages 2102, 2104, and 2106 is skipped and processing is resumed at the MPSL stage 2108.

[0193] The MPLS Stage 2108 is also configured to support tunneling. FIG. 22 illustrates two examples of other forms of tunneling that could be encountered by MPLS Stage 2108. The first is identified with numeral 2216 and is referred to as MPLS tunneling. The second is identified with numeral 2218 and is referred to as L2 or MAC tunneling. In one embodiment, the MPLS Stage 2108 first checks for MPLS tunneling, and if not present, it checks for L2 or MAC tunneling. If MPLS or L2 tunneling is detected, the MPLS Stage 2108 initiates a Page 1 parser (described below).

[0194] The MPLS Stage 2108 detects a MPLS tunneling condition when it detects a MAC header, identified with numeral 2202, after an MPLS stack, identified with numeral 2204, in lieu of an IP v4 header, identified with numeral 2210, an IP v6 header, identified with numeral 2212, or an IPX header, identified with numeral 2214. The MPLS Stage 2208 detects an L2 tunneling condition when it detects a MAC header, identified with numeral 2206, after the encapsulation set data structure, identified with numeral 2208, in lieu of an MPLS stack, identified with numeral 2204.

[0195] Upon encountering a tunneling condition, the MPLS Stage 2108 enters a paging mode of operation. In this paging mode of operation, the MPLS Stage 2108 associates the parsed data produced to date, i.e., the context pointers and flags, with a first page, page 0, initiates a second copy of the parser daisy-chained to the first to parse the remaining portion of the packet, and associates the parsed data produced by this second copy with a second page, page 1. Consequently, the first page (page 0) identifies the parsed data corresponding to the outer packet of the embedded packet, while the second page (page 1) identifies the parsed data corresponding to the inner packet of the embedded packet.

[0196] The IP Stage 2110 is activated upon detection of an initial IP v4 or v6 header structure, and utilizes an iterative process to detect and parse any Next Header structures that are present. Before parsing a detected Next Header structure, the stage 2110 checks a control bit in the structure to determine if parsing of the structure is desired. Separate bits are provided to respectively control v4 and v6 processing. If the control bit indicates that parsing of the structure is not desired, parsing of the structure is avoided or terminated. The IP Stage 2110 supports both PIM (Sparse Mode) and GRE packet decoding. Again, separate control bits are provided in the packet to respectively control v4 and v6 processing.

[0197] The IP Stage 2110 is configured to support up to two nested IP headers (deemed outer and inner) in order to handle IP v4 and IP v6 tunneling and similar services. In the case in which two IP headers are detected, the IP Stage 2110 performs Next Header processing for each of the headers. The IP Stage 2110 decodes fragment information to provide fragment offset information for both inner and outer IP headers. Also, the last IP header found that is not subject to Next Header processing is by definition a layer four header, and therefore the beginning of the layer four data structure within the packet.

[0198] The overall paging mode of operation is illustrated in FIG. 23. During step 2302, the various stages of the system are applied to the outer packet of an embedded packet to produce page 0 parsing data, and in step 2304, these stages are applied to the inner packet of the embedded packet to produce page 1 parsing data. In one example, the system 2000 produces the context pointers of FIG. 24 for each of the pages of an embedded packet.

[0199] An embodiment of a data structure representing a page of an embedded packet is illustrated in FIG. 25. The embedded packet comprises a first packet that forms the payload portion of a second packet. The first and second packets have locations within the embedded packet. Each of the first and second packets comprise one or more packet layers, each having a location within the respective packet. This data structure may be tangibly embodied or stored on a processor readable medium.

[0200] In one example, the data structure illustrated in FIG. 25 represents the outer packet or page of an embedded packet, and is followed by another such data structure representing the inner packet or page of an embedded packet. As illustrated, this data structure includes data that represents the following context pointers:

- [0201] MAC Context Pointer—Starting byte location of MAC header.
- [0202] EtherType Context Pointer—Starting byte location of EtherType/LLC/PPID field.
- [0203] MPLS Context Pointer—Starting byte location of MPLS label stack.
- [0204] L3 Outer Context Pointer—Starting byte location of Outer L3 Header.
- [0205] L3 Inner Context Pointer—Starting byte location of Inner L3 Header.

[0206] L4 Context Pointer—Starting byte location of L4 Structure.

[0207] This data structure also includes data that represents the following packet flags:

- [0208] VLAN Count—Absolute count of the number of VLANs detected in the packet:
- [0209] Permissible values: 0x0, 0x1, 0x2.
- [0210] Reserved: 0x3.
- [0211] VLAN Match Matrix—Matrix reflecting VLAN probe vs. packet VLAN Header comparison:
- [0212] Bits 3:0 correspond respectively to Probe 1:VLAN 1, Probe 1:VLAN 0, Probe 0:VLAN 1, and Probe 0:VLAN 0.
- [0213] VLAN Tags 0,1—VLAN Tags for VLAN Headers 0 and 1 (if present)
- [0214] EtherType—Extracted EtherType/PPID/LLC field.
- [0215] MPLS Label Count—Absolute MPLS Label Count.
- [0216] Outer IP Type—Encodes outer IP Header Type:
- [0217] 0x0—neither.
- [0218] 0x1—IP v4.
- [0219] 0x2—IP v6.
- [0220] 0x3—reserved.
- [0221] Outer IP Fragment Type—Encodes outer IP Fragment type:
- [0222] 0x0—only or single.
- [0223] 0x1—first.
- [0224] 0x2—last.
- [0225] 0x3—middle.
- [0226] Outer IP Don't Fragment.
- [0227] For Outer IP Header—v4, reflects setting of Don't Fragment Flag.
- [0228] For Outer IP Header—v6, always set.
- [0229] Outer IP Protocol—Protocol field resulting from processing of Outer IP Header and any following Next Header structures.
- [0230] Outer IP Next Header Exception—Exception flags for Outer IP Header, covering PIM, GRE and Next Header processing.
- [0231] Inner IP Type—Encodes Inner IP Header type:
- [0232] 0x0—neither.
- [0233] 0x1—IP v4.
- [0234] 0x2—IP v6.
- [0235] 0x3—reserved.
- [0236] Inner IP Fragment Type—Encodes Inner IP Fragment type:
- [0237] 0x0—only or single.
- [0238] 0x1—first.
- [0239] 0x2—last.
- [0240] 0x3—middle.
- [0241] Inner IP Don't Fragment.
- [0242] For Inner IP Header=v4, reflects setting of Don't Fragment flag.
- [0243] For Inner IP Header—v6, always set.
- [0244] Inner IP Protocol—Protocol field resulting from processing of Inner IP Header and any following Next Header structures.
- [0245] Inner IP Next Header Exception—Exception flags for Inner IP Header, covering PIM, GRE and Next Header processing.

[0246] L4 OCS—Ones Complement Sum (OCS) of L3/L4 Structure.

[0247] In one embodiment, the context pointers are expressed in relation to the beginning of the respective page. Thus, the context pointers for the first page (page 0) are expressed in relation to a pointer to the beginning of the first page, while the context pointers for the second page (page 1) are expressed in relation to a pointer to the beginning of the second page.

[0248] In one application, different portions of the data structure of FIG. 25 are utilized by each of the three instantiations of parser illustrated in FIG. 1. FIG. 26 illustrates the portions of this data structures utilized, respectively, by these three instantiations, identified, respectively, with numerals 126, 130 and 134.

[0249] In one implementation example, any of the foregoing systems and methods may be implemented or embodied as one or more application specific integrated circuits (ASICs).

[0250] While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention.

Claims

What is claimed is:

1. A method of parsing a packet in a system comprising one or more processors, the packet comprising a plurality of packet data units and a plurality of packet layers, each having locations, the method comprising:

testing one or more of the packet data units within a first window for the presence of a first packet layer;

identifying the location of the first packet layer within the packet if the first packet layer is detected within the first window;

testing one or more of the packet data units within a second window for the presence of a second packet layer, the second packet layer corresponding to a layer in an applicable reference model distinct from that the first packet layer corresponds to, the one or more packet data units in the second window partially but not completely overlapping the one or more packet data units in the first window to account for uncertainty in the location of the second layer relative to the first, and the testing of the one or more packet data units in the second window occurring in parallel with the testing of the one or more packet data units in the first window, such that parallel testing for the presence of the first and second packet layers is performed; and

as part of or following this parallel testing, identifying the location of the second packet layer within the packet if the second packet layer is detected within the second window, including deferring completing such identifying until after completing the identifying of the location of the first packet layer or it has been determined that such first layer is absent from the packet, to allow more accurate identification of the location of the second packet layer relative to the first.

2. The method of claim 1 wherein the packet data units are of a predetermined size.

3. The method of claim 1 wherein the step of identifying the location of the first packet layer within the packet comprises forming first data identifying the location of the first packet layer.

4. The method of claim 3 wherein the first data identifies the beginning of the first packet layer.

5. The method of claim 3 wherein the first data is expressed in absolute terms.

6. The method of claim 3 wherein the first data is expressed in relative terms.

7. The method of claim 6 wherein the packet is the outer packet of an embedded packet, and the first data is expressed relative to the location of the outer packet.

8. The method of claim 7 wherein the first data is expressed relative to the beginning of the outer packet.

9. The method of claim 6 wherein the packet is the inner packet of an embedded packet, and the first data is expressed relative to the location of the inner packet.

10. The method of claim 9 wherein the first data is expressed relative to the beginning of the inner packet.

11. The method of claim 3 wherein the first data is pointer data.

12. The method of claim 1 wherein the step of identifying the location of the second packet layer with the packet comprises forming second data identifying the location of the second packet layer.

13. The method of claim 12 wherein the second data identifies the beginning of the second packet layer.

14. The method of claim 12 wherein the second data is expressed in absolute terms.

15. The method of claim 12 wherein the second data is expressed in relative terms.

16. The method of claim 15 wherein the packet is the outer packet of an embedded packet, and the second data is expressed relative to the location of the outer packet.

17. The method of claim 16 wherein the second data is expressed relative to the beginning of the outer packet.

18. The method of claim 15 wherein the packet is the inner packet of an embedded packet, and the second data is expressed relative to the location of the inner packet.

19. The method of claim 18 wherein the second data is expressed relative to the beginning of the inner packet.

20. The method of claim 12 wherein the second data is pointer data.

21. The method of claim 1 further comprising testing for the presence of additional packet layers within the packet, and identifying the locations of such additional packet layers if such are detected within the packet, the additional packet layers being distinct from both the first packet layer and the second packet layer within an applicable reference model.

22. The method of claim 1 wherein the first and second windows are of the same predetermined size.

23. A processor readable medium storing one or more software instructions embodying the method of claim 1.

24. A system for parsing a packet, the packet comprising a plurality of packet data units and a plurality of packet layers, each having locations, the system comprising:

a buffer for buffering a plurality of the packet data units;

a first stage configured to test one or more of the buffered packet data units within a first window for the presence of a first packet layer, and to identify the location of the first packet layer within the packet if the first packet layer is detected within the first window; and

a second stage configured to test one or more of the buffered packet data units within a second window for the presence of a second packet layer, the second packet layer corresponding to a layer of an applicable reference model distinct from that the first packet layer corresponds to, the one or more buffered packet data units in the second window partially but not completely overlapping the one or more buffered packet data units in the first window to account for uncertainty in the location of the second packet layer relative to the first, and the testing of the one or more buffered packet data units in the second window occurring in parallel with the testing of the one or more buffered packet data units in the first window, such that parallel testing for the presence of the first and second packet layers is performed;

the second stage further configured to identify, as part of or following this parallel testing, the location of the second packet layer within the packet if the second packet layer is detected within the second window, and defer completing such identification until after the identification of the location of the first packet layer has been completed or it has been determined that such first layer is absent from the packet, to allow more accurate identification of the location of the second packet layer relative to the first.

25. The system of claim 24 wherein each of the first and second stages are implemented as software executing on a processor.

26. The system of claim 24 wherein the first stage is configured to identify the location of the first packet layer by forming first data identifying the location of that packet layer.

27. The system of claim 26 wherein the first data identifies the beginning of the first packet layer.

28. The system of claim 24 wherein the second stage is configured to identify the location of the second packet layer by forming second data identifying the location of that packet layer.

29. The system of claim 28 wherein the second data identifies the beginning of the second packet layer.

30. The system of claim 24 further comprising one or more additional stages configured to test for the presence of additional packet layers within the packet, the additional packet layers being distinct from both the first packet layer and the second packet layer within an applicable reference model.

31. The system of claim 24 wherein the packet is an embedded packet comprising a first packet forming the payload portion of a second packet, and the first stage is configured to test for the presence of the first packet layer in the first and second packets.

32. The system of claim 24 wherein the packet is an embedded packet comprising a first packet forming the payload portion of a second packet, and the second stage is configured to test for the presence of the second packet layer in the first and second packets.

33. A system for parsing a packet, the packet comprising a plurality of packet data units and a plurality of layers, each having a location within the packet, the system comprising:

buffer means for buffering a plurality of the packet data units;

first stage means for testing one or more of the buffered packet data units within a first window for the presence of a first packet layer, and identifying the location of the first packet layer within the packet if the first packet layer is detected within the first window; and

second stage means for testing one or more of the buffered packet data units within a second window for the presence of a second packet layer, the second packet layer corresponding to a layer of an applicable reference model distinct from that the first packet layer corresponds to, the one or more buffered packet data units in the second window partially but not completely overlapping the one or more buffered packet data units in the first window, and the testing of the one or more buffered packet data units in the second window occurring in parallel with the testing of the one or more buffered packet data units in the first window to account for uncertainty in the location of the second packet layer relative to the first, such that parallel testing for the presence of the first and second packet layers is performed; and (2) identifying, as part of or following this parallel testing, the location of the second packet layer within the packet if the second packet layer is detected within the second window, including deferring completing such identifying until after the identifying of the location of the first packet layer has been completed or it has been determined that such first layer is absent from the packet, to allow more accurate identification of the location of the second packet layer relative to the first.

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Abstract