Method and system for processing DMA requests

[0001] The present invention relates to computing systems, and more particularly, to processing direct memory access (“DMA”) operations.

[0002] Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.

[0003] Host systems communicate with various devices using standard network interface and standard computer bus architectures. Direct memory access (DMA) requests are used to move data to/from a host system memory. DMA modules (also referred to as channels) are typically used to move data to and from a host system memory. DMA modules provide address and control information to generate read and write accesses to host memory.

[0004] A single DMA channel typically breaks up a DMA data transfer request from a host system into smaller requests to comply with interface protocol requirements. Some of the factors affecting the break up of a DMA request include payload size requirement and address boundary alignment on a PCI-X/PCI-Express interface (or any other interface), and frame size negotiation on fibre channel interface and others.

[0005] In conventional systems, often a DMA channel generates a request with a fixed or minimum frame size. This is based on being able to transfer a packet/frame (collectively referred to as data) of a particular size. However, a DMA channel may have more data available for transfer between the time it generates the DMA request and when an arbitration module grants access. The conventional approach of generating DMA requests based on fixed size is static and undesirable because the DMA channel can only transfer data that it specifies in the DMA request regardless of whether more data is available for transfer. This shortcoming is especially undesirable in high bandwidth network operations (for example, 1 Gigabit (G) to 10 G networks) because it results in latency. Therefore, optimizing DMA request handling continues to be a challenge in the computing industry.

[0006] In one aspect of the present invention, a method for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

[0007] In another aspect of the present invention, a system for processing direct memory access (DMA) requests in a peripheral device is provided. The system includes a host system operationally interfacing with the peripheral device. The peripheral device includes a DMA module for generating a DMA request to transfer information to/from the host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and an arbitration module that receives the DMA request from the DMA module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

[0008] In yet another aspect of the present invention, an input/output peripheral device is provided. The device includes a DMA module for generating a direct memory access (“DMA”) request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and an arbitration module that receives the DMA request from the DMA module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

[0009] This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings.

[0017] To facilitate an understanding of the preferred embodiment, the general architecture and operation of a storage area network (SAN), and a host bus adapter (HBA) will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the SAN and HBA.

Host System/HBA:

[0018] Host systems often communicate with peripheral devices via an interface/bus such as the Peripheral Component Interconnect (“PCI”) interface, incorporated herein by reference in its entirety. PCI-X is another bus standard that is compatible with existing PCI cards using the PCI bus. The PCI-X standard is also incorporated herein by reference in its entirety.

[0019] PCI-Express (incorporated herein by reference in its entirety) is yet another standard interface used by host systems to interface with peripheral devices. PCI-Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that uses discrete logical layers to process inbound and outbound information.

[0020] Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.

[0021] Host systems are used in various network applications, including SANs. In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters, for example, host bus adapters (“HBAs”).

[0022] HBAs (a PCI/PCI-X/PCI-Express device) that are placed in SANs receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing. HBAs operate as a transmitting device as well as a receiving device.

[0023] DMA modules in HBAs are used to perform data transfers between host memory and the HBA without host processor intervention. The local HBA processor, for example 106A in FIG. 1B, initializes and sets up the DMA channel registers with the starting address of the host memory and length of the data transfer. In conventional methods, the smallest unit of transfer required to comply with the network interface (for example, the Fibre Channel interface) protocol typically fixes the size of the DMA burst. For example, in a fibre channel environment, a DMA request size is based on a single fibre channel frame. Therefore, to transfer multiple frames, multiple DMA requests are generated, which results in latency and inefficiencies.

[0024] A DMA read request is a request from a DMA module (or channel) to transfer data from a host system to a storage device. A DMA write request is a request from a DMA module to transfer data from the storage device to a host system.

[0025] HBAs typically implement multiple DMA channels with an arbitration module that arbitrates for the access to a PCI/PCI-X bus or PCI-Express link. This allows an HBA to switch contexts between command, status and data. Multiple channels are serviced in periodic bursts.

[0026] FIG. 1A shows a SAN system 100 that uses a HBA 106 (may also be referred to as “adapter 106”) for communication between a host system with host memory 101 with various systems (for example, storage subsystem 116 and 121, tape library 118 and 120, and servers 117 and 119) using fibre channel storage area networks 114 and 115. The host system uses a driver 102 that co-ordinates data transfers via adapter 106 using input/output control blocks (“IOCBs”).

[0027] A request queue 103 and response queue 104 is maintained in host memory 101 for transferring information using adapter 106. The host system communicates with adapter 106 via a bus 105 through an interface described below with respect to FIG. 1B.

[0028] FIG. 1B shows a block diagram of adapter 106. Adapter 106 includes processors (may also be referred to as “sequencers”) “RSEQ” 109 and “XSEQ” 112 for receive and transmit side, respectively for processing data received from storage sub-systems and transmitting data to storage sub-systems. Transmit path in this context means data path from host memory 101 to the storage systems via adapter 106. Receive path means data path from storage subsystem via adapter 106. It is noteworthy, that only one processor is used for receive and transmit paths, and the present invention is not limited to any particular number/type of processors. Buffers 111A and 111B are used to store information in receive and transmit paths, respectively.

[0029] Besides dedicated processors on the receive and transmit path, adapter 106 also includes processor 106A, which may be a reduced instruction set computer (“RISC”) for performing various functions in adapter 106.

[0030] Adapter 106 also includes fibre channel interface (also referred to as fibre channel protocol manager “FPM”) 113 that includes modules 113A and 113B in receive and transmit paths, respectively (shown as “FC RCV” and “FC XMT”). Modules 113A and 113B allow data to move to/from storage systems and are described below in detail. Frames 146A are received from a fibre channel network, while frames 146B are transmitted to the fibre channel network.

[0031] Adapter 106 is also coupled to external memory 108 and 110 via connection 116A/116B (FIG. 1A) (referred interchangeably, hereinafter) and local memory interface 122. Memory interface 122 is provided for managing local memory 108 and 110. Local DMA module 137A is used for gaining access to a channel to move data from local memory (108/110). Adapter 106 also includes a serial/de-serializer (shown as “XGXS/SERDES”) 136 for converting data from 10-bit to 8-bit format and vice-versa, and is described below in detail.

[0032] Adapter 106 also includes request queue DMA channel (0) 130, response queue (0) DMA channel 131, response queue (1) 132A, and request queue (1) DMA channel 132 that interface with request queue 103 and response queue 104; and a command DMA channel 133 for managing command information. DMA channels are coupled to an arbiter module (204, FIG. 2B) that receives requests and grants access to a certain channel.

[0033] Both receive and transmit paths have DMA modules “RCV DATA DMA” 129A and 129B and “XMT DATA DMA” 135 that are used to gain access to a channel for data transfer in the receive/transmit paths. Transmit path also has a scheduler 134 that is coupled to processor 112 and schedules transmit operations.

[0034] The host processor (not shown) sets up command/control structures in the host memory 101. These control structures are then transferred into the Local (or External) Memory 108 (or 110) by the local RISC processor 106A. The local RISC processor then executes them with the help of the appropriate sequencer (i.e. 109 or 112).

[0035] PCI Express (or PCI-X) master interface 107A and PCI target interface 107B are both coupled to a PCI-Express Core (or PCI-X core) logic 137 (may also be referred to as “logic 137”). Logic 137 is coupled to a host system. Interface 107A and 107B include an arbitration module that processes DMA access to plural DMA channels.

[0036] FIG. 2A shows examples of slots 0-7 of transmit buffer 111B. Transmit buffer 111B has various slots (shown as 0-7). Each slot operates independently, i.e. read and written independently. A status is sent to scheduler 134 when a particular slot is ready to be written. Scheduler 134 schedules a write operation, when a slot is ready to be written. DMA requests are used to gain access to bus 105 to move data to slots 0-7.

[0037] Read buffer 111A also has a similar configuration as transmit buffer 111B, except it is used to stage frames/data that is being received from the network before being transferred to host system memory.

[0038] FIG. 2B shows an example of a generic system that optimizes DMA request handling for both transmit/receive sides (i.e. for reading or writing data to/from a host system memory), according to one aspect of the present invention. A buffer (similar to buffers 111A and 111B) has plural slots. These slots send a status to plural DMA modules (shown as 201 and 203) when they become available to accept data (slot empty status) for transmission to a fibre channel interface (113) or send data (slot full status) when receiving from the fibre channel interface. The DMA modules in FIG. 2B are similar to the DMA modules 135 and 129A/129B.

[0039] DMA requests are generated by DMA modules (shown as 202 and 203) after they are initiated by processor 106A. All DMA requests are sent to an arbitration module (shown as arbiter logic 204) that arbitrates between plural DMA requests. Arbiter 204 checks to see if slots are available to accommodate the DMA request size. Arbiter 204 grants access to a DMA request, which means a particular DMA channel has access to the bus (shown as 206) via bus interface logic 205 (similar to modules 137, 107A and 107B).

[0040] In one aspect of the present invention, DMA 202 generates a request based on a minimum data transfer size (for example, 2K) to comply with network interface requirements. This indicates to the arbiter 204 the size of the data transfer. However, while arbiter 204 is arbitrating (i.e. before the request is granted), if DMA module gets status availability indicators from other slots, then DMA module 202 can aggregate status information from multiple slots and request a transfer size that is greater than the minimum size. At grant, the transfer size is fixed and is based on the available slots. This dynamic DMA request size allocation ensures that the optimum amount of data is transferred within a single request. With this new adaptive method, multiple frames are transferred with a single DMA request instead of one DMA request per frame in conventional methods.

[0041] The foregoing examples have been described with respect to a HBA in a SAN. However, the adaptive aspects of the present invention are applicable in a more generic manner to any I/O device coupled to a host computing system. An example of one such architecture is shown in FIG. 3 where an interface device 300 is coupled to a host CPU 101A and a host memory 101 via a bus 105. Device 300 interfaces with host CPU 101A via a host interface 303.

[0042] Device 300 includes transmit buffer 111B, DMA module 134 and a processor 301 (similar to processor 106A). Traffic 302 is sent/received from a network. Transmit buffer 111B and DMA module 134 (that also includes a scheduler 135 (not shown) performs similar function that has been described above. The DMA request processing, according to one aspect of the present invention is now described below with respect to FIG. 4.

[0043] Turning in detail to FIG. 4, the host system generates an IOCB that commands HBA 106 to transfer data S400. The IOCB provides the total size of the transfer and the address from where the information is to be transferred. A request queue 103 and a response queue 104 are used to manage the IOCBs (FIG. 1A).

[0044] In step S402, a DMA module (e.g. 202) generates a DMA request to transfer data. It is noteworthy that plural DMA modules can generate requests at any given time. The DMA request specifies a minimum size “A” and the address where the information is transferred (derived from the IOCB).

[0045] In step S404, while arbiter 204 arbitrates between plural DMA requests, the DMA module (for example, 202) monitors the status from the slots in buffer 201. If another slot becomes available, then the DMA module changes the data transfer size accordingly.

[0046] In step S406, based on the status from the buffer slots, the DMA size is changed before arbiter 204 grants the request. The number of available slots from where data can be transferred keeps changing before the grant. The DMA module optimizes the data transfer size depending on the available buffer slots. Thereafter, in step S408, the arbiter 204 grants the request. The DMA size is fixed when the DMA request is granted.

[0047] In one aspect of the present invention, an optimum data transfer size is used for each DMA request, instead of using a fixed frame size for every request. This reduces latency in transferring data and improves overall performance.

[0048] Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.