US 7,593,259 B2Grant
Flash multi-level threshold distribution scheme
Issue Date:2009-09-22
•16 Claims
•14 Drawing Sheets
Abstract
A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
Metadata
Assignee
- MOSAID Technologies Incorporated
Inventor
- Jin-Ki Kim
Application Information
Application Number:US 11/762,330
Filing Date:2007-06-13
Priority Date:2006-09-13
Art Unit:2827
Classifications
IPC:
G11C11/34
Patent Drawings (14 sheets)
Description
Cross Reference to Related Applications
[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 60/844,154 filed on Sep. 13, 2006 which is incorporated herein by reference in its entirety.
Field of the Invention
[0002] The present invention relates generally to Flash memory. More particularly, the present invention relates to a Flash memory device, a method for programming of Flash memory cell and a method for and a method for verifying a threshold voltage.
Background of the Invention
[0003] Numerous types of consumer electronics products rely on some form of mass storage for retaining data or software for the execution of code by a microcontroller. Such consumer electronics are prolific, and include devices such as personal digital assistants (PDA's), portable music players, portable multimedia players (PMP's) and digital cameras. In PDA's, mass storage is required for storing applications and data, while portable music players and digital cameras require large amounts of mass storage for retaining music file data and/or image data. The mass storage solution for such portable electronics is preferably small in size, consumes minimal power, and has high storage density. This limits the selection to non-volatile forms of memory since volatile memories, such as static random access memory (SRAM) and dynamic random access memory (DRAM), require a constant application of power in order to retain data. As is known in the art, portable electronics rely on batteries that have a finite power supply. Therefore, non-volatile memories that retain data after power is removed are preferred.
[0004] While many consumer products use commodity Flash memory, Flash memory is indirectly used by consumers in products such as cell phones and devices with microprocessing functions. More specifically, the application specific integrated circuits (ASIC) commonly found in consumer electronics can have integrated Flash memory to enable firmware upgrades. Needless to say, Flash memory is versatile due to its optimal balance in size, storage density, and speed, making it a preferred non-volatile mass storage solution for consumer electronics.
[0005] FIG. 1 is a block diagram of a typical Flash memory device. Flash memory 10 includes logic circuitry for controlling various functions of the Flash circuits, registers for storing address and data, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the Flash memory array. The functions of the shown circuit blocks of Flash memory 10 should are well known in the art. Persons skilled in the art will understand that Flash memory 10 shown in FIG. 1 represents one possible Flash memory configuration among many possible configurations.
[0006] A read operation is a relatively straightforward access of data stored at a particular memory location of the memory array, called an address. Prior to a write operation to a specific block of the memory array, the specific block must first be erased with the application of high voltages. A write operation, more accurately called a program operation, requires the careful application of high voltages to a selected memory location, followed by a program verify operation to ensure that the data has been properly programmed. Furthermore, since high voltages are used, the Flash chip must be designed to be relatively tolerant to inadvertent programming of non-selected memory cells.
[0007] FIG. 2 is a circuit schematic showing a NAND cell string used in memory cell array shown in FIG. 1 . FIG. 2 is a circuit schematic of two NAND memory cell strings. Each NAND memory cell string includes 32 serially connected floating gate memory cells 50 each connected to respective wordlines WL0 to WL31, a string select transistor 52 connected between the bitline 54 and the first floating gate memory cell 50, and a ground select transistor 56 connected between a common source line (CSL) 58 and the last floating gate memory cell 50. The gate of string select transistor 52 receives a string select signal SSL, while the gate of ground select transistor 56 receives a ground select signal GSL. The NAND memory cell strings of a block share common wordlines, string select SSL, and ground select GSL signal lines. The construction and arrangement of the shown NAND memory string is well known in the art.
[0008] As previously mentioned, the NAND memory cell strings of the memory array are first erased, according to well-known techniques in the art. Each block of NAND memory cell strings can be selectively erased; therefore one or more blocks can be simultaneously erased. When successfully erased, all erased floating gate memory cells 50 will have a negative threshold voltage. In effect, all erased memory cells 50 are set to a default logic state, such as a logic “1”, for example. Programmed memory cells 50 will have their threshold voltages changed to a positive threshold voltage, thus representing the opposite “0” logic state.
[0009] FIG. 3 is a cross-sectional schematic of a typical Flash memory cell. A structure of such cells in well known in the art. Generally, control gate 60 is connected to a word line, while the floating gate 62 is isolated from all other nodes by an oxide insulator 61. Electrons (charge carriers) are injected into or ejected from floating gate 62 and substrate 68 having a source 64 and a drain 66, through thin tunneling oxide 63 between floating gate 62 and substrate 68.
[0010] FIG. 4 is a cross-sectional schematic of a nitride ROM cell having charge traps. Such a cell is also known in the art. In a nitride ROM cell, the floating gate is eliminated and the data is placed in a “holding chamber” or “charge traps” of the non-conductive layer 72, for example, of silicon nitride, between the control gate 70 and substrate 78 having a source 74 and a drain 76. Recently, silicon nanocrystals have also been used as charge traps.
[0011] Generally, a cell is programmed by applying a high voltage to its gate while keeping its source and drain terminals grounded. The high electrical field causes electrons in the memory cell channel to cross the gate oxide and embed in the floating gate (known as Fowler-Nordheim (F-N) Tunneling), thereby increasing the effective threshold voltage of the memory cell.
[0012] Due to the ever-increasing need for size reduction as well as the desire to increase the density of data storage, multi-level FLASH cells are now being widely used. As the name suggests, multi-level cells have more than two logic states per cell. A single cell storing two bits of information has 4 logic states corresponding to different levels of charge levels stored in the floating gates (or charge traps). Generally, a multi-level cell capable of storing N binary bits of data will have 2N states or logic levels.
[0013] However, each floating gate transistor has a certain total range of threshold voltages in which it may practically be operated. The total range is divided into the number of states defined for the memory cell including allowances for clear distinction of one state from another. Variations in fabrication processes and ageing of the device may cause shifts in the threshold voltages. These shifts can weaken the strength of cell states by moving one state closer to the next state. Also, as more levels are squeezed into a fixed total range (for example, fixed supply-voltage range), the tolerance for these shifts decreases.
[0014] FIG. 5 is a threshold voltage (Vt) distribution graph for a multi-level Flash memory cell. The intermediate reference voltages are also shown. This particular graph illustrates the thresholds of a Flash memory cell capable of storing 2 bits of data. Therefore, each multi-level Flash memory cell must store one of four threshold voltages. In this prior art scheme, an erased state represented by a negative threshold voltage lies in an erase voltage domain. All erased memory cells will by default have this negative threshold voltage. The remaining three states must be programmed, and their corresponding threshold voltages will be positive in value and lie in the program voltage domain. In this example, the erase voltage domain is below zero while the program voltage domain is above zero volts. A problem with this scheme is the required tightness of the distribution for each state and the distance between the states.
[0015] Programming is typically done by the page, meaning that all the memory cells 50 in the block connected to the same wordline are selected to be programmed with write data (logic “0”) at the same time. The remaining memory cells are thus unselected during programming. Since the memory cells start in the erased state (logic “1”) prior to programming, only the memory cells to be programmed with the logic “0” should be subjected to the high electric fields necessary to promote F-N tunneling. However, due to the physical connections of the memory array, all the memory cells along the same wordline receive the same high voltage programming level. As a result, there is a potential that erased memory cells will have their threshold voltages unintentionally shifted. This is called program disturb, which is well known in the Flash memory field. This problem is more pronounced in multi-level cells as more levels are squeezed into a fixed voltage range.
[0016] Several parameters such as, Vt window, Vt distance, and Vread distance, are key parameters to determine read/write speed, reliability and lifetime of multi-level flash memory shown in FIG. 5 . These three parameters influence one another: the cell Vt window and the cell Vt distance in a multi-level flash memory are much tighter than those in single-level flash memory since, in the case of a 2 bit cell, three cell states are in the program voltage domain with a positive Vt. If the cell Vt window is wider, the cell Vt distance is narrower. This reduces read sensing margin and eventually leads to a failure to sense neighboring cell states. In other words, Vt overlap or even minimum Vt distance between neighboring cell states leads to device failure.
[0017] The strength or safety margin of a Vt-state is greatest when the Vt is half-way between adjacent reference voltages. Upper and lower limits for each Vt-state defining a cell Vt window may be specified. For example, in FIG. 5 , cell state 0 is between lower limit VL0 (−3 volts) and upper limit VU0 (−2 volts). Cell state 1 is between lower limit VL1 (0.3 volts) and upper limit VU1 (0.8 volts). Typically, the cell Vt window in multi-level flash memory is in between 0.5 to 1.0 volts. Ideally, a narrow cell Vt window is preferred for better definition and distinction of a state.
[0018] The cell Vt distance, which is defined as the difference in Vt between the lower limit of Vt of the threshold voltage range of one cell state and the upper limit of Vt of the threshold voltage range of the previous cell state. For example, the Vt distance between cell state 2 and cell state 1 is 1.5-0.8=0.7 volts. Typically the cell Vt distance in a multi-level flash memory cell is in between 0.7 to 1.0V. As is evident, larger cell Vt distances are preferred.
[0019] It is also desirable to have the Vread distance, the distance between the read pass voltage and the upper limit of the fully programmed state as high as possible. For example, in FIG. 5 , Vread distance is 5.5-3.3=2.2 volts. However, for optimum performance of the memory cell, a lower Vread is preferred as high Vread can cause disturbance. Therefore, there is a trade-off between Vread distance and the value of Vread. Moreover, the fixed supply-voltage range available may determine the maximum Vread value.
[0020] Furthermore, as the number of rewrite (erase & program) cycle increases, the cell Vt window becomes wider by tunnel oxide degradation due to trapped charges. Also, the read pass voltage Vread should be lower to minimize read disturbance to unselected cells in the selected string. However, in order to accommodate the three cell states (in 2 bit cell) in the program voltage domain, the Vread distance has to be maintained at least well above VU3. This increases the level of Vread.
[0021] In order to tightly control the Vt of the programmed cell, incremental step pulse programming (ISPP) has been proposed and widely used in flash memories. FIG. 6 is a graph illustrating the relationship between the number of program pulses applied to a wordline for programming a threshold voltage versus the size of each pulse. Generally, tight threshold voltage distributions can be obtained when the step size of each program pulse is small. However, the trade-off is programming time since more program pulses would be required.
[0022] Accumulated program/erase cycles in multi-level flash memories with the above prior art scheme for cell Vt distribution typically results in well-known problems as described below.
[0023] Repeated charge transfer causes electrons to be trapped in the floating gate and the dielectric, which degrades program and erase characteristics of the cells. Consequently, cells require gradually higher program and erase voltages as the number of erase-program cycle increases; resulting in limiting the number of erase-program cycles on a cell.
[0024] The data retention characteristic in multi-level cells will be drastically degraded due to a small cell Vt distance. Moreover, as the Vt distribution for a given state is larger, the maximum Vt of programmed cells is higher. The higher Vt requires a higher programming voltage Vpgm, and adversely affects the data retention characteristics due to the larger electric field across the tunnel oxide. Moreover, the higher Vt required in multi-level cells require higher Vread. This causes read disturbance to unselected memory cells in the selected NAND cell string during read operations (i.e. soft-program by higher Vread to unselected memory cells).
[0025] In addition, the higher voltage requirements for read and write operations in multi-level flash memory does not scale with device dimension scaling as the electric field across all transistors including memory cells cannot be reduced.
[0026] Therefore, the life of a multi-level Flash memory cell is relatively short, typically only 10,000 cycles. This is significantly shorter than the 100,000 cycle limit for single bit per cell Flash memory devices.
Summary of the Invention
[0027] It is an object of the present invention to obviate or mitigate at least one disadvantage of previous multi-level Flash memory cells devices. For example, present invention improves endurance of Flash memory cells by distributing programming threshold voltages in erase and program voltage domains.
[0028] In a first aspect, the present invention provides a Flash memory device. The Flash memory device includes a memory array having memory cells arranged in rows and columns and row control logic. The memory array has memory cells arranged in rows and columns, where each memory cell is erasable to have an erase threshold voltage in an erase voltage domain and programmable to have a program threshold voltage in the erase voltage domain. The row control logic selectively drive a wordline connected to a gate terminal of a memory cell with one of a positive voltage and a negative voltage during program verify and read operations. In an embodiment of the present aspect, the Flash memory device further includes a positive voltage generator and a negative voltage generator, where the positive voltage generator provides the positive voltage to the row control logic, and the negative voltage generator provides the negative voltage to the row control logic.
[0029] According to embodiments of the present aspect, each memory cell is programmable to have the program threshold voltage in a program voltage domain, and the erase voltage domain includes threshold voltages that are negative while the program voltage domain includes threshold voltages that are positive. In the present embodiment, each memory cell is programmable to store two bits of data corresponding to first, second, third and fourth threshold voltages, where the first threshold voltage and the second threshold voltage are in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage are in the program voltage domain. The first threshold voltage can correspond to the erase threshold voltage.
[0030] In a second aspect, the present invention provides a method for verifying a threshold voltage of erased memory cells configured in a NAND string. The method includes precharging a bitline coupled to the NAND string to a first voltage level; applying a reference voltage to all wordlines connected to the erased memory cells of the NAND string for coupling the bitline to a second voltage level; and, sensing a voltage level change in the bitline.
[0031] According to an embodiment of the present invention the first voltage level is a positive voltage, and the erased memory cells have an erased threshold voltage in an erase voltage domain while the reference voltage is in the erase voltage domain. The reference voltage can be greater than the erased threshold voltage and less than a programmed threshold voltage in the erase voltage domain. In a further aspect of the present embodiment, the memory cells are erased if no voltage level change is sensed in the bitline, and the steps of precharging, applying a reference voltage and sensing the memory cells are erased.
[0032] In a third aspect, the present invention provides a method for programming a Flash memory cell initially erased to have a first threshold voltage in an erase voltage domain. The method includes changing the first threshold voltage of the Flash memory cell to a second threshold voltage, the second threshold voltage being in the erase voltage domain. The step of changing can include biasing a bitline connected to the Flash memory cell to programming voltage level followed by driving a wordline connected to the Flash memory cell with a predetermined number of pulses, each pulse having a predetermined step size.
[0033] According to an embodiment of the present aspect, the second threshold voltage is verified and the step of changing is repeated if the Flash memory cell does not have the second threshold voltage. The method of verifying includes precharging a bitline connected to the Flash memory cell to a first voltage level, driving a wordline connected to the Flash memory cell with a reference voltage in the erase voltage domain, and sensing a voltage level change in the bitline. The reference voltage can be greater than the first threshold voltage and less than the second threshold voltage. In a further embodiment, the Flash memory cell and a plurality of Flash memory cells form a NAND string, and the step of driving further includes driving wordlines connected to the plurality of Flash memory cells with a pass voltage.
[0034] In a fourth aspect, the present invention provides a method for reading a Flash memory cell programmable to have an erase voltage domain threshold voltage or a programming domain threshold voltage. The method includes determining one of an erase threshold voltage and the erase voltage domain threshold voltage by applying an erase voltage domain reference voltage to a gate terminal of the Flash memory cell and sensing a bitline voltage connected to the Flash memory cell; storing a logical state of the Flash memory cell; determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage by applying another reference voltage to the gate terminal and sensing the bitline voltage connected to the Flash memory cell; and, updating the logical state.
[0035] In a fifth aspect, the present invention provides a Flash memory device. The Flash memory device includes a memory array having memory cells, each memory cell erasable to have a threshold voltage in an erase voltage domain, and programmable to have at least one threshold voltage level in the erase voltage domain and at least another threshold voltage in a program voltage domain.
[0036] According to embodiments of the present aspect, the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive, and each memory cell is programmable to store a plurality of bits of data corresponding to first, second, third and fourth threshold voltages. The first threshold voltage and the second threshold voltage can be in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage can be in the program voltage domain. In an alternate embodiment, the erase voltage domain includes threshold voltages that are positive and the program voltage domain includes threshold voltages that are negative.
[0037] In another embodiment of the present aspect, the Flash memory device further includes row control logic for selectively driving a wordline with a negative voltage and positive voltage in response to a row address. The Flash memory device can further include a first voltage generator for providing the positive voltage and a second voltage generator for providing the negative voltage. The row control logic includes a row decoder for receiving the positive voltage and the negative voltage, the row decoder providing row signals in response to the row address, and a wordline driver for passing the row signals in response to an enable signal. In yet another embodiment, the row control logic includes a block decoder for providing the enable signal in response to a block address, the enable signal having one of the positive voltage and the negative voltage.
[0038] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
Brief Description of the Drawings
[0039] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
[0040] FIG. 1 is a block diagram of a typical Flash memory device;
[0041] FIG. 2 is a circuit schematic of a NAND cell string;
[0042] FIG. 3 is a cross-sectional schematic of a typical Flash memory cell;
[0043] FIG. 4 is a cross-sectional schematic of a nitride ROM cell having charge traps;
[0044] FIG. 5 is a threshold voltage (Vt) distribution graph for a multi-level Flash memory cell of the prior art;
[0045] FIG. 6 is a graph illustrating the relationship between the number of program pulses applied to a wordline for programming a threshold voltage versus the size of each pulse;
[0046] FIG. 7 is an exemplary embodiment of the invention showing a threshold voltage distribution for a Flash memory cell capable of storing 2 bits of data;
[0047] FIG. 8 is an alternate embodiment of the invention showing a threshold voltage distribution graph for a Flash memory cell capable of storing 3 bits of data;
[0048] FIG. 9 is a block diagram of the row circuits for a multi-level Flash memory device, according to an embodiment of the present invention;
[0049] FIG. 10 is a circuit schematic of the block decoder and the wordline driver circuit shown in FIG. 9 ;
[0050] FIG. 11 is a circuit schematic of the row decoder circuit shown in FIG. 9 ;
[0051] FIG. 12 is a flow chart showing a method for performing an erase-verify operation;
[0052] FIG. 13 is a flow chart showing a method for programming multiple threshold voltages, according to an embodiment of the present invention;
[0053] FIG. 14 is a flow chart showing a program verify method, according to an embodiment of the present invention; and,
[0054] FIG. 15 is a flow chart showing a method for reading data, according to an embodiment of the present invention.
Detailed Description
[0055] Generally, aspects of the present invention provide a threshold voltage distribution scheme for multi-level Flash cells with optimal Vt window and maximum Vt distance, while at the same time maintaining Vread at lower levels. In one embodiment, this is accomplished by programming at least one cell state in the erase voltage domain (for example, with a negative Vt value).
[0056] FIG. 7 is an exemplary embodiment of the invention. FIG. 7 shows a threshold voltage distribution for a multi-level Flash memory cell capable of storing 2 bits of data. In the present embodiment, there is one program state (cell state 1, corresponding to data “10”) lying in the erased voltage domain with erased state (cell state 0, corresponding to data “11”). Therefore, there are two cell states lying in the erased voltage domain and two cell states (cell state 2, corresponding to data “01” and cell state 3, corresponding to data “00”) in the program voltage domain. By programming this state in the erased voltage domain, different advantages are obtained. First, endurance is immediately increased relative to the prior art devices having the same Vt window, since the Vt distance between states is increased. Second, endurance is further increased by minimizing the Vt window, at the expense of programming speed. Third, the Vt distance and Vt window requirements are relaxed to provide improved programming performance over prior art devices, but having the same endurance. In addition, the Vread voltage for unselected cells can be lowered, for example, from a typical value of 5.5 volts to 4.8 volts. FIG. 7 shows example values VL and VU values, but any VL and VU can be set for each state.
[0057] In conventional approaches, such as the threshold voltage scheme described with reference to FIG. 5 , the cell state 0 has a negative Vt (erase voltage domain) while the remaining three cell states (states 1, 2, and 3) have positive Vt's (program voltage domain). In the threshold voltage scheme of the present embodiment as illustrated in FIG. 7 , cell states 0 and 1 have negative Vt's, while cell states 2 and 3 have positive Vt's. The number of cell states in the erase voltage domain and the program voltage domain are equal and hence this scheme is referred to as a “balanced” Vt distribution scheme.
[0058] This balanced cell Vt distribution scheme provides at least the following advantages: Due to the separation of the cell states, the Vt window of each state can be widened, thus improving the program speed. The cell Vt distance is maximized, which will greatly improve data retention and endurance. This scheme further lowers the program voltage Vpgm and program-pass voltage Vpass, allowing for scaling with device geometry scaling. It also enables lowering of the Vread voltage, which, as a result, provides higher immunity to read disturbance typically encountered by conventional high Vread values. While FIG. 7 is an example Vt distribution for a two bit per cell device, cells storing any number of bits will benefit from the embodiments of the present invention.
[0059] FIG. 8 is an alternate embodiment of the invention. FIG. 8 shows a threshold voltage distribution graph for a multi-level Flash memory cell capable of storing 3 bits of information (i.e. eight different states). It should be noted that in the embodiment of FIG. 8 , exactly half of the eight possible states lie in the erase voltage domain while the other half lies in the program voltage domain. In further alternate embodiments, there can be five states in the erase voltage domain or three states in the erase voltage domain, or other combinations having at least two states in the erase voltage domain.
[0060] As previously discussed for FIG. 6 , ISPP is used for programming desired threshold voltages corresponding to the different states of the multi-level Flash memory cells. As all memory cells are programmed to a desired threshold voltage from the erased state, ISPP gradually shifts the negative threshold voltage of an erased Flash memory cell using increasingly larger voltage pulses applied to its control gate. The incremental step size and number of pulses determines the final threshold voltage of the programmed Flash memory cell. According to an embodiment of the present invention, a programmed state in the erase voltage domain is achieved by setting the number of pulses and step size of the pulses such that the desired negative threshold voltage is obtained. In the example of FIG. 6 , a −2V threshold voltage is obtained by using between 2 and 3 pulses, depending on the selected pulse step size. Once the erase domain program states have been programmed, the remaining program domain states are programmed according to known techniques. It is noted that the step size for programming the erase domain states can be small without impacting programming speed since the threshold voltage shift from the erase state is relatively small.
[0061] A part of any programming operation is the program verify operation, which is used to check that the data has been properly programmed. For example, the desired threshold voltage may not have been set during a program operation. Therefore, the memory cell(s) is subjected to reprogramming until the program verify clears the memory cell, or until it is determined that the cell is defective. Once the program verify operation clears the memory cells, the data can be read. According to an embodiment of the present invention, program verify and read operations are executed with both positive and negative voltages.
[0062] Table 1 shows bias conditions of the selected wordline and unselected wordlines to distinguish each cell state during read, verify & control programmed cell Vt during program in a conventional multi-level flash memory using the cell Vt distribution scheme of FIG. 5 . Table 2 shows bias conditions of the selected wordline and unselected wordlines during program verify and read in a multi-level flash memory programmable to have at least two states in the erase voltage domain, according to an aspect of the present invention.
[0063]
| TABLE 1 | ||||
|---|---|---|---|---|
| Program Verify | Read | |||
| Selected | Unselected | Selected | Unselected | |
| Wordline | Wordlines | Wordline | Wordlines | |
Cell State 0  1 | 0.3 V (Vref_pv1) | 5.5 V (Vread) | 0 V (Vref_rd1) | 5.5 V (Vread) |
| Cell State 1 2 | 1.5 V (Vref_pv2) | 5.5 V (Vread) | 1.1 V (Vref_rd2) | 5.5 V (Vread) |
| Cell State 2 3 | 2.8 V (Vref_pv3) | 5.5 V (Vread) | 2.3 V (Vref_rd3) | 5.5 V (Vread) |
[0064] Table 2 shows exemplary bias conditions for the program verify and read operations used for a multi-level Flash cell programmable to have at least two states in the erase voltage domain. As illustrated in Table 2, the negative voltages are applied to the selected wordline during the read and program verify operations for cells having negative cell Vt (i.e. cell state 0 and cell state 1). It should be noted that the voltage values in Table 2 are for illustration purpose only. In other words, voltage values in Table 2 can be varied according to process technology and cell characteristics.
[0065]
| TABLE 2 | ||||
|---|---|---|---|---|
| Program Verify | Read | |||
| Selected | Unselected | Selected | Unselected | |
| Wordline | Wordlines | Wordline | Wordlines | |
| Cell State 0 1 | −1.1 V (Vref_pv1) | 4.8 V (Vread) | −1.5 V (Vref_rd1) | 4.8 V (Vread) |
| Cell State 1 2 | 0.5 V (Vref_pv2) | 4.8 V (Vread) | 0 V (Vref_rd2) | 4.8 V (Vread) |
| Cell State 2 3 | 2.1 V (Vref_pv3) | 4.8 V (Vread) | 1.5 V (Vref_rd3) | 4.8 V (Vread) |
[0066] Due to shift in the Vt of at least one programmed cell state to the erase voltage domain, the program verify voltage and read voltage applied to the selected wordlines are different from conventional program verify and read operations, as shown in Table 2. Typically, all program verify voltage and read voltage are implemented with positive voltage values. However, the threshold voltage distribution scheme for multi-level Flash cells described herein utilizes both positive and negative voltages for program verify and read operations. This results in changes to the implementation for the wordline circuits as described below.
[0067] FIG. 9 is a block diagram of an exemplary row control logic for a multi-level Flash memory device according to an embodiment of the present invention. The row control logic 100 includes a block decoder 102, a row decoder circuit 108 and a wordline driver circuit 110. The device having row control logic 100 has a high voltage generator 104 and a negative voltage generator 106, which may be used by other circuits that are not shown in FIG. 9 . There is one block decoder 102 per memory block, which receives a block address BA, for enabling the wordline drivers. The row decoder 108 is commonly shared among all memory blocks, which receives a row address RA_b, as well as other signals which are not shown, for generating the source select signal SS, wordline signals S[0:n], and the ground select signal GS, generically referred to as row signals. Since at least one of the programmed states will be in the erase voltage domain (with a negative threshold voltage for example), the block decoder 102 and the row decoder circuit 108 will receive one or more negative voltages for application to a selected wordline signal. In response to a valid block address BA and row decoder signals, signals SSL, GSL and WL0-WLn are set to their required voltage levels during program, program verify and read operations. Example voltages are shown in Table 2 for program verify and read operations.
[0068] FIG. 10 is a circuit schematic showing circuit details of the block decoder 102 and wordline driver circuit 110 of FIG. 9 . Block decoder 102 is associated with one memory block, and includes a cross coupled inverter latch circuit and level shifter circuit. The latch circuit includes cross-coupled inverters 200 and 202, an n-channel reset transistor 204, and n-channel enable transistors 206 and 208. The latch circuit is enabled, or set, when latch enable signal LTCH_EN and a block address BA are at the high logic level. The latch circuit of inverters 200 and 202 is reset when signal RST_BD is at the high logic level. The level shifter circuit includes a pair of cross-coupled p-channel transistors 210 and 212, each being connected to respective n-channel steering transistors 214 and 216. The shared terminals of transistors 210 and 212 receives a high voltage Vh while the shared terminals of transistors 214 and 216 receives a negative voltage Vn. Node Vh is connected to the positive voltage generator 104 while node Vn is connected to the negative voltage generator 106. Steering transistors 214 and 216 have gate terminals connected to the output of inverter 200 and inverter 218, the input of which is connected to the gate of transistor 214. It is noted that the high voltage supply provided to inverter 200 is lower than Vh while the low voltage supply provided to inverter 202 is higher than Vn. The output of the level shifter circuit (an enabling signal) BD_out drives the gate terminals of all the n-channel pass transistors 220 of wordline drivers 110. The substrate terminal of all the pass transistors 220 are connected to Vn. Each pass transistor can selectively pass the source select (SS), wordline (S0-Sn) and ground select (GS) signals to the memory array. Placeholder “n” can be any non-zero integer number, typically corresponding to the maximum number of cells in the Flash cell string. The general operation of the block decoder circuit is now described.
[0069] In a read operation for example, one memory block is selected while other blocks remain unselected. In otherwords, one memory block is enabled while remaining memory blocks are disabled. To enable a memory block, LTCH_EN and BA will be at the high logic level, thereby setting the level shifter circuit to output high voltage Vh. Therefore, all the pass transistors 220 of wordline driver circuit 110 are turned on. Unselected wordlines (unselected Si) will be set to a Vread voltage while the selected wordline (selected Si) will be set to the desired voltage. The desired voltage can be −1.5V if the present read operation is intended to distinguish between cell state 0 and cell state 1, for example. Disabled memory blocks will have their corresponding block decoder circuit output set to output low voltage Vn (−1.5V for example). Therefore, all the pass transistors 220 in the unselected memory blocks will be turned off even though one of the Si signals may be at Vn of −1.5V for example. Table 3 illustrates example Vh and Vn voltages for read, program, program verify, erase and erase verify operations.
[0070]
| TABLE 3 | |||
|---|---|---|---|
| Vh | Vn | ||
| Read | ~6.5 V | 0 V/−1.5 V (Vref_rd1) | |
| Program | ~18 V | 0 V | |
| Program Verify | ~6.5 V | 0 V/−1.1 V (Vref_pv1) | |
| Erase | Vdd | 0 V | |
| Erase Verify | ~6.5 V | 0 V | |
[0071] FIG. 11 is a circuit schematic showing one row decoder circuit of row decoder 108 of FIG. 9 . The presently shown schematic of FIG. 11 is a functional representation only, as there can be different specific circuit implementations that are possible. In prior art row decoder circuits, only voltages in the program voltage domain are provided. According to an embodiment of the present invention, both program voltage domain (ie. positive voltages) and erase voltage domain (ie. negative voltages) are provided by the presently shown row decoder circuit. FIG. 11 shows one circuit for generating one row signal Si where i can be an integer value between 0 and n, but the circuits for generating signals SS and GS are similarly configured. The row decoder circuit includes a multiplexor 300 for receiving all the voltages that are used during program, program verify, read, erase and erase verify operations. This includes for example, a program verify voltage Vver, a read voltage Vread, a pass voltage Vpass, and a programming voltage Vpgm.
[0072] Multiplexor 300 further receives the different reference voltages used for read and program verify operations, such as Vref_rd1, Vref_rd2 and Vref_rd3 for the 2 bit/cell configuration. In the present embodiment, Vref_rd1 is a negative erase domain voltage while Vref_rd2 and Vref_rd3 are positive program domain voltages. Any number of voltages can be provided to multiplexor 300, and then selectively passed to node Sn. Voltage selection signal Vselect is used to pass any one of the voltages. Those skilled in the art will understand that Vselect will be a multi-bit signal, the number depending on the number of input ports that multiplexor 300 is configured to have. The row decoder circuit includes an n-channel disabling transistor 302 connected between node Sn and ground for disabling the circuit when not in use, or during a power down mode of operation, for example.
[0073] In general operation, signal Sn is enabled in response to a selected address for enabling a particular wordline when address RA_b is at the low logic level. RA_b can be a decoded row address or a predecoded row address. Depending on the operation being performed, Vselect will be set to pass one of the voltages received by multiplexor 300 to the Sn node. While not shown, the voltage generators 104 and 106 of FIG. 9 are controlled to provide the appropriate voltage levels depending on the operation being performed. Table 4 illustrates example voltages applied to the wordlines and by the row decoder circuit during a read operation for selected and unselected wordlines Si, where i is an integer value between 0 and n. Table 5 illustrates example voltages applied to the wordlines and by the row decoder circuit during a program verify operation for selected and unselected wordlines Si, where i is an integer value between 0 and n.
[0074]
| TABLE 4 | |||
|---|---|---|---|
| Cell | Cell | Cell | |
| Signal | State 1 2 | State 2 3 | State 3 4 |
| Unselected | −1.5 V | −1.5 V or 0 V | −1.5 V or 0 V |
| BD_out | |||
| (Unselected | |||
| Block) | |||
| Selected | 6.5 V | 6.5 V | 6.5 V |
| BD_out | |||
| (Selected | |||
| Block) | |||
| Vh | 6.5 V | 6.5 V | 6.5 V |
| Vn | −1.5 V | −1.5 V or 0 V | −1.5 V or 0 V |
| SS | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
| Selected Si | −1.5 V (Vref_rd1) | 0 V | 1.5 V |
| (Vref_rd2) | (Vref_rd3) | ||
| Unselected | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
| Si | |||
| GS | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
[0075]
| TABLE 5 | |||
|---|---|---|---|
| Signal | Cell State 1 2 | Cell State 2 3 | Cell State 3 4 |
| Unselected | −1.1 V | −1.1 V or 0 V | −1.1 V or 0 V |
| BD_out | |||
| (Unselected | |||
| Block) | |||
| Selected | 6.5 V | 6.5 V | 6.5 V |
| BD_out | |||
| (Selected | |||
| Block) | |||
| Vh | 6.5 V | 6.5 V | 6.5 V |
| Vn | −1.1 V | 0.5 V or 0 V | 2.1 V or 0 V |
| SS | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
| Selected Si | −1.1 V (Vref_pv1) | 0.5 V | 2.1 V |
| (Vref_pv2) | (Vref_pv3) | ||
| Unselected | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
| Si | |||
| GS | 4.8 V (Vread) | 4.8 V (Vread) | 4.8 V (Vread) |
[0076] In the prior art programming schemes, programmed cell states are confined to the program voltage domain, ie. having positive threshold voltages. In the presently disclosed balanced threshold programming scheme, at least one programmed cell state resides in the erase voltage domain. Therefore, an erase verify algorithm is used for ensuring that all the erased memory cells have the proper erase threshold voltage level. FIG. 12 is a flow chart showing a method for performing an erase verify operation according to an embodiment of the present invention. Since a programmed state will be in the erase voltage domain, the method of FIG. 12 ensures that all the memory cells are sufficiently erased such that their threshold voltages do not lie within the designated negative threshold voltage range for a programmed state.
[0077] The method of FIG. 12 commences at step 400 by erasing a selected block of the memory array. After all the memory cells have been erased, all the bitlines of the selected memory block are precharged to a first voltage level such as VDD at step 402. A reference voltage is then applied to all the wordlines of the memory cells at step 404. It is presumed that the memory cells are configured as NAND cell strings, such as the ones previously shown in FIG. 2 . The reference voltage is selected to be greater than the highest possible erase threshold voltage for the erase state, and lower than the lowest possible program threshold voltage for the adjacent program state. Generally, the reference voltage in the erase domain voltage, and in the example where the erase domain is below 0V, the reference voltage is a negative voltage level. With reference to the example threshold voltage distribution of FIG. 7 for example, if all the memory cells have been properly erased, then their threshold voltage should be between −2.9 and −2.1 volts. The reference voltage applied to the wordlines will be about −1.5 volts. If all the memory cells have been properly erased, then the −1.5 volt level on wordlines 0 to 31 is sufficient to turn on the transistors and discharge the bitline to CSL or ground. However, if any one of the cells in the NAND cell string has a threshold voltage higher than −1.5 volts, then the bitline will not discharge to ground. Therefore, the bitline voltage is sensed at step 406. At step 408, a determination is made to see if the bitline voltage is equal or not to the original pre-charge voltage. If the bitline voltage is the same, then the method loops back to step 400 to re-erase the cells and repeat the verification process. Otherwise, all the memory cells have been properly erased and the erase verify method ends at step 410.
[0078] After all the memory cells have been verified as being successfully erased, programming of data to the memory cells can proceed. FIG. 13 is a flow chart illustrating a method of programming one programmed state in the erase voltage domain, according to an embodiment of the present invention. The method starts at step 500 by setting the ISPP parameters such as number of program pulses and step size for each pulse, for the state to be programmed in the erase voltage domain. At step 502 the erase voltage domain threshold voltage is programmed to the selected Flash memory cells. As previously mentioned, the erase threshold voltage of a memory cell is effectively shifted to the desired erase domain threshold voltage level by using a predetermined number of program pulses and step sizes in accordance with the ISPP scheme. At step 504 a program verify operation is executed to ensure that the programmed state has been properly programmed. More specifically, the program verify will use the appropriate erase voltage domain reference voltage to verify the programmed state. In the present example, the program verify reference voltage will be a negative voltage level. Further details of the program verify operation are shown later in FIG. 14 .
[0079] A determination is made at step 506 to see if at least one memory cell fails program verification. If at least one failure is determined, then the method loops back to step 502 for reprogramming of the at least one memory cell. Otherwise, all the memory cells have been deemed to have been successfully programmed, and the method proceeds to step 508 where subsequent programming sequences are executed for the remaining states. The remaining states can include further erase voltage domain states and/or program voltage domain states. Further erase voltage domain states are programmed according to the same sequence shown in steps 500 to 506, but with different ISPP parameters and program verify reference voltages.
[0080] FIG. 14 is a flow chart of a method for performing a program verify operation after a state has been programmed in the erase voltage domain. The method starts at step 600 by precharging the bitlines to a first voltage level, such as positive voltage level for example. At step 602 the selected wordline corresponding to the page that was programmed is driven to an erase voltage domain reference voltage, and unselected wordlines are driven to a read voltage at step 604. The erase voltage domain reference voltage is selected to be lower than the desired threshold voltage range of the currently programmed state, but higher than the adjacent state having a lower threshold voltage range. In the example of FIG. 7 , if the programmed state being verified is cell state 1, then the erase voltage domain reference voltage is selected to be higher than Vref1-rd. The read voltage is typically a program voltage domain voltage sufficient to turn on a memory cell having the highest programmed threshold voltage, such as Vread in the example of FIG. 7 . The bitline is sensed at step 606, and a determination is made at step 608 to see if the bitline voltage has changed, ie. been discharged through the NAND cell string. If there is a change to the bitline voltage, then the threshold voltage of the currently programmed state is too low and conducts current. Thus the memory cell(s) are deemed to have failed, and the method proceeds to step 610 to repeat programming for the failed cell(s). Otherwise, the program verify method ends at step 612 as all the cells have passed verification for the currently programmed state.
[0081] Once data has been programmed and verified, it can be read from the memory array. In one multi-level sensing scheme, latches for the two bits representing one of four possible logic states are set to default states, such as 1,1 for example. Reading is accomplished by iteratively reading out the cell by applying Vref1-rd, Vref2-rd and Vref3-rd in each iteration. If the threshold voltage of the selected memory cell is determined to be less than the applied reference voltage for that iteration, then neither bit state is changed, or toggled. If the threshold voltage of the selected memory cell is determined to be greater than the applied reference voltage for that iteration, then one bit state is changed, or toggled. The particular bit to toggle depends on the specific read iteration being executed. This ensures that the bit states for the lowest threshold voltage (ie. erased state) will remain unchanged for each subsequent iteration. Hence, for a two bit multi-level memory cell, three read iterations are required for determining the two bit state of the memory cell.
[0082] FIG. 15 is a flow chart of a method for reading one cell state in the erase voltage domain. The method starts at step 700 by precharging the bitlines to a first voltage level, such as a positive voltage level for example. The selected wordline is driven to an erase voltage domain reference voltage at step 702, while the remaining unselected wordlines are driven to a read voltage at step 704. In the presently described example, the erase voltage domain reference voltage is selected to be lower than the desired threshold voltage range of the currently programmed state, but higher than the adjacent state having a lower threshold voltage range. In the example of FIG. 8 , if the programmed state being read is cell state 1, then the erase voltage domain reference voltage is selected to be Vref1-rd. The read voltage is typically a program voltage domain voltage sufficient to turn on a memory cell having the highest programmed threshold voltage, such as Vread in the example of FIG. 8 . The bitline is sensed at step 706 to determine if the cell threshold voltage is either greater than or less than Vref1-rd, and the states of the bits are updated. At step 708, the remaining states are sensed to complete the read operation for the memory cell. The remaining states can be further erase voltage domain states and program voltage domain states. In otherwords, the read process will repeat with the updated parameters corresponding to the state being sensed, ie, setting the reference voltage to Vref2-rd at step 700. Once all the possible states stored in the Flash memory cell are sensed, the multi-bit logic states corresponding to the threshold level stored in the memory cell are output through read path circuits at step 710.
[0083] Therefore, by programming at least one state in the erase voltage domain as previously described by the embodiments of the present invention, reliability or endurance of a multi-level Flash memory device is maximized relative to prior art multi-level Flash memory devices because the Vt window for each cell state is minimized while the Vt distance between cell states is maximized. Alternately, the Vt window for each cell state can be relaxed, thereby increasing ISPP programming speed relative to prior art multi-level Flash memory devices as the step sizes are increased and number of steps are decreased. Those skilled in the art will understand that optimization of the Vt window and Vt distance will be tailored for the specific application of the multi-level Flash memory device.
[0084] The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.
[0085] For example, the erase voltage domain is described in the example embodiments as being voltages less than 0V while the program voltage domain include voltages greater than 0V. In an alternate embodiment, the threshold voltage distribution scheme can be inverted, such that the erase voltage domain includes voltages greater than 0V while the program voltage domain includes voltages less than 0V.
[0086] In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.
[0087] Embodiments of the invention can be represented as a software product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the invention. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described invention can also be stored on the machine-readable medium. Software running from the machine-readable medium can interface with circuitry to perform the described tasks.
[0088] The above-described embodiments of the invention are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A Flash memory device comprising:
a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable to have a program threshold voltage in the erase voltage domain and a program voltage domain;
each memory cell programmable to store two bits of data corresponding to first, second, third, and fourth threshold voltages with the first threshold voltage and the second threshold voltage in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage in the program voltage domain; and,
row control logic for selectively driving a wordline connected to a gate terminal of a memory cell with one of a positive voltage and a negative voltage during program verify and read operations.
2. The Flash memory device of claim 1, further including a positive voltage generator for providing a positive voltage, and a negative voltage generator for providing a negative voltage.
3. The Flash memory device of claim 1, wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.
4. The Flash memory device of claim 1, wherein the first threshold voltage corresponds to the erase threshold voltage.
5. A method for programming a Flash memory cell initially erased to have a first threshold voltage in an erase voltage domain, the method comprising:
changing the first threshold voltage of the Flash memory cell to a second threshold voltage, the second threshold voltage being in the erase voltage domain;
precharging a bitline connected to the Flash memory cell to a first voltage level,
driving a wordline connected to the Flash memory cell with a reference voltage in the erase voltage domain, and
sensing a voltage level change in the bitline; and
verifying the second threshold voltage and repeating the step of changing if the Flash memory cell does not have the second threshold voltage.
6. The method of claim 5, wherein the step of changing includes:
biasing a bitline connected to the Flash memory cell to a programming voltage level; and
driving a wordline connected to the Flash memory cell with a predetermined number of pulses, each pulse having a predetermined step size.
7. The method of claim 5, wherein the reference voltage is greater than the first threshold voltage and less than the second threshold voltage.
8. The method of claim 6, wherein the Flash memory cell and a plurality of Flash memory cells form a NAND string, and the step of driving further includes driving wordlines connected to the plurality of Flash memory cells with a pass voltage.
9. A method for reading a Flash memory cell programmable to have an erase voltage domain threshold voltage or a programming domain threshold voltage, the method comprising:
determining one of an erase threshold voltage and the erase voltage domain threshold voltage by applying an erase voltage domain reference voltage to a gate terminal of the Flash memory cell and sensing a bitline voltage connected to the Flash memory cell;
storing a logical state of the Flash memory cell in response to the step of determining one of an erase threshold voltage and the erase voltage domain threshold voltage;
determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage by applying another reference voltage to the gate terminal and sensing the bitline voltage connected to the Flash memory cell; and
updating the logical state in response to the step of determining one of the erase voltage domain threshold voltage and the programming domain threshold voltage.
10. A Flash memory device comprising:
a memory array having memory cells, each memory cell erasable to have a threshold voltage in an erase voltage domain, and programmable to have at least one threshold voltage level in the erase voltage domain and at least another threshold voltage in a program voltage domain; and
each memory cell programmable to store a plurality of bits of data corresponding to first, second, third and fourth threshold voltages with the first threshold voltage and the second threshold voltage in the erase voltage domain, and the third threshold voltage and the fourth threshold voltage in the program voltage domain.
11. The Flash memory device of claim 10, wherein the erase voltage domain includes threshold voltages that are negative and the program voltage domain includes threshold voltages that are positive.
12. The Flash memory device of claim 10, wherein the erase voltage domain includes threshold voltages that are positive and the program voltage domain includes threshold voltages that are negative.
13. The Flash memory device of claim 10, further including row control logic for selectively driving a wordline with a negative voltage and positive voltage in response to a row address.
14. The Flash memory device of claim 13, further including a first voltage generator for providing the positive voltage and a second voltage generator for providing the negative voltage.
15. The Flash memory device of claim 14, wherein the row control logic further comprises:
a row decoder for receiving the positive voltage and the negative voltage, the row decoder providing row signals in response to the row address, and
a wordline driver for passing the row signals in response to an enable signal.
16. The Flash memory device of claim 15, wherein the row control logic further comprises:
a block decoder for providing the enable signal in response to a block address, the enable signal having one of the positive voltage and the negative voltage.
Patent Citations (43)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5109361(A) | 1992-04-01 | Yim et al. | Applicant |
| US5299162(A) | 1994-03-01 | Kim et al. | Applicant |
| US5396459(A) | 1995-03-01 | Arakawa | Examiner |
| US5473563(A) | 1995-12-01 | Suh et al. | Applicant |
| US5541879(A) | 1996-07-01 | Suh et al. | Applicant |
| US5546341(A) | 1996-08-01 | Suh et al. | Applicant |
| US5671178(A) | 1997-09-01 | Park et al. | Applicant |
| US5732018(A) | 1998-03-01 | Choi et al. | Applicant |
| US5835935(A) | 1998-11-01 | Estakhri et al. | Applicant |
| US5937425(A) | 1999-08-01 | Ban | Applicant |
| US5995417(A) | 1999-11-01 | Chen et al. | Applicant |
| US6111787(A) | 2000-08-01 | Akaogi et al. | Applicant |
| US6118705(A) | 2000-09-01 | Gupta et al. | Applicant |
| US6128224(A) | 2000-10-01 | Morton et al. | Examiner |
| US6208556(B1) | 2001-03-01 | Akaogi et al. | Applicant |
| US6256254(B1) | 2001-07-01 | Kwak et al. | Applicant |
| US6278636(B1) | 2001-08-01 | Lee | Applicant |
| US6359810(B1) | 2002-03-01 | Gupta et al. | Applicant |
| US6456528(B1) | 2002-09-01 | Chen | Applicant |
| US6522580(B2) | 2003-02-01 | Chen et al. | Examiner |
| US6552580(B2) | 2003-04-01 | Nilson et al. | Examiner |
| US6594183(B1) | 2003-07-01 | Lofgren et al. | Applicant |
| US6671204(B2) | 2003-12-01 | Im | Applicant |
| US6717857(B2) | 2004-04-01 | Byeon et al. | Applicant |
| US6732221(B2) | 2004-05-01 | Ban | Applicant |
| US6763424(B2) | 2004-07-01 | Conley | Applicant |
| US6804148(B2) | 2004-10-01 | Bedarida et al. | Applicant |
| US6807103(B2) | 2004-10-01 | Cavaleri et al. | Applicant |
| US6885583(B2) | 2005-04-01 | Tanaka | Applicant |
| US6963509(B1) | 2005-11-01 | Ju | Applicant |
| US7016229(B2) | 2006-03-01 | Kim | Applicant |
| US7042770(B2) | 2006-05-01 | Lee et al. | Applicant |
| US7046554(B2) | 2006-05-01 | Lee | Applicant |
| US7061813(B2) | 2006-06-01 | Lee | Applicant |
| US7082056(B2) | 2006-07-01 | Chen et al. | Applicant |
| US7099213(B2) | 2006-08-01 | Ju | Applicant |
| US7149130(B2) | 2006-12-01 | Lee | Applicant |
| US2004/0080979(A1) | 2004-04-01 | Park | Applicant |
| US2004/0179403(A1) | 2004-09-01 | Noguchi et al. | Examiner |
| US2005/0157558(A1) | 2005-07-01 | Noguchi et al. | Examiner |
| US2005/0232008(A1) | 2005-10-01 | Shukuri et al. | Applicant |
| US2006/0133155(A1) | 2006-06-01 | Fujita et al. | Applicant |
| US2008/0062762(A1) | 2008-03-01 | Doyle | Examiner |
Non-Patent Literature (22)
- Samsung Electronics Co., Ltd., “Samsung Announces First 40-nanometer Device—32 Gb NAND Flash with Revolutionary Charge Trap Technology”, World Press Release, Sep. 11, 2006, pp. 1-2.Applicant
- Aritome, et al., “A Reliable Bi-Polarity Write/Erase Technology In Flash Eeproms”, Int'l. Electron Devices Meeting, 1990, Technical Digest, Dec. 9-12, 1990; pp. 111-114.Applicant
- Shirota, et al., “A 2.3 um2 Memory Cell Structure For 16Mb Nand Eeproms”, International Electron Device Meeting Tech. Dig.,(1990), pp. 103-106.Applicant
- Jung, et al., “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications”, 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1996, pp. 32-33.Applicant
- Hara, et al., “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology”, ISSCC Session 2 Non-Volatile Memory 2.1, IEEE International Solid-State Circuits Conference, Feb. 7, 2005, pp. 44, 45 and 584.Applicant
- Byeon, et al., “An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology”, ISSCC Session 2 Non-Volatile Memory 2.2, IEEE International Solid-State Circuits Conference, Feb. 7, 2005, pp. 46-47.Applicant
- Suh, et al., “A 3.3 V 32 Mb NAND Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1156.Applicant
- Takeuchi, et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug. 1998, pp. 1228-1238.Applicant
- Jung, et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1575-1583.Applicant
- Cho, et al., “A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High Performance 512-Mb Single-Level Modes”, IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp. 1700-1706.Applicant
- Lee, et al., “A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology”, 2004 IEEE International Solid-State Circuits Conference, Session 2, Feb. 16, 2004, pp. 52-513, vol. 1.Applicant
- Takeuchi, et al., “A 56nm CMOS 99mm2 8Gb Multi-Level NAND Flash Memory with 10MB/s Program Throughput”, 2006 IEEE International Solid-State Circuits Conference, Session 7, Feb. 6, 2004, pp. 507-516.Applicant
- Kirisawa, et al., A Nand Structural Cell With A New Programming Technology For Highly Reliable 5V-Only Flash Eeprom, 1990 IEEE Symposium on VLSI Tech., Jun. 4-7, 1990, pp. 129-130.Applicant
- Cho, et al., “A 3.3 V 1 Gb multi-level NAND flash memory with non-uniformthreshold voltage distribution”, Solid-State Circuits Conference, 2001, Digest of Technical Papers, ISSCC, 2001 IEEE International, Feb. 5, 2001, pp. 28-29.Applicant
- Kim, “Multilevel Flash Memory Cell with Balanced Cell Vth”, MOSAID Technologies Incorporated, Mar. 14, 2006, pp. 1-27.Applicant
- Momodomi, M. et al., “A 4 MB NAND EEPROM with Tight Programmed VT Distribution”, IEEE Journal of Solid-State Circuits, vol. 26, Issue 4, Apr. 1991, pp. 492-496.Applicant
- Kim, et al. “A 120-mm2 64 Mb NAND Flash Memory Archiving 180 ns/Byte Effective Program Speed,” IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1977, pp. 670-680.Applicant
- Imamiya, K. et al., “A 125-mm2 1-Gb NAND Flash Memory with 10-MByte/s Program Speed”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1493-1501.Applicant
- Samsung Electronics Co. Ltd, “256M×8 Bit / 128 M×16 Bit / 512M×8 Bit NAND Flash Memory”, K9K4G08U1M, May 6, 2005, pp. 1-41.Applicant
- Gal, et al., “Algorithms and data structures for flash memories”, ACM Computing Surveys (CSUR), vol. 37, No. 2, p. 138-163, Jun. 2005, Tel Aviv University.Applicant
- Lee J. et al., “A 90-nm CMOS 1.8-V 2Gb NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003. pp. 1934-1942.Applicant
- Toshiba, “2GBIT (256M×8 Bits) CMOS NAND E2PROM”, TH58NVG1S3AFT05, May 19, 2003, pp. 1-32.Applicant