Image processing apparatus and method

[0001] This application is a divisional of U.S. patent application Ser. No. 10/390,638, now U.S. Pat. No. 7,379,609, filed on Mar. 19, 2003, which claims priority from Korean Patent Application No. 2002-42603, filed on Jul. 19, 2002, and Korean Patent Application No. 2002-44991 filed on Jul. 30, 2002, the contents of all of which are herein incorporated by reference in their entirety.

[0002] 1. Field of the Invention

[0003] The present invention relates to an image processing apparatus and method and, more specifically, to an image processing apparatus and method for converting image data between a raster scan order and a block scan order.

[0004] 2. Description of the Related Art

[0005] JPEG (Joint Photographic Experts Group) is a compression standard for transmitting still image data such as photographs. JPEG is designed for compressing full-color or gray-scale images, and works well for photographs or art. While another format, GIF (Graphics Interchange Format) allows transmission of color images of 256 colors, JPEG is capable of processing color images in approximately 16 million colors and is more suited to high-resolution display devices. Another advantage of JPEG is that users can control the quality of an image and the size of an image file. For example, when a large-sized image file is compressed into a considerably smaller-sized file, the quality of images may be degraded. However, JPEG compression techniques are capable of compressing images reliably so that compressed images are not lower in quality.

[0006] Therefore, JPEG has been widely used for the compression of still image data in such devices as digital still cameras. As is popularly known, JPEG employs a discrete cosine transform (DCT) for compression of data. DCT processes data in a block format of, for example, 8*8 pixels. However, an image data processor of a digital still camera which precedes the DCT processing outputs image data in a raster format (i.e., in a raster scan order, which is from left to right and from top to bottom throughout the image data). FIG. 1A illustrates image data in a raster scan order as output by an image data processor of a digital still camera.

[0007] To use JPEG image data stored in a line buffer in a raster format (which is output from the image data processor of the camera as illustrated in FIG. 1A), this data should be read in a block format as shown in FIG. 1B before being supplied to a JPEG compressor. FIG. 1B illustrates image data in a block order format to be input to the JPEG compressor. The conversion from raster scan order to block scan order requires line memories that are capable of storing image data of at least 8 lines. Also, because the image data includes luminance component Y and chrominance components U and V, each color component requires a separate line memory.

[0008] FIG. 2 illustrates a conventional line memory system operating under the conventional VGA (Variable Graphics Array) standard for producing an 8*8 block for JPEG compression. An image data processor 10 generates the luminance component Y and chrominance components U and V of the image data in raster format (for example, a 4:2:2 raster format). The image data components Y, U, and V, which are generated from the image data processor 10, are stored in cell arrays of corresponding line memories 12, 14, and 16 by a memory controller. The image data components Y, U, and V, which are stored in the respective line memories 12, 14, and 16 by the image data processor 10, are read in sequences of 8*8 block units to be transferred to a JPEG compressor 20 through a multiplexer 18.

[0009] Each line memory 12, 14, and 16 may include additional peripheral circuits for driving the cell arrays of the corresponding line memories 12, 14, and 16. One such example is an address decoder. Thus, there is a great deal of hardware duplication when using multiple line memories. This causes an increase in design costs. Additionally, line memories have become larger and when the line memories are embedded in chips in order to operate a line memory system with low power, the chips also must increase in size. Finally, as the amount of image data increases in size, so must the line memories. As a result, the foregoing problems will grow more serious.

[0010] As discussed above, JPEG employs DCT for compression of data and DCT processes data on a block unit of 8*8 pixels and an image data processor of a camera generates image data (in a raster scan order, i.e., from left to right and from top to bottom throughout an image data). Accordingly, conversion of image data of a raster scan order into a block scan order requires a line memory that is capable of storing image data of at least 8 lines. While an image block of 8*8 pixels is produced from the line memory in which the image data of 8 lines are stored, the image data processor of the camera generates new image data. Therefore, a pair of line memory of 8 lines (one to read and one to write) is required to continuously process image data. In other words, while image data is written into one line memory in raster scan order, image data stored in the other line memory is read out in an 8*8 block. Because image data is divided into a luminance component Y and chrominance components U and V, a pair of line memories is needed for each image data component Y, U, V.

[0011] FIG. 3A is a schematic block diagram of another conventional VGA-standard image processing apparatus, and illustrates a pairwise line memory system for the luminance component Y only (a pairwise line memory system would also be necessary for each of the chrominance components U and V). Luminance components Y of 8 lines are output from the image data processor 10 and stored linearly into a first line memory Y1 (121). Second luminance components Y of 8 lines are stored linearly into a second line memory Y2 (122), and at the same time a reading operation is performed on the first line memory Y1 on an 8*8 block unit. To accomplish this, switch 181 of MUX 18 is closed and the 8*8 image data block read out from the second line memory Y1 (121) is transferred to the JPEG compressor 20.

[0012] FIG. 3B illustrates the pixel order from the image data processor 10 and FIG. 3C illustrates color components Y, U, V stored in their respective line memories 12, 14, and 16.

[0013] Write and read addresses of the first and second line memories 121 and 122 are generated by an address generator 24. For a 640×480 VGA image, as illustrated in FIG. 3D, the write address wr_addrline for the line memories 121 and 122 increases from 0 to 640*8−1. The read address rd_addrline for the line memories 121 and 122 for reading out image data in a block unit is set according to Equation 1 below.

[0014]

	for(i=0;i<640/8;i++){
	for( vv=0;vv<8; vv++){
	for( hh=0; hh<8; hh++){
	addr= vv*640+(i*8+ hh)=(vv*80+i)*8+ hh
	}
	}
	}

[0015] where “640” represents the number of horizontal pixels in the VGA standard, “i” represents the block order, “vv” is a variable represents a vertical pixel (line) of one block, “hh” is a variable representing a horizontal pixel of one block, and (vv*80+i) is an anchor address which holds its value for 8 cycles.

[0016] When third luminance components Y of 8 lines are stored into the first line memory Y1 (121) referring to the write address wr_addrline, the switch 181 of MUX 18 is opened and the switch 182 of MUX 18 is closed. A reading operation is performed on the second line memory_Y2 (122) on a block unit referring to the read address, and the read block is transferred to the JPEG compressor 20.

[0017] As illustrated and described, the foregoing conventional image processing method uses at least one line memory for each color component and possibly a pair of line memories for each color component. For example, in case of VGA standard, a pair of line memories of 640*8 bytes are used for the luminance component Y, and a pair of line memories of 320*8 bytes for each of the chrominance components U, V. Accordingly, in the event that the line memories are embedded in a chip in order to operate a system with low power, the chip may be increased in size. Still further, as the size of image data increases, the foregoing problem can become more serious.

[0018] In an exemplary embodiment, the present invention provides an image processing apparatus with a smaller line buffer memory for converting image data between a raster format and a block format.

[0019] In an exemplary embodiment, the present invention provides an image processing method for converting image data between a raster format and a block format, which is performed with a smaller line buffer memory.

[0020] In an exemplary embodiment, the present invention provides an image processing apparatus having a reduced number of line memories. For example, each image data component or color component is stored in a single unified line memory. In such an exemplary embodiment, since the number of extra circuits, such as an address decoder embedded in the memory is reduced, the line memory can be smaller in size.

[0021] In an exemplary embodiment, the present invention employs FIFO (First In First Out) small capacity memories for each color components so as to read image data in sequence of a block unit from a unified line memory. The image data components are read out from each FIFO memory, and stored in the unified line memory such that it is easy to read the image data in sequence of a block unit from the unified line memory.

[0022] In an exemplary embodiment, the present invention is directed to image processing apparatus for converting image data between a raster format and a block format, including an image data processor for providing the image data including a luminance component and at least one chrominance component in the raster format; at least two FIFO memories for storing corresponding image data components; a multiplexer for multiplexing the image data components from the at least two FIFO memories; a unified line buffer memory for storing outputs of the multiplexer linearly; and an image compressor for receiving the image data components in block format in sequence from the unified line buffer memory and compressing the received image data components.

[0023] In another exemplary embodiment of the present invention, the luminance component is the luminance component Y, and the chrominance components are the chrominance components U and V.

[0024] In another exemplary embodiment of the present invention, the multiplexing means multiplexes 2*h luminance components and 2*h chrominance components in this order to make it easy to read in sequence of a block unit from the unified line memory, where h stands for a horizontal resolution of one block format, or the number of pixels in horizontal direction. In the example of the JPEG standard, the horizontal resolution of one block format or the number of horizontal pixels is 8.

[0025] In another exemplary embodiment, the image data processor provides image data in the order of the luminance component Y, the chrominance component U, the luminance component Y, and the chrominance component V, i.e., YUYVYUYV□. The multiplexing means multiplexes in the order of 2*h numbered luminance components Y, h numbered chrominance components U, and h numbered chrominance components V, where h is a horizontal resolution of one block format. The JPEG compressor receives the image data in block format in the order of block Y, block Y, block U, and block V. That is, the JPEG compressor receives the image data in the order of Y, Y, U, V, Y, Y, U, V . . . and compresses the received image data.

[0026] In an exemplary embodiment, the unified line buffer memory has a size of H*v*2 bytes, where H is a horizontal resolution of image data and a multiple of v that is the vertical resolution of one block format. In the example of the JPEG standard, h equals 8 and H equals 640 in the VGA standard.

[0027] In an exemplary embodiment, the present invention is directed to an image processing apparatus comprising an image data processor, which provides image data of horizontal resolution H including a luminance of Y, U, Y, V . . . , FIFO memories for storing corresponding components Y, U, and V, a multiplexer for multiplexing 16 components Y, 8 components U, and 8 components V, a unified line buffer memory for storing output of the multiplexing means linearly, and an image processor receiving two blocks of luminance components Y, one block of chrominance component U, and one block of chrominance component V in this order and compressing the received image data components on a block unit.

[0028] In an exemplary embodiment, each block comprises 8*8 color components, and the unified line buffer memory has a size of H*8*2 bytes. That is, if a frame of image data can be divided into N blocks, the unified line buffer memory of the present invention has a capacity to store N blocks of components Y, N/2 blocks of components U, and N/2 blocks of components V.

[0029] According to an exemplary embodiment of the present invention, the image processing apparatus uses only one unified line buffer memory. Thus, since each extra circuit like an address decoder, which is embedded in the line buffer memory, is not required more than one, a size of the memory can be reduced. In addition, image data are stored in the unified line buffer memory by using a FIFO memory so as to make it easy to read on a block unit, i.e., in the order of 16 components Y, 8 components U, and 8 components V.

[0030] In an exemplary embodiment, the present invention provides an image processing method wherein image data including different color components in a raster format are stored into a single unified line buffer memory. Each color component is stored into respective FIFO memory of small capacity and multiplexed into the single unified line buffer memory so as to be easily read on a block unit. Thereafter, each color component is stored in the unified line buffer memory.

[0031] In an exemplary embodiment, the present invention provides an image processing method comprising providing image data, which include a luminance component and a pair of chrominance components, in a raster format, storing the image data into corresponding FIFO memories, storing the image data stored in the FIFO memories into a single unified line buffer memory, and outputting the image data in sequence of a block format.

[0032] In another exemplary embodiment, the image data are stored in the unified line buffer memory in the order of 16 luminance components, first 8 chrominance components, and second 8 chrominance component. The image data stored in the unified line buffer memory are outputted in the order of two blocks of luminance components, one block of first chrominance component, and one block of second chrominance component in sequence. Preferably, the luminance component is Y, the first chrominance component is U, and the second chrominance component is V.

[0033] In an exemplary embodiment, the present invention provides an image processing method, storing the image data stored in the FIFO memories into single line buffer memory comprises reading the image data from the FIFO memories in the order of the 16 luminance components, the first 8 chrominance components, and the second 8 chrominance components, then writing the image data linearly in the unified line buffer memory to the reading order. In an exemplary embodiment, when the image data are read from the FIFO memory and written in the unified line buffer memory, new image data are stored in the FIFO memory.

[0034] In an exemplary embodiment, reading an initial luminance component from the FIFO memory starts after 8 chrominance components Y are stored into the FIFO memory.

[0035] In another exemplary embodiment of the present invention, the reading an initial luminance component from the FIFO memory can start after 16 chrominance components Y are stored into the FIFO memory.

[0036] In an exemplary embodiment, the present invention is directed to an image processing apparatus for converting image data between raster scan order and block scan order including an image data processor for providing image data including a horizontal resolution H and a vertical resolution V in a raster scan order; a single line memory for storing image data of v lines; an address generator for generating a common read/write address for the single line buffer memory; and an image compressor for receiving image data of a v*h block unit from the single line memory and compressing the received image data, wherein when the image data of v lines are read out from the single line memory in a block scan order referring to the common read/write address, next image data of v lines are written into the single line memory with reference to the same common read/write address.

[0037] The common read/write address generator may comprises a pair of address buffers for storing an anchor address, and an address controller for synthesizing the common read/write address based on the anchor address. The anchor address has values of 0˜H*v/h−1, which increments on every h pixels of v*H pixels of image data of v lines. An anchor address is stored into one address buffer in a block scan order with respect to an order of an anchor address stored in the other address buffer.

[0038] The anchor address stored in the one address buffer may be f[n], where f[n] is an anchor address stored in an nth address of the other address buffer and n equals (H/h)*vv+i, wherein “i” represents a block order of image data of v lines and increments from 0 to (H/h)−1. “vv” stands for the number of lines of a block and increments from 0 to v−1 with respect to each i. That is, anchor addresses stored in addresses 0, H/h, H/h*2, H/h*3, . . . , H/h*(v−1), 1, H/h+1, H/h*2+1, H/h*3+1, . . . , H/h*(v−1)+1, . . . of the other address buffer are stored in sequence in addresses 0, 1, 2, 3, . . . , v−1, v, v+1, v+2, v+3, v+7, . . . of the one address buffer.

[0039] In another exemplary embodiment, an address controller provides a read address for reading out the anchor address from the one address buffer as well as a write address for writing the anchor addresses read out from the one address buffer into the other address buffer. The address controller synthesize the common read/write address by multiplying the anchor address read out from the one address buffer by h and adds hh which increments 0˜h−1.

[0040] In another exemplary embodiment, the address controller provides the read address n=(H/h)*v+i for the one address buffer, and the write address incrementing from 0 to H−1 for writing the anchor address read out by the read address n=(H/h)*v+i into the other address buffer.

[0041] When the next image data of v lines are read out from the single line memory and next following image data of v lines are written into the single line memory, the address controller provides the read address n=(H/h)*v+i so as to read out the anchor address from the one address buffer, and provides the write address incrementing from 0 to H−1 so as to write the anchor address read out from the one address buffer into the other address buffer.

[0042] In an exemplary embodiment, the present invention is directed to an address generator for converting image data between a raster scan order having a resolution V*H and a block scan order of v*h pixels by using one line memory, which comprises a pair of address buffers and an address controller. Each of a pair of the address buffers converts between read and write operation modes having complementary operation mode to the other, and stores the anchor address. The address controller provides a read address for the address buffers for the read operation mode as well as a write address for the address buffers for the write operation mode, and synthesizes common read/write address for to the line memory based on the anchor address read out from the address buffers.

[0043] The anchor address has values of 0˜v*H/h−1, which increment on every h pixels of v*H pixels written into the line memory. The anchor address read out from one address buffer referring to the read address is written into the other address buffer referring to the write address. At this time, the read address is given (H/h)*v+i to correspond to the block scan order (here, “i” stands for the block order of the image data of v lines, and increments from 0 to (H/h)−1, and “v” stands for the number of lines of one block and increments from 0 to v−1 with respect to each i), and the write address is given incrementing 0 to v*H/h−1.

[0044] The common read/write address is synthesized by multiplying the anchor address read out by the read address by h and adds hh, where hh increments from 0 to h−1 with respect to each “vv”.

[0045] In another exemplary embodiment of the present invention, h equals 8 and v equals 8.

[0046] Preferably, conversion between the read and write operation modes is made when data of the address buffer are completely renewed.

[0047] In an exemplary embodiment, the present invention is directed to an image processing method for converting image data between a raster scan order and a v*h block scan order by using a single line memory, comprising: providing first and second address buffers; generating read address and write address for the address buffers; storing image data of v lines into the single line memory and storing an anchor address generated on every h pixels into the first address buffer with reference to the write address; reading out the anchor address stored in the first address buffer by referring to the read address and storing the read anchor address into the second address buffer referring to the write address; generating common read/write address for the line memory based on the anchor address read out by the read address; reading the image data of v lines referring to the common read/write address out from and at the same time writing new image data of v lines into the line memory; and repeating the reading out the anchor addresses, generating the common read/write addresses, and reading the image data of v lines until all image data are completely processed, wherein every time the reading out the anchor addresses, generating common read/write addresses, and reading the image data of v lines are repeated, the address buffers are alternately referred to by the read and write addresses, the write address increments in sequence, and the read address corresponds to the block scan order.

[0048] In the image processing method, if image data, which will be processed, have a resolution of V*H, the anchor address has values of 0˜v*H/h−1, the write address increments on every h pixels from 0 to v*H/h−1, and the read address is H/h*vv+i (here, “i” is a variable standing for a block order of v*H image data written into the single line memory and increments from 0 to H/h−1. “vv” is a variable standing for an order of lines of a block and increments from 0 to v−1 with respect to each i) and maintains a value on every h pixels. The common read/write address is f[(H/h*vv+i)]*h+hh (where “hh” is a variable standing for an order of horizontal pixels of a block and increments from 0 to h−1 with respect to each and f[(H/h*vv+i)] is the anchor address read out by the read address H/h*vv+i from the address buffer).

[0049] In another exemplary embodiment of the present invention, v equals 8 and h equals 8.

[0050] In an exemplary embodiment, the present invention is directed to An image processing method for converting image data between a raster scan order having a resolution V*H and a 8*8 block scan order, comprising: writing image data of 8*H pixels linearly into a single line memory, and writing an anchor address maintaining a fixed value on every 8 pixels, into a first address buffer referring to a write; reading the anchor address stored in the first address buffer with reference to a read address; storing the anchor address read out from the first address buffer into a second address buffer with reference to the write address, and synthesizing a common read/write address based on the read anchor address; reading out the image data of 8*H pixels from the single line memory referring to the common read/write address, and at the same time writing image data of next 8*H pixels into the single line memory referring to the common read/write address; repeating the reading the anchor address, storing the anchor address, and reading out the image data of 8*H pixels until the image data of V*H pixels are completely processed, wherein every time the reading the anchor address, storing the anchor address, and reading out the image data of 8*H pixels are repeated, the address buffers are alternately referred to by the read and write addresses, the write address increments in sequence from 0 to H−1, and the reading address satisfying (H/8)*vv+i, where “i” represents an order of a block of image data of 8 lines and increments from 0 to (H/8)−1, “vv” represents the number of lines of a block and increments from 0 to 7 with respect to each i, and the common read/writing address is synthesized by multiplying the anchor address read out by the read address by 8 and adding hh incrementing 0˜7.

[0051] In another exemplary embodiment of the present invention, v equals 8 and h equals 8.

[0052] In an exemplary embodiment, the present invention is directed to image processing apparatus and method for converting image data between a raster scan order and a block scan order, which employs a reduced number of line memories. In other words, the present invention uses a single line memory for each color components and a pair of address buffers in order to perform a read operation of a raster scan order and a write operation of a block scan order in succession in the single line memory. Each address buffer stores a value (hereinafter referred to as an “anchor address”) obtained by dividing a first address of each line (hereinafter referred to as a “segment”) of a block by 8 when first 8 lines of image data are stored into line memory from address 0 to last address in sequence. Each segment includes 8 pixels, and eight segments constitute one block. For instance, in case of luminance components of VGA standard using JPEG, the anchor address is 0, 1, 2, 3, . . . , 638, 639. One address buffer stores the anchor address in the different order from the order of an anchor address stored in the other address buffer. Namely, the one address buffer stores anchor address in order corresponding block scan order (for example, in the order of 0, 80, 160, . . . , 560, 1, 81, . . . , 561, 2, 82, 162, . . . , 78, . . . , 638, 79, 159, 239, . . . , 559, 639) with respect to the order of the anchor address (0, 1, 2, 3, . . . 638, 639) stored in the other address buffer. When image data of initial 8 lines are written (stored) linearly into the single line memory, the anchor address (0, 1, 2, 3, . . . , 638, 639) incrementing on every 8 pixels are written into the first address buffer at address 0˜639. The common read/write address is generated by the address controller so as to generate 8*8 image blocks, i.e., to read out image data of first 8 lines from the single line memory on an 8*8 block unit. The address controller reads out the anchor address (0, 1, 2, 3, . . . , 638, 639) stored in the first address buffer in the block scan order (i.e., read out the anchor address at address 0, 80, 160, . . . , 560, 1, 81, . . . , 561, 2, 82, 162, . . . , 78, . . . , 638, 79, 159, 239, . . . , 559, 639) and stores the read anchor address in a second address buffer at address 0˜639. The common read/write addresses are synthesized by multiplying the read anchor address of the block scan order by 8 and adding 0˜7 in sequence. The first 8 lines are read out in the block scan order referring to the common read/write address from the single line memory and at the same time second 8 lines are written into the single line with reference to the common read/write address. The read address for reading out the anchor address from the first address buffer is (640/8)*vv+i and, here, “i” represents the block order of image data and increments from 0 to 79. “vv” increments from 0 to 7 with respect to each “i”. That is, in the first address buffer, the anchor addresses stored in address 0, 80, 160, . . . , 1, 81, . . . are read out in this order.

[0053] A common address for reading out the second 8 lines from and writing third 8 lines into the single line memory is synthesized based on the anchor address (0, 80, 160, . . . , 560, 1, 81, . . . , 561, 2, 82, 162, . . . , 78, . . . , 638, 79, 159, 239, . . . , 559, 639) stored in the address numbers 0˜639 of the second address buffer. The read address of the second buffer address is the same as the read address of the first buffer address. That is, the anchor addresses stored in the address 0, 80, 160, . . . , 560, 1, 81, . . . , 561, 2, 82, 162, . . . , 78, . . . , 638, 79, 159, 239, . . . , 559, 639 of the second address buffer are read out and written into the first address buffer in address 0˜639. Similarly, the read anchor addresses from the second address buffer are multiplied by 8 and added by 0˜7 in sequence, thereby synthesizing the common read/write address.

[0054] The foregoing steps are repeated until a frame of image data (in case of JPEG, the frame of image data is 680*480) is completely processed. According to the present invention, the read address of the address buffer is always generated according to the fixed pattern, i.e., (640/8)*vv+i and the write address always increments from 0 to 639. When 8 lines are completely processed, the anchor address of the address buffer is renewed and replaced by an anchor address of a new order. The write address of the address buffer can be easily embodied by using a counter and likewise the read address having the fixed pattern can be easily embodied using a counter, a multiplier, and an adder.

[0077] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. Below, “H” represents a horizontal resolution of image data, or the number of pixels in horizontal direction, and “h” represents a horizontal resolution of a block, or the number of pixels in horizontal direction of a block. In case of a VGA standard, a horizontal resolution “H” is 640 and a vertical resolution “V” is 480.

[0078] FIG. 4 is a schematic block diagram of an image processing apparatus including a single unified line memory system according to an exemplary embodiment of the present invention. The image processing apparatus includes an image data processor 100 for providing image data in raster format, a JPEG compressor 200 for compressing image data in a sequence of block units, e.g., in sequence of a 8*8 block units, and a line buffer system 150 for converting image data between a raster format and a block format between the image data processor 100 and the JPEG compressor 200. The image data processor 100 generates digital data of color components including luminance components and chrominance components. For example, the luminance component is Y and the chrominance components are U and V. The image data processor 100 may generate the luminance component Y and the chrominance components U and V in the 4:2:2 format, the 4:4:4 format, or in any other format known to are of ordinary skill in the art. In case of the 4:2:2 format, the image data processor 100 generates the luminance and chrominance component in the order of Y, U, Y, V, Y, U, Y, V . . . in a raster format. The following discussion assumes that the image data processor 100 generates the luminance components and chrominance components in the 4:2:2 format, but this need not be the case.

[0079] According to the line buffer system 150 of exemplary embodiments of the present invention, the image data comprising the luminance and chrominance components, which are generated from the image data processor 100, are stored in a unified line buffer memory 180. The unified line buffer memory 180 may store image data of at least 8 lines for conversion of a scanning format (conversion between a raster format and the 8*8 block format). Since the image data processor 100 generates image data in the 4:2:2 format, the unified line buffer memory 180 has a size of at least H*8*2 bytes. Unlike a conventional apparatus using a separate line buffer for each color component, the present invention in exemplary embodiments, provides an image processing apparatus with a single unified line buffer memory. Therefore, peripheral circuits for driving a memory cell array included in each line memory for each color component in conventional line memory system are unified into one peripheral circuit and, similarly, address decoders for reading a block unit are unified into one address decoder. As a result, a size of the line buffer memory 180 can be reduced over conventional image processing apparatus. FIFO memories 154, 156, and 158 of small capacity are used for each color component in order to store image data into the unified line buffer memory 180 in a format for the JPEG compressor 200. Each of the FIFO memories 154, 156, and 158 divides the image data generated from the image data processor 100 into color components and transfers the divided image data to the unified line buffer memory 180 through a multiplexer 160, so that each color component can be transferred to the unified line buffer memory 180 in a format for the JPEG compressor 200.

[0080] More specifically, image data Y0U0Y1V0Y2U1Y3V1 . . . output from the image data processor 100 is stored in the FIFO memories 154, 156, and 158 by color component under the control of a FIFO controller 152. That is, the luminance components Y are stored in the FIFO_Y memory 154 in the order of Y0Y1Y2Y3 . . . , the chrominance components U are stored in the FIFO_U memory 156 in the order of U0U1 . . . , and the chrominance components V are stored in the FIFO_V memory 158 in the order of V0V1 . . . .

[0081] The color components stored in the FIFO memories 154, 156, and 158 are stored (and also read out and written) in the unified line buffer memory 180 through the multiplexer 160 under the control of the FIFO controller 152. That is, a color component is read from a FIFO memory 154, 156, 158 and written in the unified line buffer memory 180. In this case, the FIFO controller 152 is used to control the multiplexer 160 such that each color component is stored in the format for the JPEG compressor 200, i.e., such that the color components are stored in sequence into the unified line buffer memory 180 in the order of 16 luminance components Y, 8 chrominance components U, and 8 chrominance components V. Accordingly, to start, the 16 luminance components Y are read out from the FIFO_Y memory 154, and then the 8 chrominance components U are read out from the FIFO_U memory 156, and then the 8 chrominance components V are read out from the FIFO_V memory 158. After repeating the foregoing process, the image data of 8 lines(8*H pixels) are stored into the unified line buffer memory 180. Namely, each line in the unified line buffer memory stores the H luminance components Y, the H/2 chrominance components U, and the H/2 chrominance components V.

[0082] The operation of the exemplary line buffer system 150 of FIG. 4 will be explained reference with FIG. 5 and FIGS. 6A-6E. FIG. 5 is an exemplary timing diagram of the exemplary line buffer system 150 for the 4:2:2 format.

[0083] Referring to FIGS. 5 and 6A-6E, storing each color component in one unified line buffer memory 180 will be described more fully hereinafter. FIG. 5 is a timing diagram for illustrating that image data Y0U0Y1V0Y2U1Y3V1 . . . in raster format from the image data processor 100 is stored linearly in the unified line buffer memory 180 in the order of (Y0Y1 . . . Y15)(U0U1 . . . U7)(V0V1 . . . V7)(Y16Y17 . . . Y31)(U8U9 . . . U15)(V8V9 . . . V15) . . . .

[0084] FIGS. 6A to 6E are schematic diagrams for illustrating that respective color components are stored in each of FIFO memories 154, 156, and 158.

[0085] In an exemplary embodiment, the FIFO_Y and FIFO_U memories 154 and 156 are 8 bytes and the FIFO_V memory 158 is 10 bytes.

[0086] Referring to FIG. 5, a clock CLK is generated from the image data processor 100. In synchronization with the clock CLK, the image data is output from the image data processor 100 in the order of Y0U0Y1V0Y2U1Y3V1 . . . , i.e., raster format. The FIFO controller 152 controls write signals WR_Y, WR_U, and WR_V so as to store the image data generated from the image data processor 100 into each FIFO memory 154, 156, and 158 by color component. In addition, the FIFO controller 152 controls read signals RD_Y, RD_U, and RD_V so as to transfer the color components stored in each FIFO memory 154, 156, and 158 to the unified line buffer memory 180 through the MUX 160 in the sequence of a block unit. The write signals WR_Y, WR_U, and WR_V and the read signals RD_Y, RD_U, and RD_V act on the respective FIFO memories 154, 156, and 158. The write signal WD_Y for writing the luminance component Y to the FIFO_Y memory 154 is activated at every odd numbered clock CLK, the write signals WD_U and WD_V for writing the chrominance components U and V are activated alternately at every even numbered clock CLK, or at an inactivation period of the read signal WD_Y. Thus, luminance component Y0 at first a clock C0 is stored in the FIFO_Y memory 154, chrominance component U0 is stored in the FIFO_U memory 156 at a second clock C1, Y1 is stored in the FIFO_Y memory 154 at a third clock C2, chrominance component V0 is stored in the FIFO_V memory 158 at a fourth clock C3, Y2 is stored in the FIFO_Y memory 154 at a fifth clock C4, U1 is stored in FIFO_U memory 156 at a sixth clock C5, Y3 is stored in the FIFO_Y memory 154 at a seventh clock C6, and V1 is stored in the FIFO_V memory 158 at an eighth clock C7.

[0087] When the FIFO_Y memory 154 is filled, a reading operation starts with the FIFO_Y memory 154 before a new luminance component Y is written into the FIFO_Y memory 154. For example, in case of an 8 byte FIFO_Y memory, since an eighth luminance component Y7 is stored in the FIFO_Y memory at a 15th clock C14, a first read signal RD_Y for luminance component Y is activated at a 17th clock C16. Read signal RD_Y is activated every 16 clocks (for example, during 17th clock C16˜32nd clock C31). At this time, 16 luminance components Y0˜Y15 are stored (written) into the unified line buffer memory 180 with a linearly increasing memory address. Meanwhile, the read signals RD_U and RD_V are activated alternately during an inactivation period of the read signal RD_Y, or during 16 clocks C32˜C47 following the 16 clocks where the read signal RD_Y is activated. For instance, the read signal RD_U is activated during 8 clocks C32˜C39 and the read signal RD_V is activated during the following clocks C40˜C47. Thus, the 8 chrominance components U and the 8 chrominance components V are read from each of the FIFO memories 156 and 158 and written into the unified line buffer memory 180. Next, reading operation is performed with the luminance component Y during the following 16 clocks C48˜C63, reading operation is performed with the chrominance component U during following 6 clocks C64˜C71, and reading operation is performed with the chrominance component V during following 8 clocks C72˜C79. By repeating the foregoing read operation, as addresses increase linearly in the unified line buffer memory 180 (for example, addresses increase in succession from address 0 to address H*8*2−1), the total H*8*2 color components are stored into the unified line buffer memory 180. Since write addresses for the unified line buffer memory 180 increase in succession, the write addresses generator can be readily embodied by using a simple counter.

[0088] In this case, while color components are read from each FIFO memory 154, 156, and 158, the image data processor 100 continues to output image data in synchronization with the clock CLK. Therefore, new color components continue to be written into each of the FIFO memories 154, 156, and 158. As a result, reading and writing operations for the FIFO memories 154, 156, and 158 are simultaneously carried out and will be described with reference to an example shown in FIGS. 6A to 6E.

[0089] FIGS. 6A to 6E illustrate color components stored in each FIFO memory 154, 156, and 158 at time t0, t1, t2, t3, and t4, respectively. Referring to FIG. 6A, at time t0, i.e., just before the 17th clock C16 is generated, 8 components Y (Y0˜Y7) have been stored in the FIFO_Y memory 154, and 4 components U (U0˜U3) and 4 components V (V0˜V3) have been stored in the FIFO_U and FIFO_V memories 156 and 158, respectively. The FIFO_Y memory 154 of 8 bytes has been filled with the luminance components Y. The FIFO_U memory of 8 bytes and FIFO_V memory of 10 bytes have been partially filled. As described above, a reading operation is performed at 17th clock C16. At the 17th clock C16, first luminance component Y0 is read out from the FIFO_Y memory 154 and written into the unified line buffer memory (for example, at address 0). At this time, 9th luminance component Y8 is written into the FIFO_Y memory 154 at a region where first luminance component Y0 was stored. At an 18th clock C17, second luminance component Y1 is read out from the FIFO_Y memory 154 and written into the unified line buffer memory (for example, at address 1), and at this time 5th chrominance component U4 is written into the FIFO_U memory 156. At a 19th clock C18, 3rd luminance component Y2 is read out from the FIFO_Y memory 154 and written into the unified line buffer memory (for example, at address 2), and at this time, 10th luminance component Y9 is written into the FIFO_Y memory 154. At a 20th clock C19, 4th luminance component Y3 is read out from the FIFO_Y memory 154 and written into the unified line buffer memory (for example, at address 3), and at this time, 5th chrominance component V4 is written into the FIFO_V memory 158. Thus, at time t1, as illustrated in FIG. 6B, the 8 luminance components Y (Y0˜Y7) have been read from the FIFO_Y memory, and there exist the new 4 luminance components Y (Y8˜Y11) and the prior 4 luminance components Y (Y4˜Y7), and 6 color components exist in the FIFO_U and FIFO_V memories, respectively. In this way, color components are read out from FIFO memories 154, 156, 158 and new color components are written into the FIFO memories 154, 156, 158.

[0090] As illustrated in FIG. 6C, at time t2, or at a 33rd clock C32 where the read signal RD_Y is inactivated, a reading operation is complete for the luminance components Y8˜Y15 (between t1 and t2) in the FIFO_Y memory 154. Consequently, 16 luminance components Y (Y0˜Y15) have been written into the unified line buffer memory 180. At this time, the luminance components Y8˜Y15 are in the FIFO_Y memory 154. The FIFO_U memory is filled with chrominance components U0˜U7. The chrominance components V0˜V7 are stored in the FIFO_V memory and an additional 2 chrominance components V (V8 and V9) can be stored during the following 8 clocks C32˜C39.

[0091] Referring to FIG. 6D, at time t3 (at a 41th clock C40), the chrominance components U0˜1 have been read out from the FIFO_U memory 156 and written into the unified line buffer memory 180 (for example, at addresses 16˜23), and the chrominance components U8 and U9 are written in the FIFO_U memory 156. Meanwhile, 4 luminance components Y (Y16 to Y19) have been written into the FIFO_Y memory 154 and the chrominance components V8 and V9 have been written in the FIFO_V memory 158. As a result, the FIFO_V memory 158 is filled with chrominance components V.

[0092] Referring to FIG. 6E, at time t4 (at a 49th clock C48), the chrominance components V0˜V1 have been read out from the FIFO_V memory 158 and written into the unified line buffer memory (for example, at address 23˜24), and the chrominance components V10 and V11 have been in the FIFO_V memory 158. Meanwhile, the 4 luminance components Y (Y20˜Y23) have been in the FIFO_Y 154 memory and, as a result, the luminance components Y16˜Y23 are in the FIFO_Y memory 154. The chrominance components U10 and U11 are newly written into the FIFO_U memory 156.

[0093] While color components are read from the FIFO memories 154, 156, 158 as described above, new color components, which are provided from the image data processor 100, are written in corresponding FIFO memories 154, 156, 158.

[0094] In the method of storing all color components in the unified line buffer memory 180, after storing the 8 components Y in the FIFO_Y memory 154, an initial read operation of the component Y begins. However, according to another exemplary embodiment, various changes and modifications are also possible. In other words, in the case of using a FIFO_Y memory of 16 bytes, after the 16 components Y are stored in the FIFO_Y memory 154, a read operation may start with an initial component Y. In this example, the FIFO_Y memory 154 may be 16 bytes, the FIFO_U memory 156 may be 12 bytes, and the FIFO_V memory 158 may be 14 bytes. Even in this case, after storing the 8 components Y in the FIFO_Y memory 154, a read operation may start with an initial component Y.

[0095] In addition, even if the format of the image data provided from the image data processor 100 changes, a size of the FIFO memory 154, 156, 158 may be adjusted to store the image data in the unified line buffer memory 180 such that a read operation is easily performed on a block unit.

[0096] FIG. 7 is a schematic diagram of the unified line buffer memory 180 in which the image data are stored. The unified line buffer memory 180 has a size of H*8*2 bytes and the memory address increases in series in a raster scan order (i.e., from left to right and from top to bottom). The image data in each line are repeatedly stored in the order of the 16 components Y, the 8 components U, and the 8 components V. Accordingly, a read address generating circuit for reading on an 8*8 block unit can be easily embodied.

[0097] The blocks are read in the order of the luminance block BY0, the luminance block BY1, the chrominance block BU0, the chrominance block BV0, the luminance block BY2, the luminance block BY3, the chrominance block BU1, the chrominance block BV1, . . . , the luminance block BY(N−2), the luminance block BY(N−1), the chrominance block BU(N/2−1), the chrominance block BV(N/2−1). Here, N equals H/8, i.e., a value obtained by dividing a horizontal resolution of the image data by 8.

[0098] More specifically, the image data are read out from the unified line buffer memory 180 in a sequence of block as follows. The image data at addresses 0˜7, addresses 2*H˜2*H+7, addresses 4*H˜4*H+7, addresses 14*H˜14*H+7 are sequentially read out from the unified line buffer memory 180 to form luminance block BY0. Then, image data at addresses 8˜15, addresses 2*H+8˜2*H+15, addresses 4*H+8˜4*H+15, addresses 14*H+8˜14*H+15 are read out from the unified line buffer memory 180 to form luminance block BY1. In this way, all the image data of 2*N blocks are read out from the unified line buffer memory 180 in block units.

[0099] A read address Add_R for reading on an 8*8 block unit from the unified line buffer memory 180 is produced by the following Equation 2 and can be readily embodied by using a counter.

[0100]

[Equation 2]
	for(i=0;i<(H*2)/8;i++){
	for(vv=0;vv<8;vv++){
	for(hh=0;hh<8;hh++){
	Add_R=vv*H*2+i*8+hh;
	}
	}
	}

[0101] In Equation 2, i is a variable standing for the block order of the unified line buffer memory 180, and “vv” and “hh” represent vertical and horizontal variables of the block.

[0102] It is further noted that additional unified line buffer memories 180 may be used. That is, while image data of 8 lines are written in a first unified line buffer memory 180 as described above, the image data can be read in a block unit from a second unified line buffer memory. If the image data of 8 lines are completely written and read, new image data of 8 lines are written in the second unified line buffer memory 180 and the prior image data written in the first unified line buffer memory 180 are read in a block unit.

[0103] While the method of converting data of a raster format into data of a block format is described above, the method can be applied to inverse conversion, i.e., conversion of data of a block format into data of a raster format.

[0104] When the line buffer system of an exemplary embodiment of the present invention and the typical line buffer system, which uses a separate line buffer memory by each color component, were applied to a VGA standard, the following Table 1 shows comparison of the number of required equivalent gates therebetween.

[0105]

	TABLE 1
	Conventional
	line buffer	single unified line buffer
	system	system of the present invention
memory bits	81920	81920
equivalent gate number	162280	128352
for embodying the line
buffer system
Equivalent gate number	0	2200
for embodying FIFO
memory
total gate number	162280	130552

[0106] The number of memory bits of the line buffer system of an exemplary embodiment of the present invention is the same as that of the typical line buffer system. In case of the conventional method using a separate line memory for each color component, the number of bits of the line memory is 640*8*8+(640/2)*8*8*2=81920. In case of the exemplary embodiment of the present invention using a unified line buffer memory 180, the number of bits of the line memory is 640*8*8*2=81920. However, while the typical method using three line memories requires a peripheral circuit for each line memory, the exemplary embodiment of the present invention requires only one peripheral circuit. Accordingly, the number of gates for embodying the line memory of the conventional method is 162280, and the number of gates for embodying the line memory of the exemplary embodiment of the present invention is 128352. The results were obtained through a simulation on the assumption that the line memory is embodied from a single port SRAM.

[0107] Because the exemplary embodiment of the present invention includes a FIFO memory including 8-byte FIFO_Y, 8-byte FIFO_U, and 10-byte FIFO_V, 2200 gates are needed to embody the FIFO memories. However, in case of the typical line memory system, the number of total required gates is 162280, and the exemplary embodiment of the present invention requires total 130552 gates. It can be seen that the exemplary embodiments of the present invention requires fewer gates than the conventional circuit.

[0108] FIG. 8 is a schematic block diagram of an image processing apparatus including a single line memory according to another exemplary embodiment of the present invention. The image processing apparatus of this exemplary embodiment of the present invention includes an image data processor 8100, a unified line memory 8120, an address generator 8140, and a JPEG compressor 8160. The image data processor 8100 generates image data. The image data is divided into a luminance component Y and chrominance components U and V. In FIG. 8, only a line memory_Y (8120) for the luminance component Y is shown. The image data processor 8100 outputs image data in synchronization with a clock. Chrominance components Y from the image data processor 8100 are stored into the line memory_Y (8120). If the image data, which will be processed, has a resolution of V*H and the JPEG compressor 8160 processes the image data on a v*h block unit, the line memory_Y(8120) has a size of v*H bytes. For example, in case of JPEG compression, v equals h and h equals 8 (v=h=8). Hereinafter, the case that VGA standard will be described as an example.

[0109] The address generator 8140 generates read and write addresses for the line memory_Y (8120). In an exemplary embodiment of the present invention, the read address of the line memory_Y(8120) is the same as the write address of the line memory_Y (8120). That is, a write operation is performed with a memory cell into which an address for read operation is applied. The address generator 8140 in an exemplary embodiment of the present invention includes a pair of address buffers 8142 and 8144, multiplexer 8146 for selecting one of the address buffers, and an address controller 8148. Each of the address buffers 8142 and 8144 has a size of ⅛ of the line memory_Y (8120) and the pair of address buffers 8142 and 8144 have a size of ¼ of the line memory_Y (8120).

[0110] The address controller 8148 generates read and write addresses for the address buffers and synthesizes a common read/write address for the line memory. Each of the address buffers 8142 and 8144 store anchor addresses for 8*H pixels stored in the single line memory_Y (8120). Accordingly, the anchor addresses are 0, 1, 2, 3, . . . , 637, 638, 639, and each address buffer 8142, 8144 stores 640 anchor addresses. As described above, each address buffer 8142, 8144 stores the anchor addresses in a different order.

[0111] The address controller 8148 generates a read address and a write address for the address buffers 8142, 8144 to read out the anchor address from the address buffers 8142, 8144 and write the read anchor address into the address buffers 8142, 8144. The address controller 8148 synthesizes the common read/write address for the line memory_Y (8120) based on the read anchor address. With reference to the common read/write address, image data are read out from and new image data are written into the single line memory 8120. That is, an address of a first pixel of a segment is obtained by multiplying the anchor address read out by the read address by 8 and a read/write address of 8 pixel of the segment is obtained by adding 0˜7 in sequence to the address of the first pixel.

[0112] The anchor address read out from one address buffer with reference to the read address is stored in the other address buffer with reference to the write address. The read address is (640/8)*vv+i corresponding to block scan order where, “i” represents a block order of image data and increments from 0 to 79(=640/8−1). “vv” is a variable represents for the number of lines of each block and increments from 0 to 7 with respect to each “i”. In other words, the anchor addresses stored in address 0, 80, 160, . . . , 560, 1, 81, . . . of the address buffer are read. On the other hand, the write address always increments from 0 to 639.

[0113] Common read/write address crw_addr are obtained by Equation 3 as follows.

[0114]

[Equation 3]
	for(i=0;i<640/8;i++){
	for(vv=0;vv<8;vv++){
	for(hh=0;hh<8;hh++){
	rd_addr=vv*640/8+i;
	crw_addr=f[rd_addr]*8+hh
	}
	}
	}

[0115] where, “vv*640/8+i” is the read address rd_addr, and f[rd_addr] is the anchor address stored at address of the address buffer pointed by the read address rd_addr.

[0116] When another value is used in place of 640 in Equation 3, a common read/write address corresponding to a size of image which will be processed can be generated.

[0117] For example, 640 maybe replaced 1280 when VGA images having three components Y, U and V are processed

[0118] While image data of 8 lines, i.e., 8*640 pixels are processed, each address buffer 8142, 8144 has a read or write operation mode. That is, the read address is applied to one address buffer 8142 to read the anchor addresses, and the write address is applied to the other address buffer 8144 to write the read anchor addresses. When the image data of 8 lines are processed, a selection signal with respect to the multiplexer 8146 is changed to change the operation mode of each address buffer. The read address is applied to the address buffer 8144 into which the write address had been applied, and the write address is applied to the address buffer 8142 into which the read address has been applied.

[0119] In another exemplary embodiment, the address controller 8148 generates a read address and a write address for the address buffers 8142, 8144 to read out the anchor address from the address buffers 8142, 8144 and write the read anchor address into the address buffers 8142, 8144. The address controller 8148 generate a read address (assuming a VGA luminance image) obtained by Equation 4 as follows.

[0120]

[Equation 4]
	x=0; x′=1;
	waddr_anchor = 0;
	For (i=0; i<640/8; i++){
	For (vv=0; vv<8; vv++){
	For (hh=0; hh<8; hh++){
	raddr_anchor = vv·80 + i;
	ABUFx′[waddr_anchor] = ABUFx[raddr_anchor];
	addr1 = ABUFx[raddr_anchor]·8 + hh;
	}
	waddr_anchor ++;
	}
	}
	x=~x; x′=~x′;

[0121] where “i” is the block index (0≦i≦80), “vv” is the vertical index in a block (0≦vv≦7), “hh” is the horizontal index in a block (0≦hh≦7), x, x′=0 or 1 (toggles at the end of loop)

[0122] Referring to FIGS. 9A-9D and 10A-10D, operation of an exemplary embodiment of the present inventions will be now described more fully. A line memory storing 8*80 pixels used as an example.

[0123] FIG. 9A-9D show that a segment (a line including horizontal 8 pixels constituting a block) of image data is stored in the line memory 8120. FIGS. 10A-10D show that the anchor address is stored into the address buffers 8142, 8144. In FIGS. 9 and 10, addresses of the line memory 8120 and the address buffers 8142, 8144 increase from left to right and from top to bottom.

[0124] The image data (raster H1) of 8*80 pixels, which are generated from the image data processor 100, are written into the line memory_Y (8120) at address from 0 to 639. That is, 80 segments (segment 0˜segment 79) are stored in the line memory 120 as illustrated in FIG. 9A. For example, the segment 0 comprises pixels 0˜7, and the segment 1 comprises pixels 8˜15, and the segment 10 comprises pixels 80˜87. At this time, the anchor addresses 0˜79, which are generated for every 8 pixels (i.e., which maintain a fixed value for every 8 pixels), are stored into address buffer 142 at address from 0 to 79 in sequence as illustrated in FIG. 10A. The anchor addresses 0˜79 correspond to values obtained by dividing the address into which a first pixel of each segment is stored by 8 when image data (8*80 pixels) of initial 8 lines are stored into the single line memory_Y (8120) in sequence. Accordingly, the anchor addresses 0˜79 indicate the addresses of the line memory_Y (8120) in which a first pixel of each segment is stored when the anchor address is multiplied by 8. The order of storing the segments in the line memory_Y (8120) shows that the image data are stored into the addresses of the line memory_Y (8120) corresponding to the anchor addresses in that order.

[0125] When 640 pixels are all stored into the line memory_Y (8120), the read address for the address buffer 8142 is generated by the address controller 8148. The read address is given as from Equation 3 or 4. That is, the read addresses for the address buffer 8142, 8144 are generated in the order of 0, 10, 20, 30, 40, 50, 60, 70, 1, 11, 21, 31, . . . and multiplied by 8 to obtain values of first pixels of respective segments.

[0126] To generate the 8*8 block, the common read/write address for the line memory is synthesized by the address controller 8148 according to Equation 3 or 4. In other words, the read address is applied to the address buffer1(8142) to read the anchor address, and the read anchor address is multiplied by 8 to obtain a value of the first pixel of the segment. Then, the values of the first pixels of the segments are added by 0˜7 to synthesize the common read/write address of pixels of the segment.

[0127] A read operation is performed with the line memory_Y (8120) on a block unit referring to the common read/write address. In this case, 8*80 pixels (raster H2) of new 8 line image data, which are generated from the image data processor 8100, are written into the line memory_Y (8120) referring to the common read/write address, as illustrated in FIG. 9B. The read anchor addresses are stored in sequence into the address buffer 144 referring to the write addresses, which increment from 0 to 79, as illustrated in FIG. 10B. After the common read/write address is generated according to Equation 3 or 4, read and write operations are performed in the line memory 8120. At this time, the anchor address with respect to the common read/write address are stored into the address buffer 144 which coincides with the anchor address of the address buffer 1(8142) read by the read address.

[0128] As described above, the 0^th segment of the raster H2 is stored at address 0˜7 (in which the 0^th segment of the raster H1 is stored) of the line memory, the second segment of the raster H2 is stored at address 10*8˜10*8+7 (in which the 10^th segment of the raster H1 is stored) of the line memory, and the third segment of the raster H2 is stored in the address numbers 20*8˜20*8+7 (in which the 20^th segment of the raster H1 is stored) of the line memory. At this time, the anchor addresses 0, 10, 20 . . . are stored into the address buffer 2(8144) at address 0 to 79. Thus, if the same read address are applied to the address buffer 8144, the raster H2 can be read out on a block unit.

[0129] Likewise, the raster H2 is read out from the single line memory 8120 on a block unit and image data (raster H3) of new 8 lines are written into the single line memory 8120 with reference to a common read/write address. That is, the anchor addresses 0, 21, 42, 63, 5, 26, 47, 68, 10, . . . , which are stored at address 0, 10, 20, 30, 40, 50, 60, 70, 1, . . . are read out from the address buffer 8144 with reference to read address rd_addr=vv*80/8+i, as illustrated in FIG. 10B, and the common read/write address is generated based on the read anchor addresses. Referring to the line memory 8120 of FIG. 9B, the anchor addresses correspond to the segments 0, 10, 20, 30, 40, 50, 60, 70, 1, . . . . This corresponds to the block scan order. The raster H2 is read out from the single line memory 8120 on a block unit referring to the generated common read/write address and at the same time image data (raster H3) of new 8 lines are written into the line memory (see FIG. 9C). At this time, anchor address read out from the address buffer 2(8144) are written into the address buffer 1(8142) at address 0˜79 in sequence as shown in FIG. 10C.

[0130] The anchor addresses 0, 52, 25, . . . are read out from the address buffer 8142 referring to the read address. Based on the read anchor addresses, the common read/write address is generated, and then the raster H3 is read out and image data (raster H4) of new 8 lines are written (see FIG. 9D). The anchor addresses read out from the address buffer 8142 are stored into the address buffer 8144 at address 0 to 79 in sequence (see FIG. 10D).

[0131] The foregoing steps are repeated until entire image (a frame of image) is processed. In case of the last 8 lines, only a read operation will be performed. That is, after image data of second last 8 lines are read out and at the same time the image data of the last 8 lines are written, only a read operation is performed for the image data of the last 8 lines. When the entire image is processed, another frame of image data may be processed the same way.

[0132] FIG. 11 is a schematic block diagram of an address generator 8140 according to another exemplary embodiment of the present invention. The luminance VGA standard will also be used as an example hereinafter. In case of the VGA standard, since a horizontal resolution is 640, the line memory 1120 has a size of 640*8*8 bits. When image data of initial 8 lines (8*640 pixels=5120 pixels) are stored in the line memory 120 at address from 0 to 5119 in sequence, the anchor addresses, which increment for every 8 pixels from 0 to 639, are generated. Accordingly, since the line memory 1120 stores 5120 pixels, the address for the line memory needs 13 bits and the anchor address needs 10 bits. For this reason, each of the address buffers 1142 and 1144 for storing the anchor addresses has a size of 640*10 bits.

[0133] A system clock, a horizontal synchronous signal, a vertical synchronous signal, a frame start signal are applied to the address controller 1148. The address controller 1148 generates various control signals for controlling the address buffers 1142, 1144, the multiplexer 1146, 1150, 1150′, 1152, 1152′, and 1154, and the line memory 1120 in response to the foregoing signals. The control signals include, for example, the anchor address, the write address, the read address, and the common read/write address.

[0134] The anchor address may be obtained by using a 3-bit counter. Alternatively, the anchor address can be obtained by shifting a 13-bit address by 3 bits when the image data of initial 8 lines are written into the line memory 1120 referring to the incremented 13-bit address. That is, if the initial write address for writing into the line memory 120 has a least significant bit (LSB) on the right as illustrated in FIG. 12A, the write address of the line memory is shifted to the right by 3 bits, thereby obtaining the anchor address as illustrated in FIG. 12B. In other words, the anchor address maintains the same value for every 8 pixels and increments from 0 to 639.

[0135] Because the common read/write address is obtained by multiplying the anchor address by 8 and adding 0˜7 (which are required to represent horizontal pixels of segments), the common read/write address becomes 13 bits. Multiplying the anchor address by 8 is equivalent to shifting the anchor address by 3 bits, and adding 0˜7 can be realized by adding 3 bits. That is, as illustrated in FIG. 13A, shifting 10 bits of the anchor address having LSB on the right to the left by 3 bits is equivalent to multiplying 8. This corresponds to the shifting of the 13 bits of the write address to the right by 3 bits for obtaining the anchor address. Therefore, the result obtained by multiplying the anchor address by 8 indicates the address of a first pixel of each block. Further, as illustrated in FIG. 13B, the result obtained by multiplying the anchor address by 8 is added by 3 bits to obtain horizontal components of each segment of a block. As a result, the common read/write address can be obtained with respect to all pixels of the block.

[0136] The address controller 1148 generates the read and write addresses raddr_anchor and waddr_anchor for the address buffers 1142 and 1144. The read addresses can be exemplarily generated by using a counter, multiplier, and adder. The write addresses waddr_anchor are generated on every 8 pixels of 8*640 pixels and increment from 0 to 639. The write address waddr_anchor can be embodied by using a counter. The read operation for the address buffers can be performed un-synchronized. If the read addresses raddr_anchor are applied to the address buffer 1142 and 1144, the anchor addresses at the address corresponding to the applied read address raddr_anchor are output terminals DOUT of the address buffers 1142 and 1144. The write operation for the address buffers is performed in synchronization. That is, when a write enable signal wen for writing operation is in a logic low state, the anchor address is written into a position corresponding to the applied write address waddr_anchor at a rising edge or a falling edge of a clock. The read operation can be performed in synchronization. In this case, a controlling signal for reading operation is applied and the anchor address stored in the applied read address is read out at a rising edge or a falling edge of a clock.

[0137] When the address buffer 1142 operates in a read mode (the write enable is at a high level), the address buffer 1144 operates in a write mode. When the address buffer 1142 operates in a write mode (the write enable is at a low level), the address buffer 1144 operates at a read mode. If image data of 8 lines (8*640 pixels) are completely processed, an operation mode of each address buffer is shifted. To accomplish this, the address generator 140 includes MUXes 1150, 1150′, 1152, 1152′, 1154 and 1146.

[0138] The MUX 1150 multiplexes the write enable wen and a logic high signal to transfer to a write mode input terminal WEN of the address buffer 1142. The MUX 1150′ multiplexes the write enable wen and the logic high signal to transfer to the write mode input terminal WEN of the address buffer 1144 and operates complementarily with respect to the MUX 1150.

[0139] The MUX 1152 multiplexes the read and write addresses raddr_anchor and waddr_anchor to transfer to an address input terminal A of the address buffer 1142. The MUX 1152′ multiplexes the read and write addresses raddr_anchor and waddr_anchor to transfer to the address input terminal A of the address buffer 1144 and operates complementarily with respect to the MUX 1152. Accordingly, when one address buffer operates on a write mode, the other address buffer operates in a read mode.

[0140] The address controller may be initialized when the first image data (PixelM [7:0]) is inputted into the line buffer memory 1120 from the image data processor 100 in FIG. 8. FIG. 14 is a timing diagram showing an initializing procedure according to an exemplary embodiment of the present invention.

[0141] The address controller 1148 generates the initializing signal (init), a write enable signal (wen) for the address buffer 1142, and write addresses (waddr_anchor). The write address increases from 0 to 639 by step 1 sequentially (waddr_anchor in FIG. 14). The wen signal becomes low during one clock time at every 8 clocks.

[0142] During the initialization, a data input port (DI) of address buffer 1142 is connected to waddr_anchor, therefore each location of address buffer 1142 stores its address. At the same time, the data from the image data processor 100 are stored in the unified line memory 1120 sequentially from address 0 to the last address.

[0143] After initialization, the contents of the address buffer 1142 are shown in FIG. 15. Also, after initialization, the init signal is disabled, therefore the data input port of the 1142 is connected to output port of the MUX 1146 through the MUX 1154.

[0144] The address controller 1148 outputs the wen, raddr_anchor, waddr_anchor signals. The waddr_anchor signals are generated the same as during initialization, as describe above. The wen signal makes the address buffer 1 1144 writable. The anchor address is determined by Equation 3 or 4, i.e., the content of the address buffer whose address is vv*80+i. When the anchor address is determined, the address stored in the address buffer 1144 is inputted to the address controller 1148.

[0145] The address controller 1148 calculates the line memory address by the equation
addr1 =ABUFx[vv*80+i]*8+hh,

• • [0146] wherein, the value of ABUFx[vv*80+i] is anchor address.

[0147] The read addresses for the address buffer 1142 are shown in FIG. 15. The procedure for writing the address in address buffer 1144 is shown in FIG. 16 and timing diagram for read and write is drawn in FIG. 17.

[0148] FIG. 18 shows the contents of the address buffer 1142 for the next 8 pixel rows.

[0149] The MUX 1146 multiplexes the anchor address generated from the output terminals DOUT of the address buffers to transfer to the address controller 1148 and the address buffers. The anchor addresses generated from one address buffer are written in sequence through an input terminal DI of the other address buffer, and inputted in the address controller 1148 to be used to generate the common read/write address.

[0150] If the selection signal is logic low (“0”), the MUX 1150 transfers the write enable wen to the write mode input terminal WEN of the address buffer 1142. On the other hand, the MUX 1150′ transfers the logic low (“0”) to the write mode input terminal WEN of the address buffer 1144. Accordingly, since the write mode input terminal WEN is low active, the address buffer 1144 does not operate in a write mode. However, the address buffer 1(1144) operates on a write mode if the write enable wen is applied as logic low.

[0151] The MUX 1152 transfers the write address waddr_anchor to the address buffer 1142 and the MUX 1152′ transfers the read address raddr_anchor to the address buffer 1144. The MUX 1146 selects the output of the address buffer 1144.

[0152] As illustrated in FIG. 19, the image data of 8 lines generated from the image data processor 100 are synchronized with the rising edge of the clock and stored in sequence in the line memory 1120. At this time, select signal is logic low level. Thus, the address buffer 1142 operates in a write mode, the address buffer 1144 operates in a read mode, and the MUX 1146 selects the generation of the address buffer 1144.

[0153] When the image data of 8 lines are generated from the image data processor 100 and stored in sequence in the line memory 1120, the anchor addresses, which increment on every 8 pixels from 0 to 639, as well as the write addresses write_addr are generated. Also, the generated anchor addresses 0˜639 are stored in the address buffer 1142 in sequence from the address 0 to 639 referring to the write address waddr_anchor. At this time, since the read address raddr_anchor is not generated by the controller 1148, an output does not originated from the address buffer 1144.

[0154] When all the image data of 8 lines (8*640 pixels) are written into the line memory_Y(1120), the selection signal of the multiplexing means is shifted from logic low to logic high (“1”). Accordingly, the write enable wen of logic high is inputted into the write mode input terminal WEN of the address buffer 1142. As a result, the address buffer 1142 does not operate in a write mode any more, and the read address raddr_anchor is transferred to the address buffer 1142 through the MUX 1152. That is, the address buffer 1142 is shifted to a read mode. Meanwhile, since the write enable wen of logic low is inputted into the write mode input terminal WEN of the address buffer 1144, the write mode input terminal WEN of the address buffer 1144 becomes active, and the write address waddr_anchor is transferred to the address buffer 1144 through the MUX 1152′. That is, the address buffer 1144 is shifted to a write mode. Meanwhile, the MUX 1146 selects the output of the address buffer 1142 and transfers to the address controller 1148 and the address buffer 1144.

[0155] The address controller 1148 generates the read address raddr_anchor and applies the generated read address to the address buffer 1142, thereby reading out the anchor address from the address buffer 1142. The read address raddr_anchor is generated to meet raddr_anchor=v*640/8+i. That is, the read address raddr_anchor is generated in the order of 0, 80, 160, 240, . . . , 560, 1, 81, . . . Accordingly, the anchor addresses stored in the address buffer0 (1142) at address 0, 80, 160, 240, . . . 560, 1, 81, . . . are output in sequence. The output anchor addresses are input into the address buffer 1144 and the address controller 1148 through the MUX 1146.

[0156] Since the anchor address maintains a fixed value for every 8 pixels, the write enable bar wen for writing the anchor address into the address buffer 1144 can be activated (i.e., logic low) anytime during 8 clocks. The write enable wen may be activated at every first clock as illustrated in FIG. 20. If the write enable wen is activated (becomes logic low), the anchor addresses 0, 80, 160, 240, . . . , 560, 1, 81, . . . , which are read out from the address buffer 1142, are stored in the address buffer 1144 from 0 to 639 in sequence referring to the incremented write address waddr_anchor.

[0157] Meanwhile, the common read/write address is generated by the address controller 1148 based on the anchor address output from the address buffer 1142 according to Equation 3 or 4. For example, the common read/write addresses are generated in this order 0˜7, 640˜647, 1280˜1287, 1920˜1927, . . . , 4480˜4487, . . . , 8˜15, 648˜655 . . . . The read operation is performed on the line memory 1120 according to the generated common read/write address and at the same time image data of new 8 lines are written in to the line memory 120 according to the generated common read/write address.

[0158] Likewise, if all the image data of new 8 lines are written into the line memory 120, the selection signal of the multiplexing means is shifted to low state again. Thus, the address buffer 1142 operates on a write mode again, and the address buffer 1144 operates on a read operation again. The MUX 1146 selects the anchor address output from the address buffer 1144 and the output anchor address is input into the address buffer 1142 and the address controller 1148.

[0159] The read address raddr_anchor is applied to the address buffer 1144 to obtain an anchor address, and the obtained anchor addresses are stored in the address buffer 1142 in sequence referring to the write address waddr_anchor. The address controller 1148 synthesizes common read/write address based on the anchor address obtained from the address buffer 1144. Referring to the generated common read/write address, the line memory 1120 is read out and at the same time the image data of another new 8 lines are stored.

[0160] If the read and write operations are complete with the line memory 1120, the selection signal of the multiplexing means is shifted to a high state again.

[0161] The foregoing steps are repeated until a frame of image data (480*640 pixels) is completely processed. After image data of last 8 lines are written into the line memory 1120, only a read operation is performed with the line memory 1120 referring to the common read/write address. Likewise, when first 8 lines of image data are output from the image data processor, only a write operation is performed on the line memory 1120.

[0162] FIG. 21 illustrates another exemplary embodiment of the present invention, namely the combination of the embodiments illustrated in FIGS. 4 and 11.

[0163] According to exemplary embodiments of the present invention as described above, the anchor addresses stored in the first address buffer in sequence are read out by pre-set read addresses (i.e., in a block unit) and stored in the second address buffer in sequence in the read order. The anchor addresses stored in the second address buffer are read out again by the read addresses and stored in the first address buffer in sequence. That is, the anchor addresses are stored in a pair of address buffers, each of which has a size of ⅛ of a line memory. This enables conversion of image data between a raster scan order and a block scan order to be easily embodied by using a single line memory. The read address of the address buffer represents as a fixed pattern, or H/8*vv+i, and the write address also represent a fixed pattern incrementing 0˜H−1. The write address pattern may be embodied by using a counter, and the read address pattern also may be embodied by using a shift register and adder. The common read/write address can be obtained by shifting the anchor address read out from the address buffer by 3 bits by shift register and adding 3 bits by adder.

[0164] In the foregoing technique, when the image data of first 8 lines are stored in the single line memory, the anchor address is set by dividing the address in which a first pixel of a segment is stored by 8. However, the anchor address can be set in different ways. That is, the anchor address can be set as the address in which a first pixel of a segment is stored. However, the read and write addresses of the address buffers need not be changed from foregoing technique. In case of the common read/write address, in Equation 3, the anchor address f[rd_addr] read out by the read address raddr_anchor may be incremented by only hh, which stands for a horizontal pixel of the segment. Namely, the common read/write address crw_addr equals f[rd_addr]+hh, and the read address raddr_anchor equals vv*640/8+i.

[0165] While the method for converting image data of a raster scan order into image data of a block scan order has been described above, the method can also be applied to inverse conversion, i.e., conversion of image data of a block scan order into image data of a raster scan order.

[0166] When the exemplary embodiments line buffer system of the present invention, which uses the single line memory as well as a pair of address buffers, and the typical line buffer system, which use a separate line buffer memory by each color component, are applied to VGA standard, the following Table 2 shows comparison of the number of required equivalent gates therebetween.

[0167]

	TABLE 2
		Line Buffer
	Typical Line	System of The
	Buffer System	Present Invention
Number of Memory Bits	81920	52480
Number of Equivalent Gates	79170	64471
for Embodying Memory

[0168] While the number of memory bits of the typical line system using a pair of line memories is 640*8*8*2, or 81920 bits, the number of memory bits of the exemplary embodiments of line buffer system of the present invention is 640*8*8+640*10*2, or 52480 bits. In case that the line memory is embodied from a single port SRAM, the conventional method needs 79170 gates and the exemplary embodiments of the present invention needs 64471 gates.

[0169] While exemplary embodiments of the present invention have been described in connection with specific and exemplary embodiments thereof, it is capable of various changes and modifications without departing from the spirit and scope of the invention. It should be appreciated that the scope of the invention is not limited to the detailed description of the invention hereinabove, which is intended merely to be illustrative, but rather comprehends the subject matter defined by the following claims.

[0170] According to exemplary embodiments of the present invention, since only one line memory is used with respect to each color component, a size of a memory can be reduced. Therefore, a downsized chip including the line memory can be obtained and a system can operate with low power.