Low-power clock gating circuit

[0001] This application claims priority to and the benefit of Korean Patent Application No. 2006-122514, filed Dec. 5, 2006, and No. 2007-54320, filed Jun. 4, 2007, the disclosure of which is incorporated herein by reference in its entirety.

[0002] 1. Field of the Invention

[0003] The present invention relates to a clock gating circuit capable of blocking a clock supplied in an active mode when a device in a targeted logic circuit does not operate and retaining data without leakage current in a sleep mode, by using a Multi-Threshold CMOS (MTCMOS) technique.

[0004] The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S-006-01, Components/Module technology for Ubiquitous Terminals] in Korea.

[0005] 2. Discussion of Related Art

[0006] FIG. 1 illustrates a conventional clock gating circuit using a single threshold voltage and including an AND gate 150. A gated clock GCLK is transferred to a flip-flop 200. When an enable signal EN is high, an input clock CP passes through the AND gate 150 and the gated clock GCLK is transferred to the flip-flop 200. When the enable signal EN is low, the gated clock GCLK becomes low irrespective of the input clock CP and the clock is not supplied to the flip-flop 200. Thus, the clock gating circuit has such a simple structure. However, the gated clock GCLK from the clock gating circuit of FIG. 1 may include glitch or spike.

[0007] FIG. 2 illustrates a clock gating circuit 160 comprising a latch circuit located at an input of the AND gate 150 to solve the problem associated with the clock gating circuit of FIG. 1, in which a conventional single threshold voltage is used. Here, when a 130 nm transistor operating at 1.2V is used, the single threshold voltage is about 0.34V. The configuration and operation of the conventional clock gating circuit of FIG. 2 will now be described. The clock gating circuit 160 using a single threshold voltage includes a transmission gate 100 that is controlled by a clock signal CP and an inverted clock signal CPb and receives an enable signal EN from a targeted logic gate 170, a feedback transmission gate 140 connected via a second inverter 130 for inverting an output signal of a first inverter 110, and an AND gate 150 for receiving the enable signal from the third inverter 120 via the first inverter 110 and the clock CP and outputting the gated clock GCLK.

[0008] The clock signal CP is generated by a clock signal generating circuit (not shown), and the inverted clock signal CPb is an inverted version of the clock signal CP.

[0009] Each of the transmission gate 100, the inverters 110, 120 and 130, the feedback transmission gate 140, and the AND gate 150 consists of a PMOS transistor and an NMOS transistor each having a single threshold voltage, i.e., an intermediate threshold voltage (normal Vt), as shown in FIGS. 3a and 3b.

[0010] Operation of the clock gating circuit of FIG. 2 will now be described.

[0011] When the clock signal CP is high and the inverted clock signal CPb is low, the transmission gate 100 is turned on and the feedback transmission gate 140 is turned off.

[0012] In this case, when the enable signal EN is high, the output signal passing through the first inverter 110 and the third inverter 120 becomes high and is input to the AND gate 150. The clock signal CP at a high level is also input to the AND gate 150. Accordingly, the gated clock GCLK becomes high to turn the targeted logic circuit 170 on.

[0013] On the other hand, when the enable signal EN is low, the output signal passing through the first inverter 110 and the third inverter 120 becomes low and is input to the AND gate 150. The clock signal CP at a high level is also input to the AND gate 150. Accordingly, the gated clock GCLK becomes low to turn the targeted logic circuit 170 off and block the clock.

[0014] When the clock signal CP is low and the inverted clock signal CPb is high, the transmission gate 100 is turned off and the feedback transmission gate 140 is turned on. Accordingly, the clock gating circuit enters a standby state and retains a previous data state in the feedback circuit.

[0015] Although a conventional clock gating circuit comprising a single threshold voltage can block the clock when a specific targeted circuit is not active, it is difficult to implement a high-performance and low-power circuit due to leakage current in a scaled-down device.

[0016] The present invention relates to a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The present invention is directed to a low-power clock gating circuit comprising a latch circuit and an AND gate circuit configured by the MTCMOS technique, in which power consumption caused by leakage current is reduced in a sleep mode, and supply of a clock to a targeted logic circuit is prevented in an active mode.

[0017] As described above, a conventional clock gating circuit using single threshold voltage devices cannot both block a clock and reduce power consumption caused by leakage current. To solve this problem, the present invention provides a low-power clock gating circuit including a latch circuit and an AND gate using an MTCMOS technique. The present invention is directed to a clock gating circuit which retains data without leakage current in a sleep mode, reduces power consumption caused by leakage current, and prevents a clock from being supplied to an unused targeted logic circuit in an active mode for reduction of power consumption in the targeted logic circuit.

[0018] One aspect of the present invention provides a clock gating circuit including a first inverter, a second inverter, an AND gate, a power terminal, a data terminal, a clock terminal, a sleep control terminal, and an output terminal, the clock gating circuit comprising: PMOS transistors electrically connected between the power terminal and the first inverter, between the power terminal and the second inverter, and between the power terminal and the AND gate and controlled by a sleep control signal applied via the sleep control terminal, each PMOS transistor having a high threshold voltage; and NMOS transistors electrically connected between a ground and the first inverter, between the ground and the second inverter, and between the ground and the AND gate and controlled by the sleep control signal, each NMOS transistor having a high threshold voltage.

[0019] Preferably, the sleep control signal comprises a sleep signal and an inverted sleep signal.

[0020] Each of the first inverter and the second inverter comprises a PMOS transistor having a low threshold voltage and an NMOS transistor having a low threshold voltage.

[0021] The AND gate comprises a PMOS transistor having a low threshold voltage and an NMOS transistor having a low threshold voltage.

[0022] The clock gating circuit further comprises a transfer gate connected between the data terminal and the first signal inverting circuit for transferring the data signal input via the data terminal to the first signal inverting circuit under control of a clock signal.

[0023] The clock gating circuit further comprises a feedback transfer gate for inverting an output signal of the first signal inverting circuit and transferring the inverted signal back to the first signal inverting circuit under control of the clock signal.

[0024] Another aspect of the present invention provides a clock gating circuit comprising: a first signal inverting circuit for inverting a data signal through a first inverter and outputting an inverted signal under control of a sleep control signal; a second signal inverting circuit for inverting the output signal of the first signal inverting circuit through a second inverter and outputting an inverted signal under control of the sleep control signal; and an AND gate circuit for receiving the output signal of the second signal inverting circuit and a clock signal and outputting a gated signal under control of the sleep control signal.

[0034] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention, however, may be changed into several other forms, and the scope of the present invention should not be construed to be limited to the following embodiments. The embodiments of the present invention are intended to more entirely explain the present invention to those skilled in the art.

[0035] In general, transistors include transistors having a low threshold voltage and transistors having a high threshold voltage. 130 nm transistors operating at 1.2V have a low threshold voltage of about 0.24V and a high threshold voltage of about 0.44V. In the description below, a signal inverting circuit may be simply referred to as an inverting circuit.

[0036] FIG. 4 illustrates a clock gating circuit using an MTCMOS technique according to the present invention, FIG. 5a illustrates a transmission gate circuit comprising low threshold voltage devices according to the present invention, FIG. 5b illustrates a transmission gate circuit comprising high threshold voltage devices according to the present invention, and FIGS. 6a to 6c illustrate individual circuits in an MTCMOS clock gating circuit shown in FIG. 4.

[0037] Referring to FIG. 4, the MTCMOS clock gating circuit 450 comprises a first signal inverting circuit 400 including: a first inverter 402 for inverting and outputting an enable signal EN under control of a sleep signal SP and an inverted sleep signal SPb; a transmission gate 410 for transferring an output signal of the first signal inverting circuit 400 under control of a clock signal CP, the transmission gate 410 having an equivalent circuit as shown in FIG. 5a; a second inverter 422 for outputting an enable signal from the transmission gate 410 under control of a sleep control signal SLP; an AND gate 444 for receiving an output signal of the second inverter 422; and a feedback circuit 430 including a feedback transmission gate 434 for feeding back an output signal of the second inverter 422 to retain data in a sleep mode, the feedback transmission gate 434 having an equivalent circuit as shown in FIG. 5b.

[0038] The first signal inverting circuit 400 includes: the first inverter 402 for receiving and inverting the enable signal EN; a first PMOS transistor G1 having a source connected to a power terminal, a gate for receiving the sleep signal SP, and a drain connected to the first inverter 402; and a first NMOS transistor G2 having a drain connected to the first inverter 402, a gate for receiving an inverted sleep signal SPb, and a source connected to a ground.

[0039] Here, the first inverter 402 consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage, which allows the enable signal to be transferred along the shortest path.

[0040] The first signal inverting circuit 400 is represented by an equivalent circuit as shown in FIG. 6a.

[0041] Referring to FIG. 6a, the first PMOS transistor G1 and the first NMOS transistor G2 have high threshold voltages, and the first inverter 402 consists of the PMOS transistor and the NMOS transistor each having a low threshold voltage.

[0042] The transmission gate 410 transfers the enable signal from the first signal inverting circuit 400 to the second signal inverting circuit 420 under control of the clock signal CP and the inverted clock signal CPb. The transmission gate 410 consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

[0043] The second signal inverting circuit 420 is represented by an equivalent circuit as shown in FIG. 6b.

[0044] Referring to FIG. 6b, the second signal inverting circuit 420 includes: the second inverter 422 for receiving and outputting the output signal of the transmission gate 410 under control of the sleep signal SP and the inverted sleep signal SPb; a second PMOS transistor G3 having a source connected to the power terminal, a gate for receiving the sleep signal SP, and a drain connected to the second inverter 422; and a second NMOS transistor G4 having a drain connected to the second inverter 422, a gate for receiving the inverted sleep signal SPb, and a source connected to a ground.

[0045] The second signal inverting circuit 420 has the equivalent circuit as shown in FIG. 6b when the NMOS transistor G6 in FIG. 4 is included. The second PMOS transistor G3 and the second NMOS transistor G4 have high threshold voltages, and the second inverter 422 consists of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

[0046] The feedback circuit 430 enables data to be retained when the MTCMOS latch circuit is in a sleep mode. The feedback circuit 430 consists of a PMOS transistor and an NMOS transistor having a high threshold voltage and small leakage current.

[0047] The feedback circuit 430 includes: a third inverter 432 for inverting and outputting an output signal of the second signal inverting circuit 420; a third PMOS transistor G5 having a source for receiving the output signal of the second signal inverting circuit 420 and a gate for receiving an output signal of the third inverter 432; a third NMOS transistor G6 having a drain connected to the second inverter 422 of the second signal inverting circuit 420, a gate for receiving an output signal of the third inverter 432, and a source connected to the ground; and a feedback transmission gate 434 for receiving the output signal of the third inverter 432 and transferring the same to the second signal inverting circuit 420 under control of the clock signal CP and the inverted clock signal CPb.

[0048] Each of the third inverter 432 and the feedback transmission gate 434 consists of a PMOS transistor and an NMOS transistor each having a high threshold voltage.

[0049] The AND gate circuit 440 has an equivalent circuit as shown in FIG. 6c. The AND gate circuit 440 includes the AND gate 444 for receiving the output signal of the second inverter 422 and the clock signal CP and outputting a gated signal GCLK to a targeted logic circuit 460 under control of the sleep signal SP and the inverted sleep signal SPb.

[0050] Referring to FIG. 6c, the sleep signal SP and the inverted sleep signal SPb are received at a PMOS transistor and an NMOS transistor each having a high threshold voltage, and the AND gate 444 consists of PMOS transistors and NMOS transistors each having a low threshold voltage.

[0051] Operation of the MTCMOS clock gating circuit 450 having the above-described configuration will now be described.

[0052] The MTCMOS clock gating circuit operates in an active mode when the sleep signal SP is low and the inverted sleep signal SPb is high and in a sleep mode when the sleep signal SP is high and the inverted sleep signal SPb is low.

[0053] First, operation of the MTCMOS clock gating circuit in an active mode will be described.

[0054] When the sleep signal SP is low, the first, second and fourth PMOS transistors G1, G3 and G7 and the first, second and fourth NMOS transistors G2, G4 and G8 each having a high threshold voltage are all turned on, and the inverted sleep signal SPb becomes high.

[0055] In this state, when the clock signal CP is high, the inverted clock signal CPb becomes low, such that the transmission gate 410 is turned on and the feedback transmission gate 434 is turned off.

[0056] Accordingly, the enable signal EN is output via the first signal inverting circuit 400, the transmission gate 410, the second signal inverting circuit 420, and the AND gate circuit 440.

[0057] When the sleep signal SP is low, the clock signal CP is low, and the inverted clock signal CPb is high, the transmission gate 410 is turned off and the feedback transmission gate 434 is turned on, such that a previous enable signal EN is output.

[0058] Thus, in the active mode, the MTCMOS clock gating circuit continues to output the enable signal EN as the clock signal CP is high/low.

[0059] When the clock signal CP is high and, at this time, the enable signal EN from the targeted logic circuit 460 is high, the gated signal GCLK from the AND gate circuit 440 becomes high and this high clock is transferred to the targeted logic circuit. However, when the clock signal CP is high and, at this time, the enable signal EN from the targeted logic circuit 460 is low, the gated signal GCLK from the AND gate circuit 440 becomes low and this low clock is transferred to the targeted logic circuit, thereby preventing the clock from being transferred to a undesired device.

[0060] When the clock signal CP is low, the MTCMOS clock gating circuit retains a previous signal in the feedback circuit 430 irrespective of the enable signal EN from the targeted logic circuit 460, and remains in a standby state.

[0061] Thus, in the active mode, the MTCMOS clock gating circuit transfers a signal at a high speed because all of the first inverter 402 of the first signal inverting circuit 400, the transmission gate 410, the second inverter 422 of the second signal inverting circuit 420, and the AND gate 444 of the AND gate circuit 440 consist of a PMOS transistor and an NMOS transistor each having a low threshold voltage.

[0062] Next, operation of the MTCMOS clock gating circuit in the sleep mode will be described.

[0063] When the sleep signal SP is high, the MTCMOS clock gating circuit operates in the sleep mode.

[0064] If the sleep signal SP is high, i.e., when the sleep signal SP is high and the inverted sleep signal SPb is low, the first, second and fourth PMOS transistors G1, G3 and G7 and the first, second and fourth NMOS transistors G2, G4 and G8 each having a high threshold voltage are turned off. Accordingly, the enable signal EN is retained in the feedback circuit 430.

[0065] That is, if the output of the second inverter 422 is low, a high signal is applied to the gate of the third NMOS transistor G6 via the third inverter 432 to turn the third NMOS transistor G6 on, and also applied to the gate of the third PMOS transistor G5 to turn the third PMOS transistor G5 off.

[0066] In this case, when the clock signal CP is low, the feedback transmission gate 434 is turned on, a high signal is applied to the second inverter 422, which outputs a low signal. In this case, the output of the second inverter 422 remains low because it is connected to the ground via the NMOS transistor in the second inverter 422 and the third NMOS transistor G6, as shown in FIG. 6b.

[0067] If the output of the second inverter 422 is high, a low signal is applied to the gate of the third NMOS transistor G6 via the third inverter 432 to turn the third NMOS transistor G6 off, such that the second inverter 422 does not operate. The low signal is also applied to the gate of the PMOS transistor G5 via the second inverter 432 to turn the PMOS transistor G5 on, and the output of the second inverter 422 remains high as the source and the drain of the third PMOS transistor G5 are high.

[0068] Thus, because the feedback circuit 430 is intended to retain data, it consists of a PMOS transistor and an NMOS transistor having a high threshold voltage and accordingly small leakage current. This allows the feedback circuit 430 to be designed with a minimum size.

[0069] According to the present invention, the clock gating circuit using the MTCMOS technique can minimize power consumption caused by leakage current in nano-level devices and contribute to high-speed operation of logic circuits by using low threshold voltage devices. Furthermore, the clock gating circuit prevents the clock from being supplied to an unused device in response to a state signal, thereby reducing power consumption in the targeted logic circuit. The clock gating circuit using the MTCMOS technique according to the present invention may be widely utilized for a bus interface of a slave device in a system having a pipeline bus structure, and may also be applied to mobile devices for considerable reduction of power consumption.

[0070] While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.