Method for forming fine pattern of semiconductor device

[0001] The priority benefit of Korean patent application number 10-2007-0054974, filed on Jun. 5, 2007, is hereby claimed and the disclosure thereof is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to a method for forming a fine pattern of a semiconductor device.

[0003] Due to the popularization of information media such as computers, semiconductor device technology has advanced rapidly. Semiconductor devices are required to operate at a high speed and to have a high storage capacity. As a result, manufacturing technology of semiconductor devices is required to manufacture a memory device of high capacity with improved integration, reliability and characteristics for accessing data.

[0004] In order to improve integration of the device, photolithography technology has developed to form fine patterns. The photolithography technology includes an exposure technology using chemically amplified Deep Ultra Violet (DUV) light sources such as ArF (193 nm) and VUV (157 nm), and a technology for developing photoresist materials suitable for the exposure light sources.

[0005] As a semiconductor device becomes smaller, it is important to control a critical dimension of a pattern line-width in the photolithography technology. Generally, the processing speed of semiconductor devices depends on the critical dimension of the pattern line-width. For example, as the line-width of the pattern is decreased, the processing speed is increased to improve device performance.

[0006] However, it is difficult to form a line/space pattern of less than 40 nm by a single exposure process in the photolithography process using an ArF exposer having a common numerical aperture of less than 1.2.

[0007] In order to improve resolution of photolithography technology and extend a process margin, a double patterning technology has been developed. The double patterning technology includes processes whereby a photoresist-coated wafer is respectively exposed by two masks, and then developed, thereby obtaining a complicated pattern, a dense pattern or an isolated pattern.

[0008] Since the double patterning technology uses two masks for patterning, the manufacturing cost and the turn-around-time are lower than those of a single patterning technology using a single mask, thereby degrading the throughput. When a pattern having a smaller pitch than a resolution limit of the exposer is formed in the cell region, illusory images are overlapped. As a result, the double patterning technology does not obtain a desired pattern. In alignment, overlays are mis-aligned.

[0009] Various embodiments of the present invention are directed at providing a method for forming a fine pattern of a semiconductor device which has a smaller pitch than a resolution limit of the exposer.

[0010] According to an embodiment of the present invention, a method for forming a fine pattern of a semiconductor device comprises forming a stack layer including first, second, and third mask films over a semiconductor substrate having an underlying layer. The photoresist pattern is formed on the third mask film. The third mask films are etched with the photoresist pattern as an etching barrier mask to form third mask patterns. The second and first mask films are etched with the third mask patterns as an etching barrier mask to form a first and second mask pattern. The second mask pattern is side-etched with the third mask pattern as an etching barrier mask. The third mask pattern is removed. A spin-on-carbon layer through which the upper portion of the second mask pattern is exposed is coated over first and second mask patterns and the underlying layer. A part of the first pattern and the second mask pattern are removed by the spin-on-carbon material as an etching barrier mask to expose the underlying layer. The spin-on-carbon layer is removed to obtain a fine first mask pattern having a uniform line-width.

[0011] The underlying layer can comprise a conductive layer with a stack pattern of an insulating film and a polymer layer as a top layer. The first and third mask films have a different etching selectivity ratio from that of the second mask film. For example, the first mask film is a tungsten layer. The second mask film preferably is selected from one or more of a silicon nitride film (SiN), a silicon oxide film (SiO), a silicon oxy-nitride film (SiON), and a stack layer including at least one or more films thereof. The third mask film preferably is selected from one or more of an amorphous carbon layer, a stack layer including an amorphous carbon layer and a silicon oxy-nitride film, and a multi mask film. The multi mask film preferably is formed by i) a spin-on-carbon material where a carbon element is present in an amount in a range of 85 wt % to 90 wt % based on the total compound molecular weight, or ii) the composition for mask comprising Si compound where a Si element is present in an amount in a range of 30 wt % to 80 wt % by weight based on the total compound molecular weight. The ii) Si compound preferably is selected from the group consisting of a Si-containing polymer, an oligomer of the Si-containing polymer and a spin-on glass (SOG) material such as Hydrogen Silses-Quioxane (HSQ) and Methyl Silses-Quioxane (MSQ).

[0012] The side-etching-the-second-mask-pattern step is performed by a trimming etching process. The trimming etching process has a higher polishing speed in the second mask film than that of first and third mask films. The trimming etching process is performed with an etching gas having a flow ratio of fluoro hydrocarbon (ex. CHxFy, here x and y are an integer ranging from 1 to 10): SF₆=2-10:1. Here, the fluoro hydrocarbon gas is a CHF₃ gas.

[0013] After the side-etching process is performed on the second mask pattern, the second mask pattern has a reduced line-width preferably by about 20-50%, specifically 30-40%, more specifically, 30-35% in comparison with that of the second mask pattern before the side-etching process is performed.

[0014] The removing-the-third-mask-pattern and the-spin-on-carbon-layer steps preferably are each performed by an oxygen ashing process. A ratio of line-width of the first mask pattern to interval between the first mask patterns is 1:1.

[0015] In one embodiment, a method for forming a fine pattern of a semiconductor device comprises forming a stack layer including first through third mask films over a semiconductor substrate having an underlying layer. The second and third mask films are etched to form a second and third mask patterns. The first mask film is partially etched with the second and third mask patterns as an etching barrier mask. The side-etching process is performed to the second mask film with the third mask pattern as an etching barrier mask. The third mask pattern is removed. A spin-on-carbon layer over which the upper portion of the second mask pattern is exposed is coated over first and second mask patterns and the underlying layer. A part of the first pattern and the second mask pattern are removed by the spin-on-carbon material as an etching barrier mask to expose the underlying layer. The spin-on-carbon layer is removed until the underlying layer and a portion of the first mask film are exposed.

[0016] The step of partially etching-the-first-mask-film preferably includes forming first mask patterns whose lower portions are interconnected not to expose an underlying pattern.

[0017] The method of the present invention can comprise a photoresist etching barrier mask process step which is performed once to form the mask patterns, thereby simplifying the manufacturing cost and process steps to improve efficiency.

[0018] According to an embodiment of the present invention, the method can improve the overlay mis-alignment due to overlapping of photoresist patterns, thereby obtaining a pattern having a pitch that cannot be formed by current lithography equipment.

[0026] The present invention will be described in detail with reference to the accompanying drawings.

[0027] In order to prevent the overlapping and mis-alignment, i) a double exposure etch technology (DEET) and ii) a spacer patterning technology (SPT) are developed, which have been used in a semiconductor device producing process.

[0028] The i) DEET comprises forming a first pattern having a line-width twice larger than that of a desired pattern, and forming a second pattern having the same line-width between the first patterns. More specifically, the DDET includes a) a positive method and b) a negative method.

[0029] As shown in FIG. 1, in the a) positive method, an underlying layer 3, a first mask film 5, a second mask film 7 and a first positive photoresist pattern 8 are formed over a semiconductor substrate 1. A second mask pattern 7-1 is formed with the first photoresist pattern 8 as an etching barrier mask. A second positive photoresist pattern 9 is formed between the second mask patterns 7-1. A first mask pattern 5-1 is formed with the second mask pattern 7-1 and the second photoresist pattern 9 as an etching barrier mask.

[0030] As shown in FIG. 2, in the b) negative method, an underlying layer 23, a first mask film 25, a second mask film 27 and a first negative photoresist pattern 28 are formed over a semiconductor substrate 21. A second mask pattern 27-1 is formed with the first negative photoresist pattern 28 as an etching barrier mask. A second negative photoresist pattern 29 is formed over the second mask pattern 27-1 and the first mask film 25. The second mask pattern 27-1 is etched with the second negative photoresist pattern 29 as an etching barrier mask to form a second mask pattern 27-2. The first mask film 25 is etched with the second mask pattern 27-2 as an etching barrier mask to form a first mask pattern 25-1.

[0031] Since the DEET uses two kinds of masks, it is possible to form a pattern having a desired pitch size. However, the process steps are complicated, and the manufacturing cost is increased. Moreover, when the second photoresist pattern is formed, mis-alignment occurs by inaccuracy in overlay of patterns.

[0032] The ii) SPT is a self-alignment technology to prevent mis-alignment by performing a mask process for forming a pattern in a cell region. The SPT includes a) a positive method and b) a negative method.

[0033] As shown in FIG. 3, in the a) positive method, an underlying layer 33, a first mask film 35, a second mask film 37 and a first photoresist pattern 38 are formed over a semiconductor substrate 31. A second mask pattern 37-1 is formed with the first photoresist pattern 38 as an etching barrier mask. A spacer 39 is formed at a sidewall of the second mask pattern 37-1. A first mask pattern 35-1 is formed with the spacer 39 as an etching barrier mask.

[0034] As shown in FIG. 4, the b) negative method includes forming an underling layer 43, a first mask film 45, a second mask film 47 and a first photoresist pattern 48 over a semiconductor substrate 41, and forming a second mask pattern 47-1 with the first photoresist pattern 48 as an etching barrier mask. A spacer 49 is formed at a sidewall of the second mask pattern 47-1. A spin-on-glass-film 50 or an anti-reflection film is coated over the resulting structure. A CMP or an etch-back method is performed to expose the second mask pattern 47-1 (not shown). The spacer is removed, and a first mask pattern 45-1 is formed with the second mask pattern 47-1 as an etching barrier mask.

[0035] The SPT requires an additional mask process in order to form a pattern in core and peripheral portions or isolate a pattern portion of a mini cell block region. As a result, the process steps are complicated. Also, it is difficult to regulate a line-width of the patterns when the spacer is formed, thereby degrading the uniformity of the pattern line-width.

[0036] FIGS. 5a through 5i are diagrams illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

[0037] FIG. 5a shows first to third mask films 113, 115, and 117 and an organic anti-reflection film 119, respectively which are deposited sequentially over an underlying layer 111.

[0038] In this embodiment, the underlying layer is a conductive layer including a gate oxide film, a polysilicon layer, a tungsten layer and an insulating film. The insulating film has a stacked structure including a poly layer and the insulating film.

[0039] In this embodiment, the first mask film 113 includes tungsten (W). In this embodiment, the second mask film 115 includes a nitride film (SiN), an oxide film (SiO), a silicon oxy-nitride film (SiON), and a stack layer including at least one or more films thereof. In this embodiment, the third mask film 117 includes an amorphous carbon layer or a stack layer including the amorphous carbon layer and a silicon oxy-nitride film.

[0040] Preferably the first and third mask films have a different etching selectivity ratio from that of the second mask film. Preferably, the first and third mask films have one or both of a lower etching selectivity ratio and a lower etching speed, than that of the second mask film, and also preferably to all kinds of etching gas. More specifically, the first mask film preferably includes a tungsten film, the second mask film preferably includes a nitride film, and the third mask film preferably includes a stack layer including an amorphous carbon layer and a silicon oxy-nitride film.

[0041] The tungsten film used as the first mask film can be removed while being used as an etching barrier mask during a subsequent etching process for forming gate pattern. As a result, it is unnecessary to perform an additional process for removing the tungsten film.

[0042] The third mask film preferably includes a multi mask film which can be formed by a spin-coating process and has an excellent planarization property instead of the stack layer including an amorphous carbon layer and a silicon oxy-nitride film. The multi mask film does not use a chemical vapor deposition method like the amorphous carbon layer, and the efficiency is excellent.

[0043] Any kinds of multi mask films can be used. The multi mask film can serve as a mask film for improving an etching selectivity ratio and as an anti-reflection film for increasing pattern uniformity in a general process of manufacturing a semiconductor device. A preferred multi mask film is formed in a first embodiment by i) a spin-on-carbon material where a carbon element is present in an amount in a range of 85 wt % to 90 wt % based on the total compound molecular weight, or in a second embodiment ii) a mask composition comprising Si compound where a Si element is present in an amount in a range of 30 wt % to 80 wt % by weight based on the total compound molecular weight. The second embodiment ii) Si compound can be a Si-containing polymer, an oligomer of the Si-containing polymer and a SOG material such as HSQ and MSQ. More specifically, the mask composition preferably comprises a Si-containing polymer in an amount in a range of 30 parts by weight to 70 parts by weight based on 100 parts by weight of the composition and a residual organic solvent as main components. The mask composition preferably further comprises a compound of Formula 1, Formula 2, a thermal acid generator or a photoacid generator.

[0044]
wherein R_a-R_d are each individually hydrogen or a substituted or unsubstituted linear or branched C₁-C₅ alkyl group, e is an integer in a range of 5 to 500, f is an integer in a range of 0 to 5, and g is an integer in a range of 1 to 5.

[0045] The molecular weight of the compound of Formula 1 preferably is in a range of 500 to 50,000.

[0046] The molecular weight of the Si-containing polymer preferably is in a range of 300 to 30,000. The Si-containing polymer preferably includes one or more base resin selected from compounds of Formula 3 to 5.

[0047]
wherein R₁ and R₂ are individually hydrogen or a substituted or unsubstituted linear or branched C₁-C₅ alkyl group, and m, n and o are each independently an integer in a range from 1 to 10.

[0048]
wherein R₃ is a hydrogen, a substituted or unsubstituted linear or branched C₁-C₅ alkyl group, a substituted or unsubstituted C₃-C₈ cyclo-alkyl group, or a substituted or unsubstituted C₅-C₁₂ aromatic group, and x and y each independently are an integer in a range of 0 to 5.

[0049]
wherein R₁₀ is (CH₂)_kSi(OR′)₃, R′ is a hydrogen or a linear or branched C₁-C₁₀ alkyl, and k is an integer in a range of 1 to 10.

[0050] The spin-on-carbon material for the multi mask film preferably includes SHN18 of Nissan Chemical Co., or the Si compound for the multi mask film preferably includes MHNO4 of Nissan Chemical Co.

[0051] FIG. 5b shows a photoresist pattern 121 formed over the organic anti-reflection film 119 which is the top layer.

[0052] A photoresist film (not shown) is coated over the organic anti-reflection film, and a photolithography process is performed on the photoresist film to obtain the photoresist pattern 121. The pitch of the photoresist pattern 121 preferably is twice as large as that of the design rule. Preferably, the ratio of line-width of the photoresist pattern to interval between patterns is 3:1.

[0053] FIG. 5c shows a third mask pattern 117-1 and the organic anti-reflection pattern 119-1 formed with the photoresist pattern 121 as an etching barrier mask.

[0054] FIG. 5d shows a second mask pattern 115-1 and a first mask pattern 113-1 which include an open part to expose the underlying layer 111 formed with the third mask pattern 117-1 and the organic anti-reflection pattern 119-1 as an etching barrier mask (see FIG. 6a, which shows an embodiment of the invention wherein the first mask pattern 113-1 is a tungsten layer, the second mask pattern 115-1 includes a deposition mask nitride film (HM Nit) including a nitride film (SiN) and a silicon oxy-nitride film (SiON) stack layer, and the third mask pattern 117-1 is an amorphous carbon (A-C) layer).

[0055] The etching process is performed to pattern the first and second mask films (113 and 115, respectively) until the underlying layer 111 is exposed with the third mask pattern 117-1 as an etching barrier mask. A partial etching process is performed on a top portion of the first mask film 113 not to expose the underlying layer, thereby forming a first mask pattern (not shown) whose bottom portion is connected. When the first mask pattern is formed whose bottom portion is connected, the first mask film preferably includes a tungsten or poly layer.

[0056] FIG. 5e shows a resulting structure obtained by performing a trimming process with the third mask pattern 117-1 as an etching barrier mask.

[0057] The trimming etching process is performed to regulate the pattern line-width uniformly in a logic process. The trimming etching process over-etches a lower material with an upper material as an etching barrier mask to adjust the line-width of the lower material. Here, the etching selectivity ratio of the lower material is not the same as an upper material. The trimming etching process is not performed in a conventional DRAM process.

[0058] The trimming etching process is performed with a large etching selectivity ratio difference of both the first and third mask films with the second mask film so that the sidewall of the second mask film can be etched uniformly without loss of the first and third mask films. That is, in the trimming etching process, the second mask film 115 has a higher etching speed than that of the first mask film 113 and also a higher etching speed than that of the third mask film 117 for a selected etching gas. As a result, the sidewall of the second mask pattern 115-1 is first etched and removed in the trimming etching process.

[0059] The trimming etching process preferably is performed with fluoro hydrocarbon gas (ex. CHxFy, here x and y are an integer ranging from 1 to 10) as a passivation etching gas to the tungsten and preferably with SF₆ gas to etch the nitride film. More preferably, the trimming etching process is performed with the etching gas having a flow ratio of CHF₃ gas:SF₆ gas=2-10:1, preferably, 4-5:1.

[0060] The trimming etching process is performed until line-width of the second mask pattern 115-2 i) has the same size as a interval between the photoresist patterns, or ii) is reduced by about 20-50% of the line-width size of the second mask pattern 115-1 before the trimming etching process is performed (see FIG. 6b, which shows the second mask pattern reduced line-width size by about 20-50% after the trimming etching process is performed). The third mask pattern 117-1 is not damaged by the etching gas. Moreover, since the first mask pattern 113-1 whose bottom portion is connected (not shown) is formed by a partial etching process, although the underlying layer 111 is formed by an insulating film, the first mask pattern 113-1 which remains over the underlying layer serves as a barrier film to prevent the underlying layer 111 from being damaged by the etching gas.

[0061] Referring to FIG. 5f, an O₂ ashing process is performed on the resulting structure to remove the residual third mask pattern 117-1.

[0062] A spin-on-carbon layer 123 is formed over the resulting structure. The spin-on-carbon layer preferably has a carbon element content present in an amount in a range of 85 wt % to 90 wt % based on the total molecular weight. Like the third mask film, SHN18 of Nissan Chemical Co. can be used.

[0063] FIG. 5g shows a resulting structure where a top portion of the second mask pattern 115-2 is exposed by an etch-back process performed on the spin-on-carbon layer 123.

[0064] The etch-back process preferably is performed with an etching gas selected from oxygen, nitrogen, hydrogen and combination thereof.

[0065] In order to perform subsequent etching process in stable condition, the spin-on-carbon layer preferably is etched not to expose the first mask film pattern 113-1 disposed outside the bottom of the second mask pattern 115-2.

[0066] Referring to FIG. 5h, the exposed second mask pattern 115-2 and a part of the first mask pattern 113-1 situated under the exposed second mask pattern is removed with the spin-on-carbon layer 123 as an etching barrier mask to expose the underlying layer 111. As a result, a first mask pattern 113-2 including an open part 125 is formed.

[0067] The etching process preferably is performed with an etching gas for nitride or tungsten such as SF₆, O₂, N₂, Ar and combinations thereof.

[0068] The line-width of the first mask pattern 113-2 preferably is reduced to a size smaller than that of the first mask pattern 113-1 by about ⅓. When a developing inspection critical dimension (DICD) is transcribed as it is, the first mask pattern has the same size as a gap between the photoresist patterns. For example, when an etching bias is 80 nm and a design rule is a 40 nm device, the ratio of line-width of the first mask pattern to gap between first mask patterns is 1:1.

[0069] Referring to FIG. 5i, an O₂ ashing process is performed on the resulting structure to remove the spin-on-carbon layer 123.

[0070] When the bottom portion of the first mask pattern 113-1 is interconnected, the over ashing process is performed on the interconnection part of the first mask pattern 113-1 to expose the underlying layer, thereby obtaining a uniform fine pattern.

[0071] A lower conductive layer (not shown) is etched with the first mask pattern 113-2 as an etching barrier mask to form a conductive pattern. The conductive pattern can include a gate line, a bit line and a metal line. An additional mask process preferably is performed to form a pattern in core and peripheral parts except the cell region.

[0072] With an exposure mask pattern having a pitch twice as large as the design rule, a pattern having a reduced pitch can be formed. In comparison with a conventional double patterning technology using two masks, a self-aligned pattern can be obtained without overlay mis-alignment.

[0073] As described above, according to an embodiment of the present invention, a trimming process is performed to reduce a line-width of a mask pattern formed over an underlying layer. A spin-on-carbon material is coated over the resulting structure. A mask pattern is etched with the spin-on-carbon layer as an etching barrier mask to simplify process steps and obtain a fine pattern having a uniform line-width regardless of overlay accuracy of an exposer.

[0074] The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the lithography steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications will be obvious to a person of ordinary skill in the art in view of the present disclosure, and are intended to fall within the scope of the appended claims.