Recessed gate for a CMOS image sensor

[0001] This application is a divisional of U.S. application Ser. No. 10/905,097, filed Dec. 15, 2004.

[0002] The present invention related generally to the fabrication of semiconductor pixel imager arrays, and more particularly, to a novel Active Pixel Sensor (APS) cell structure including a novel transfer gate and process therefore.

[0003] CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pickup such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.

[0004] Current CMOS image sensors comprise an array of CMOS Active Pixel Sensor (APS) cells, which are used to collect light energy and convert it into readable electrical signals. Each APS cell comprises a photosensitive element, such as a photodiode, photo gate, or photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in an underlying portion thereof. A read-out circuit is connected to each pixel cell and often includes a diffusion region for receiving charge from the photosensitive element, when read-out. Typically, this is accomplished by a transistor device having a gate electrically connected to the floating diffusion region. The imager may also include a transistor, having a transfer gate, for transferring charge from the photosensitive element to the floating diffusion region, and a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transfer.

[0005] As shown in FIG. 1, a typical CMOS APS cell 10 includes a pinned photodiode 20 having a pinning layer 18 doped p-type and, an underlying lightly doped n−type region 17. Typically, the pinned diode 20 is formed on top of a p-type substrate 15 or a p-type epitaxial layer or p-well surface layer having a lower p-type concentration than the diode pinning layer 18. The n-region 17 and p region 18 of the photodiode 20 are typically spaced between an isolation region (not shown) and a charge transfer transistor gate 25 which are surrounded by thin spacer structures 23a,b. The photodiode 20 thus has two p-type regions 18 and 15 having a same potential so that the n-region 17 is fully depleted at a pinning voltage (Vp). The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value, Vp, when the photodiode is fully depleted. In operation, light coming from the pixel is focused down onto the photodiode through the diode where electrons collect at the n−type region 17. When the transfer gate 25 is operated, i.e., turned on, the photo-generated charge 24 is transferred from the charge accumulating doped n⁻ type region 17 via a transfer device surface channel 16 to a floating diffusion region 30 which is doped n+ type.

[0006] A first problem with these current CMOS Imaging cells with a charge transfer gate 25 (e.g., a “4” Transistor cell) is the definitional problem of controlling the readout of the charge. The p type surface pinning layer 18 is necessary for low dark current, but can create a potential barrier between the n− type charge collection well 17 and the transfer device channel 16. The structure as currently practiced by the industry is also very sensitive to normal manufacturing process variations. Overlay and image size variation of the block masks is critical for cell operation.

[0007] For example, in conventional processes for fabricating the pinning layer 18 over the photodiode in the prior art APS cell 10 shown in FIG. 1, it is the case that some amount of p doping 29 overlaps onto the transfer gate 25 which is normally formed of intrinsic polysilicon or low level p-type doped 27. This is a result of mask overlay tolerance or displacement of the mask edge during fabrication. Subsequently, during formation of the n+ type doped floating diffusion region 30, the gate is processed to include a n+ type doped region 28. The presence of this p doping has an effect of reducing the efficiency and dynamic range of the gate, particularly by causing variations in transfer gate voltage thresholds (V_t). This will cause the transfer gate to not turn on completely. Also, because of lithographic alignment issues, the position of the p ‘overlap’ onto the gate varies, leading to performance variability.

[0008] A second problem is that the transfer gate structure 25 as defined takes up a lot of space in the cell leading to lower cell fill factor (the percentage of the cell that functions as a light collection area). One of the reasons for this is that there are multiple block levels whose overlay and image size goes into the minimum transfer gate length. If the n+ type floating diffusion region 30 is implanted on the collection side of the transfer gate, it will create excess leakage. If the p type surface pinning layer is implanted on the drain side of the gate, it will create a series resistance for the device. Both of these layers must abut the transfer gate on one side. The n−type charge collection layer 17 must somewhat overlap the gate or there will be a large potential barrier to charge transfer, but if it overlaps too much, the device will suffer from short channel effects.

[0009] Variation in the concentration distribution of the impurity dopant in the n−type collection well region 17, along with alignment, may cause both variation in the properties of the photodiode as well as create a potential barrier to occur immediately under the gate electrode. This effects the charge transfer efficiency of the transfer MOS transistor which in turn may degrade performance of the CMOS image sensor. Prior art teaches the use of oblique-rotating implantation or the use of excessive thermal diffusion to position or move the dopant under the gate structure 25 to minimize the potential barrier. U.S. Pat. No. 6,660,553 describes a method whereby an implant mask is used to form a photodiode which is partly situated under the gate.

[0010] Structures and methods that minimize the potential barrier and the parametric variability of the transfer gate are of great value for CMOS sensors.

[0011] It would thus be highly desirable to provide a novel CMOS image sensor APS cell structure and method of manufacture whereby the transfer gate is recessed such that the charge collection well intersects the bottom of the transfer gate channel.

[0012] This invention addresses a novel CMOS image sensor APS cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a recessed transfer gate is fabricated such that the charge collection well intersects the bottom of the transfer gate channel.

[0013] According to the embodiment of the invention, the CMOS image sensor APS cell structure includes a doped p pinning layer and an N+ doped gate. There is additionally provided a method of forming the CMOS image sensor APS cell having a transfer gate that is recessed such that the transfer channel intersects the collection well. This improves the control of the readout of the charge of the imaging cell as the pinning layer no longer has the ability to produce a potential barrier to charge transfer. By recessing the transfer gate, not only is the pinning layer out of the way of charge transfer, but now the transfer device characteristics are not sensitive to the alignment overlay of the block levels.

[0014] According to a first aspect of the invention, there is provided a CMOS optical imaging sensor comprising: a substrate having an upper surface; a gate conductor having at least a portion recessed below the upper substrate surface; a collection well region formed adjacent a first side of the gate conductor and a diffusion region formed adjacent a second side of the gate conductor. The imaging sensor further comprises a pinning layer formed on an upper surface of the collection well. At least one portion of the gate conductor is recessed below the pinning layer. Moreover, the imaging sensor collection well intersects a channel region formed by the gate conductor. Recessing the transfer gate relieves the problem as the surface pinning layer no longer produces a potential barrier to charge transfer. By recessing the transfer gate, not only is the pinning layer out of the way of charge transfer, but now the transfer device characteristics are not sensitive to the alignment overlay of the block levels.

[0015] According to a second aspect of the invention, there is provided a method for fabricating an active pixel sensor (APS) cell structure for a CMOS imager comprising the steps of: etching a trench into a semiconductor substrate to define a recessed portion of an image cell transfer gate below a substrate surface; forming a layer of dielectric material over the semiconductor substrate and including the recessed portion; filling tie recessed portion with polysilicon material atop the dielectric material layer and forming a polysilicon gate layer above the substrate surface; etching the polysilicon gate layer to define a portion of the image cell transfer gate above the substrate surface; forming a doped pinning layer comprising material of a first conductivity type in the substrate at a first side of the transfer gate; forming a doped collection well layer comprising material of a second conductivity type beneath the doped pinning layer; and, forming a doped diffusion layer of a second conductivity type in the substrate at an opposite side of the predoped transfer gate, the recessed portion of the image cell transfer gate forming a channel region enabling charge transfer between the collection well layer and the diffusion region, wherein the recessed portion of an image cell transfer gate extends to a depth below the pinning layer. Preferably, the recessed portion of the image cell transfer gate extends to a depth below the formed doped collection well layer such that the doped collection well layer intersects the channel region to thereby eliminate any potential barrier interference to charge transfer caused by the formed pinning layer.

[0016] Advantageously, the design of the recessed transfer gate allows the design of a much smaller cell, or at least a cell with smaller transfer gate area and thus higher fill factor.

[0026] FIG. 2 illustrates the CMOS image sensor APS cell 100 of the present invention. As shown in FIG. 2, the APS cell 100 includes a transfer gate 125 formed on top of a gate dielectric material layer 35 which is formed on top of a semiconductor substrate 15 having a recessed portion 127 formed below the substrate surface. Abutting one side of the transfer gate is a photodiode 200 comprising a surface pinning layer 180 doped with material of a first conductivity, e.g., p type material dopant, and an charge collection well 170 doped with material of a second conductivity, e.g., n type material dopant, formed directly underneath the pinning layer.

[0027] Abutting the other side of the transfer gate is a gate diffusion region 130 comprising doped with material of a second conductivity, e.g., n type material dopant. As shown in FIG. 2, the transfer gate channel 160 fanned underneath the transfer gate 125 intersects a portion 172 of the subsequently formed abutting charge collection well region 170. The recessed transfer gate 125 helps overcome the limitations of the prior art APS cell structure as the surface pinning layer 180 no longer has the ability to produce a potential barrier to charge transfer. By recessing the transfer gate, the pinning layer 180 does not affect charge transfer as it no longer intersects the path 124 of charge transfer, but additionally renders the transfer device characteristics not sensitive to the alignment overlay of the block levels. The charge collection well 170 is thus formed to intersect the bottom of the transfer gate channel 160. Thus, there is no potential barrier interference from the pinning layer 180.

[0028] The method to create a recessed transfer gate 125 is now described. As shown in FIG. 3(a), there is provided a substrate 15 which may be a bulk semiconductor including, for example, Si, SiGe, SiC, SiGeC, GaAs, InP, InAs and other semiconductors, or layered semiconductors such as silicon-on-insulators (SOI), SiC-on-insulator (SiCOI) or silicon germanium-on-insulators (SGOI). For purposes of description, substrate 15 is a Si-containing semiconductor substrate of a first conductivity type, e.g., lightly doped with p-type dopant material such as boron or indium (beryllium or magnesium for a III-V semiconductor), to a standard concentration ranging between, e.g., 1e¹⁴ to 1e¹⁶ cm⁻³. Next, using standard processing techniques, a trench recess is formed in the substrate. That is, utilizing a trench lithography, a photoresist mask (not shown) is applied, patterned and developed to expose an open region for forming a trench etch. Subsequently, an etch process is performed through the opening in the mask to form a trench recess 116 that extends down below the substrate surface to a depth of about 0.1 μm to 1 μm or, at least to a depth such that a subsequently formed collection well intersects the bottom of the channel region so that potential barrier interference from the pinning layer is eliminated. Preferably, the trench recess 116 formed according to this process has a width less than about the typical 0.4-0.9 μm transfer gate features present in 0.18 micron technology node processing.

[0029] Subsequent to the formation of the trench 116, a dielectric material layer 35 is formed by standard deposition or growth techniques atop the substrate 15 that will form the eventual transfer gate dielectric. The dielectric layer is typically formed to a thickness ranging between 35 Å to 100 Å and may comprise suitable gate dielectric materials including but not limited to: an oxide (e.g., SiO₂), a nitride (e.g., silicon nitride) an oxynitride (e.g., Si oxynitride), N₂O, NO, ZrO₂, or other like materials. The dielectric layer 35 is formed on the surface of the Si-containing semiconductor substrate 15 and on the sidewalls and bottom surface of trench 116 using conventional thermal oxidation or by a suitable deposition process such as chemical vapor deposition, plasma-assisted chemical vapor deposition, evaporation, sputtering and other like deposition processes. Although it is not shown, it is understood that the dielectric layer may comprise a stack of dielectric materials.

[0030] Next, a gate layer 50, is deposited to fill the trench 116 and form a layer above the gate dielectric layer 35 using conventional deposition processes including, but not limited to: CVD, plasma-assisted CVD, sputtering, plating, evaporation and other like deposition processes (e.g., a low pressure CVD). This layer may be comprised of any conductor including metals, silicides, or polysilicon. For purposes of description, an intrinsic polysilicon layer is used. The intrinsic polysilicon layer structure formed atop the dielectric layer surface to a thickness ranging between about 1 k Å to 2 k Å however, may be outside this range. It is understood that for proper operation polysilicon gate, layer 50, must be doped with the second conductivity type, e.g. n−type, to a concentration in the range of 1e¹⁸ cm⁻³ to 1e¹⁹ cm⁻³. This maybe accomplished by the standard practice of utilizing the source/drain implants or by predoping the polysilicon before etch, or by using insitu doped polysilicon.

[0031] Regardless of whether or not the formed gate polysilicon layer 50 is doped, e.g., subsequently by ion implantation or, in-situ doped and deposited, the transfer gate is then formed to result in the structure shown in FIG. 3(c), whereby a photo lithographic process is used to define the gate region. This step is not illustrated since there are many different ways how the lateral size and shape of tie gate can be defined. Typically, an etch window is provided in a resist mask (not shown), and one or more etch processes are performed, e.g., a reactive ion etch process, that is optimized to ensure proper etching of the doped polysilicon layer 50 and dielectric layer 35 or dielectric layer stack. Chemical Mechanical Polish techniques can also be used to define the gate, and may be the preferred method when using metal gates. The resulting structure of the transfer gate 125 polysilicon layer 50 is shown in FIG. 2 which illustrates the width of the formed transfer gate poly region above the substrate surface to be slightly wider than the width of the trench portion 127 of the transfer gate trench.

[0032] In a further step (not shown), gate sidewall spacers 23a,b are formed at either side of the transfer gate by conventional deposition processes well known in the art, and may comprise any conventional oxide or nitride (e.g., Si₃N₄) or oxide/nitride and then they are etched by RIE or another like etch process. The thickness of spacers 23a,b may vary, but typically they have a thickness of from about 10 nm to about 150 nm. The photodiode pinning region is typically created after forming spacers in a further step (not shown). It may also be created at other points in the process. This step comprises applying a photoresist layer patterning, and etching an ion implantation mask according to techniques known in the art to form a mask edge approximately coincident with the gate edge or as close as possible given alignment tolerances, to provide an opening to an area between an edge of the gate and a formed isolation region, e.g., STI region (not shown), where the charge accumulation region of tie photodiode is to be formed. This opening permits the implantation of ions of p-type dopant material such as boron at a concentration sufficient to form the p-type dopant regions as shown in FIG. 2 up to the edge of the spacer 23a. The active p-type dopant material is ion implanted at dosing concentrations ranging between 1e¹⁷ cm⁻³ and 1e¹⁹ cm⁻³.

[0033] Although not shown, a farther step is to ion implant the n−type doping region of the photodiode. Thus, using the same ion implantation mask as in the previous step, an ion implantation process is performed to implant dopant material of the second conductivity type, e.g., n−type dopant material, such as phosphorus, arsenic or antimony, to form the charge collection layer beneath the ion implanted p type pinning layer 180. The n−type dopant material is implanted at higher energy levels to form the n−type doped region 170 of the photodiode 100 as shown in the figures. The active n−type dopant material is ion implanted at dosing concentrations ranging between 1e¹⁶ cm⁻³ and 1e¹⁸ cm⁻³. Although not shown, the photosensitive charge storage region 170 for collecting photo-generated electrons may be formed by multiple implants to tailor the profile of the n−type region 170. It is understood that an implantation angled relative to the gate surface may be conducted to form the p pinning layer 180 and n−type region 170. It should be understood that, alternatively, the p pinning photodiode surface layer 180 may be formed by other known techniques and may be formed subsequent to or before forming the n charge collection layer. For example, the p surface layer 180 may be formed by a gas source plasma doping process, or by diffusing a p-type dopant from the in-situ doped layer or a doped oxide layer deposited over the area where photodiode 200 is to be formed.

[0034] In addition to the forming of the photodiode 200, an additional step of forming an n−type floating diffusion region at the other side of the transfer gate is performed. This step comprises forming a photoresist layer and patterning and etching an ion implantation mask according to techniques known in the art to form a mask edge approximately coincident with the gate edge or as close as possible given alignment tolerances, to provide an opening allowing the implantation of n−type dopant material, such as phosphorus, arsenic or antimony, at a concentration sufficient to form the n+-type doped floating diffusion region 130 as shown in the figures up to the edge of the spacer 23b as shown in the structure depicted in FIG. 2. The active n+-type dopant material is ion implanted at the floating diffusion region at dosing concentrations ranging between 1e¹⁸ cm⁻³ and 1e²⁰ cm⁻³.

[0035] There are several alternate embodiments to this invention that can add value to the basic idea shown and described with respect to FIG. 2. For instance, it should be understood that the present invention contemplates transfer gate recessed portions formation of varying shapes and sizes by a variety of known techniques. That is, the depth of the transfer gate is variable and, the width of the transfer gate with respect to the recess trench is variable. For example, in a first alternate embodiment, as shown in FIG. 4, a transfer gate 225 may be fabricated that includes a trench 227 etched significantly deeper than the transfer gate etch depth 116 according to the first embodiment (See FIG. 3(b)). That is, as shown in the first embodiment, the transfer gate etch depth 116 is required to be only slightly deeper than the p doped surface pinning layer 180 (which is typically about 0.1 μm deep). However, it may be beneficial to make the recess quite deep, e.g., to a depth ranging between about 0.3-1.0 μm with a preferred depth of about 0.5 μm-0.6 μm. If the recess is deeper than the n−type charge collection layer 170, then the resulting transfer gate channel length is independent of the overlay of the n charge collection well to the transfer gate. This may also help scaling by allowing a narrower transfer gate width since the total channel length will still be long. In a second alternate embodiment, as shown in FIG. 5, a transfer gate 325 may be fabricated that includes a “V” shaped trench recess portion 327 which, as known to skilled artisans, may be created by implementing a substrate wet etch process, e.g., that will stop on the <111> crystallographic plane which will provide about a 54.7 degree angle between the sidewall angle of the “V” and the surface, to form the “V” shaped trench recess which may be beneficial for surface state reduction as known in the art. In a further alternate embodiment, as shown in FIG. 6, a transfer gate 425 may be fabricated that is equal in width or narrower than the recess trench portion 427. In a further alternate embodiment, as shown in FIG. 7, a transfer gate 525 maybe fabricated that includes an extended gate portion 526 overlapping the recess on the photodiode collection side. This is different than the first embodiment depicted in FIG. 2 wherein the transfer gate width is wider than the recess and overlaps on both sides of the gate. That is, as shown in FIG. 7, the transfer gate overlaps with the recess on the photodiode collection side.

[0036] It is understood that, if the transfer gate is designed to be deep, the cell can be scaled aggressively. In the traditional cell layout, the p type surface pinning layer 180, the n−type charge collection well 170, and the n+ type diffusion region 130 all need to be lithographically aligned so that they do not cross the gate. This requirement forces a long transfer gate length. With a deep recess, however, all of these overlay tolerances can be eliminated by proper design. That is, the n−type charge collection well 170 would need to be designed to intentionally cross the transfer gate and would form the connection to the n+ drain contact. Overlay of this well 170 to the gate edge would not be critical. Further, although not shown, the p type surface pinning layer 180 may be formed to cross the transfer gate since it is no longer in tie conducting path. The n+ diffusion region 130 would not be allowed to cross the gate, but because of the charge collection well 170, it would not need to abut the gate. The combination of these features allows for a much smaller cell such as shown in the further alternate embodiment as shown in FIG. 8, which depicts an APS cell including a transfer gate 625 having a smaller width than the previous embodiments, and, a deeper recessed gate portion 627 as the technology permits between about 0.3-1.0 μm. As further shown in FIG. 8, the n−type charge collection well 170 includes a region 172 intentionally crossing over the transfer gate 627 and forms a connection to the n+ type doped diffusion region 130, e.g., a drain contact.

[0037] While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.