NAND system with a data write frequency greater than a command-and-address-load frequency

[0001] The present invention relates generally to NAND memory systems and in particular the present invention relates to a NAND system with a data write frequency greater than a command-and-address-load frequency.

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones and removable memory modules.

[0004] A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a column bit line.

[0005] The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.

[0006] A NAND flash memory device receives a command, addresses, and data sequentially over a common multiplexed input/output bus and outputs data over the common multiplexed input/output bus. The memory device also receives a single clock signal for timing or synchronizing the command and the address input and the data input. The command, portions of a column address, portions of a row address, and portions of the input data are received at a frequency of the single clock signal. The frequency of the clock signal has been chosen based on a maximum time required by the memory device to receive any one of the command, address, or data components.

[0007] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative timing schemes in memory devices.

[0008] The above-mentioned problems with timing schemes in memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

[0009] For one embodiment, the invention provides a method of operating a NAND flash memory device that includes receiving command and address signals at a first frequency, and receiving a data signal at a second frequency that is greater than the first frequency.

[0010] Further embodiments of the invention include methods and apparatus of varying scope.

[0013] In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

[0014] FIG. 1 is a simplified block diagram of a NAND flash memory device 100 coupled to a processor 130 as part of an electronic system, according to an embodiment of the invention. The processor 130 may be a memory controller or other external host device. Memory device 100 includes an array of memory cells 104 arranged in rows and columns. A row decoder 108 and a column decoder 110 are provided to decode address signals. Address signals are received and decoded to access memory array 104. Memory device 100 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 100 as well as output of data and status information from the memory device 100. An address register 114 is coupled between I/O control circuitry 112 and row decoder 108 and column decoder 110 to latch the address signals prior to decoding. A command register 124 is coupled between I/O control circuitry 112 and control logic 116 to latch incoming commands. Control logic 116 controls access to the memory array 104 in response to the commands and generates status information for the external processor 130. The control logic 116 is coupled to row decoder 108 and column decoder 110 to control the row decoder 108 and column decoder 110 in response to the addresses. Control logic 116 is also coupled to a cache register 118. Cache register 118 latches data, either incoming or outgoing, as directed by control logic 116 to temporarily store data while the memory array 104 is busy writing or reading, respectively, other data. During a write operation, data is passed from the cache register 118 to data register 120 for transfer to the memory array 104; then new data is latched in the cache register 118 from the I/O control circuitry 112. During a read operation, data is passed from the cache register 118 to the I/O control circuitry 112 for output to the external processor 130; then new data is pass from the data register 120 to the cache register 118. A status register 122 is coupled between I/O control circuitry 112 and control logic 116 to latch the status information for output to the processor 130.

[0015] Memory device 100 receives control signals at control logic 116 from processor 130 over a control link 132. The control signals may include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, and a write enable WE# in accordance with the present invention. Memory device 100 receives command signals (or commands), address signals (or addresses), and data signals (or data) from processor 130 over a multiplexed input/output (I/O) bus 134 and outputs data to processor 130 over I/O bus 134.

[0016] Specifically, the commands are received over input/output (I/O) pins [0:7] of I/O bus 134 at I/O control circuitry 112 and are written into command register 124. The addresses are received over input/output (I/O) pins [0:7] of bus 134 at I/O control circuitry 112 and are written into address register 114. The data are received over input/output (I/O) pins [0:7] for an 8-bit device or input/output (I/O) pins [0:15] for a 16-bit device at I/O control circuitry 112 and are written into cache register 118. The data are subsequently written into data register 120 for programming memory array 104. For another embodiment, cache register 118 may be omitted, and the data are written directly into data register 120. Data are also output over input/output (I/O) pins [0:7] for an 8-bit device or input/output (I/O) pins [0:15] for a 16-bit device. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 1 has been simplified to help focus on the invention. Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins may be used in the various embodiments.

[0017] FIG. 2 is a timing diagram for a command-and-address load and a data load (or write), according to another embodiment of the invention. Note that the write enable WE# control signal functions as a clock signal for timing the sequential receipt, over I/O bus 134, at memory device 100 of a command COM, portions of a first address, such as portions CA of a starting column address, portions of a second address, such as portions RA of a starting row address, and data portions D. For one embodiment, processor 130 includes a clock-and-control circuit 140 (FIG. 1) for generating and controlling the write enable WE#. That is, clock-and-control circuit 140 modifies the write enable WE# according to whether a command, an address, or data is being sent from processor 130 to memory device 100. For example, clock-and-control circuit 140 increases the frequency of write enable WE# in response to processor 130 sending data to memory device 100, so that the data is loaded at a higher frequency than the command or address.

[0018] The command COM is loaded into command register 124, the starting column and row addresses into address register 114, and the data into cache register 118 or directly into data register 120. Note that the portions CA of a starting column address constitute the starting column address, and portions RA of the starting row address constitute the starting row address. A first portion RA of the starting row address is loaded once the starting column address has been completely loaded. The column and row addresses are respectively latched to column decoder 110 and row decoder 108 (FIG. 1) for decoding.

[0019] The command COM and the portions CA of the starting column addresses, and the portions RA of the starting row address are loaded in succession and are respectively loaded during a command-and-address cycle time t_WC of a command-and-address load portion of the write enable WE#. For one embodiment, the command-and-address cycle time t_WC starts at a rising clock edge of the command-and-address load portion of the write enable WE# and ends at a successively immediately following rising clock edge of the command-and-address load portion of the write enable WE#, as shown in FIG. 2.

[0020] Specifically, the command COM is loaded into command register 124 (FIG. 1) on a rising clock edge of the command-and-address load portion of the write enable WE# when the chip enable CE# and the address latch enable ALE are low and the command latch enable CLE is high, as shown in FIG. 2. The portions CA of the column address and the portions RA the row address are loaded into address register 114 (FIG. 1) on a rising clock edge of the command-and-address load portion of the write enable WE# when the chip enable CE# and the command latch enable CLE are low and the address latch enable ALE is high, as shown in FIG. 2.

[0021] A first portion CA of the column address is loaded at the rising clock edge of the command-and-address load portion of the write enable WE# immediately following the rising clock edge of the command-and-address load portion of the write enable WE# at which the command COM was loaded. A first portion RA of the row address is loaded at the rising clock edge of the command-and-address load portion of the write enable WE# immediately following the rising clock edge of the command-and-address load portion of the write enable WE# at which the last portion CA of the column address was loaded.

[0022] The data are loaded during a data-load cycle time t_WCD of a data-load portion of the write enable WE#. For one embodiment, the data-load cycle time t_WCD of the data-load portion of the write enable WE# starts at a rising clock edge of the data-load portion of the write enable WE# and ends at an immediately following rising clock edge of the data-load portion of the write enable WE#, as shown in FIG. 2. For another embodiment, the data-load portion of the write enable WE#, and thus data loading, starts after a delay time t_ADL that starts at the last rising clock edge of the command-and-address load portion of the write enable WE#, i.e., corresponding to the loading of the last portion RA of the row address. For another embodiment, the address latch enable ALE transitions low during delay time t_ADL, while the chip enable CE# and the command latch enable CLE remain low. Therefore, data are loaded at immediately successive rising clock edges of the data-load portion of the write enable WE# when the address latch enable ALE, the chip enable CE#, and the command latch enable CLE are low.

[0023] Note that data-load cycle time t_WCD of a data-load portion of the write enable WE# is shorter than the command-and-address cycle time t_WC of the command-and-address load portion of the write enable WE#. Therefore, the frequency of the data-load portion of the write enable WE# is greater than the command-and-address load portion of the write enable WE#. For one embodiment, the frequency of the data-load portion may be about a factor of two greater than the frequency of the command-and-address load portion dependent upon the capability of the memory device. This allows for faster data loading and releases the write enable WE# sooner for other operations. For one embodiment, processor may use a clock divider that divides the period of the command-and-address load portion of the write enable WE# to obtain the data-load portion of the write enable WE#.

[0024] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.