Method and device for acquiring weak global navigation satellite system (GNSS) signals

[0001] The present invention relates generally to devices and methods for acquiring radio signals of very low power level and extracting time, frequency and other parameters therefrom. In particular, it relates to such devices and methods related to direct sequence spread spectrum (DS/SS) signals such as those used in the Global Navigation Satellite System (GNSS).

[0002] The Global Navigation Satellite System (GNSS) under construction encompasses the U.S. Global Positioning System (GPS), the Russian Global Navigation Satellite System (GLONASS) and the future European GALILEO System. The GPS has a constellation of twenty four satellites that are in six different orbit plans around the earth. A navigation solution is obtained through measuring propagation delay times of the radio signals broadcast by the orbiting satellites to a GPS receiver. Normally, a receiver must acquire signals from at least four satellites in order to solve for the variables of longitude, latitude, altitude and time that are needed to precisely determine location. The received GPS signals must attain a minimum power level to ensure a GPS solution, which is routinely met when there is a clear line-of-sight (LOS) view from the receiver antenna to GPS satellites above the horizon.

[0003] Each GPS satellite transmits signals at several frequencies including 1575.42 MHz (referred to as L1), 1227.60 MHz (L2) and soon 1176.45 MHz (L5). Each carrier signal is phase-modulated with at least one pseudo random number (PRN) code, which is also known as the spectrum spreading code, and some signals are further modulated with a navigation data message that provides the precise satellite orbital, clock, and other information. Each spectrum-spreading code is unique for a satellite and is used as the identifier for that satellite. At the receiver, successful correlation between the incoming signal and a locally generated reference code identifies which GPS satellite signal is being received. This also removes the spectrum-spreading code and this despreading process increases the signal to noise ratio (SNR) and allows the navigation data bits to be demodulated. Decoding of PRN codes and navigation data bits provides the exact knowledge of the GPS satellite orbital position and the time at which the received signal was transmitted (a transmission time tag). Each GPS receiver has its own local clock used to mark the time at which the signal was received (a reception time tag). The difference between the two time tags is a measurement of the signal propagation time. The range to each satellite is then calculated by multiplying each delay by the speed of light. The location and time of the user are then found by solving known equations that incorporate the measured range (also called the pseudorange due to timing errors involved in the measurement) to the known location of several GPS satellites.

[0004] However, when the line-of-sight view between the receiver and a satellite is obstructed (e.g., due to foliage, mountains, buildings, or other structures) the GPS signal strength may be severely attenuated, leading to position fix with poor accuracy and even breakdown of tracking loops inside a regular receiver. It is therefore desired to improve GPS receiver sensitivity to operate on GPS signals of very low power level (also referred to as weak signals) to satisfy the requirements of location-based mobile e-commerce and emergency call location (E911).

[0005] To enable weak GPS signal acquisition, one known technique at the receiver end is to extend the signal integration time. Coherent integration is more gainful than the non-coherent counterpart. However, when the coherent integration interval extends beyond, say, 20 milliseconds, which is the duration of one data bit for GPS C/A-code, the sign reversal of navigation data bits becomes destructive if it occurs in the middle of a long coherent integration. As a result, an additional signal parameter, namely, the data bit transition, has to be searched in addition to the two usual parameters, code phase (time) and carrier frequency, beside the ID number of GPS satellites. This in fact constitutes a four dimensional search.

[0006] With nominally twenty-four active GPS satellites in orbit, the maximum number of visible satellites is about ten for a near-Earth receiver. For GPS C/A-code, the amount of search in time (code phase) is actually fixed. With a search step of a half code chip, there are 2046 steps needed to cover the entire code sequence of 1023 chips. Sequential stepping through all the 2046 code phases, use of 2046 correlators in parallel, or a combination of sequential and parallel techniques are among a host of approaches of different complexity for code search and acquisition.

[0007] However, the amount of search in frequency and in data bit transition increases as the coherent integration prolongs. This can be seen from Eq. (1) below:
Δf≦½T_i  (1)
where T_i is the desired coherent integration time interval and Δf is the tolerable frequency error (thus the search step size) in order to keep the processing loss within an acceptable level. The frequency uncertainty for a stationary user (due to the relative motion between the user and a GPS satellite and the receiver local clock drift) is typically ±5 kHz. When the integration time is increased from the C/A-code epoch of 1 millisecond to, say, 20 milliseconds, the amount of frequency search needs to be increased by 20-fold according to Eq. (1). Similarly, the number of possible locations of data bit transition also increases proportionally as the coherent integration interval increases. There are also second-order effects associated with the extended coherent integration. This mainly involves changes in the carrier frequency and code chipping rate due to acceleration and instability of local clock, which may become significant over long integration intervals.

[0008] A typical search process is described below for a GPS receiver employing 1 millisecond correlation for the C/A-code using either sequential or parallel correlators. It involves search in four dimensions. The first search is to look for a visible GPS satellite among those active satellites in orbit. For a given satellite, parametric search is conducted in three nested loops. The outer parametric loop is typically the frequency search, which steps through the frequency uncertainty interval 500 Hz per step. The selected frequency offset (a frequency bin) is added to the nominal frequency to control the carrier numerically controlled oscillator (NCO) whose output drives the in-phase and quadrature components of the reference carrier for down-conversation to baseband.

[0009] The middle parametric loop is the code phase search over the entire code epoch of 1023 chips, a half chip per step (a code lag) typically. In a correlator-based receiver, the code phase search may be done sequentially one code phase at a time or in parallel with all code phases searched at the same time.

[0010] The inner loop accumulates the 1 millisecond correlations for each search grid point made of the frequency bin and code lag over a certain period of time (a dwell time), during which the signal is added up for detection. Under normal signal strength, the dwell time is usually chosen to be several milliseconds wherein the 1 millisecond correlations are power-combined (i.e., the non-coherent integration) with the navigation data bit transitions squared out, thus not being an issue. However, for weak GPS signals, the dwell time may extend beyond 20 milliseconds for coherent integration where the navigation data bit transition plays a critical role. It is the way in which coherent integration is carried out over an interval lasting multiple data bits that differentiates a weak signal acquisition (and tracking) scheme from that with normal signal strength.

[0011] For a search grid, the worst code uncertainty is a quarter of a chip duration (Δt=T_c/4) and the worst Doppler uncertainty is Δf=250 Hz. As a result, the maximum loss in a 1 millisecond coherent integration (T_i=1 millisecond) is

[0012] $\begin{array}{cc}\begin{array}{c}\mathrm{Loss}=20{\log }_{10}R\left(\Delta t\right)+20{\log }_{10}\left[\sin \left(\pi \Delta {\mathrm{fT}}_i\right)/\mathrm{\pi \Delta }{\mathrm{fT}}_i\right]\\ =20{\log }_{10}\left(0.75\right)+20{\log }_{10}\left(0.9\right)=-3.4\mathrm{dB}\end{array}& \left(2\right)\end{array}$
where R(·) stands for the correlation function with an ideally triangular shape.

[0013] For this worst search grid point, the correlator output is complex-valued. Since the spreading code is stripped off, the signal now contains a sine wave with its frequency being the residual Doppler up to 250 Hz that is bi-phase modulated by the unknown navigation data bit sequence at 50 Hz. However, the signal is too weak for the modulation to be visible at this point for it is deeply buried in noise.

[0014] To boost the SNR, coherent integration needs to last longer. When the despreading correlation is carried out every 1 millisecond, the complex correlation is available at the rate of 1 kHz. To further integrate, there will be twenty 1 millisecond correlations (20 data points) per a data bit. When coherent integration is beyond two data bits, the number of possible bit transitions is large and bit transition patterns become complicated.

[0015] There are, consequently, outstanding problems with known techniques for weak GPS signal acquisition and tracking in a standalone high-sensitivity receivers.

[0016] Another approach to acquiring weak GPS signals is assisted GPS (AGPS). The AGPS approach relies upon a wireless data link (or other means) to distribute, in real time, such information as time, frequency, navigation data bits, satellite ephemeredes, and approximate position as well as differential corrections to special GPS receivers equipped with a network modem so as to reduce the uncertainty search space, to help lock onto signals, and to assist navigation solution. This approach, however, comes with a heavy price associated with installing and maintaining the wireless aiding infrastructure and services required to provide the coverage.

[0017] A need therefore exists for weak GPS signal acquisition without network assistance. This need is met by the present invention as described and claimed below, which belongs to the category of approaches aimed at enhancing the sensitivity of standalone GPS receivers.

[0018] A Global Navigation Satellite System (GNSS) receiver and associated method capable of acquiring weak GNSS signals (i.e., of very low power level) from a plurality of GNSS satellites produces GNSS signal code time, carrier frequency, and data bit transition parameters for subsequent signal tracking and position fixing. The GNSS receiver includes an antenna and an analog front-end to intercept the incoming radio-frequency signal and to convert it to an appropriate intermediate frequency for digital sampling. A baseband signal processor is organized into functionally identical channels, each dynamically assigned to a different satellite in view, with processing results delivered to a data processor for obtaining a navigation solution. By processing the digital samples with a special functionality, the baseband signal processor is able to acquire weak signals. In one embodiment, the weak signal acquisition capable baseband signal processor first reduces the time and frequency uncertainty space using any useful information that can be obtained and then searches through the remaining uncertainty space in a rapid manner in accordance with three techniques of the invention. The first technique of successive sign reversal of short-length correlations (e.g., the 1 millisecond correlation for GPS C/A-codes) enables data bit transition detection and data bit sign correction within a data bit interval (a block). This is in sharp contrast to conventional methods that only process half blocks at a time (undesired SNR loss) or are stretched over two blocks (excessive latency). In addition, it allows for efficient use of Fast Fourier Transform (FFT), which only needs to be calculated once and manipulated simply for all tentative bit alignments.

[0019] As the second technique, the FFT is implemented as a bank of bandpass filters to integrate blocks of correlations in a coherent manner, as opposed to conventional phase rotation that can only handle one bandpass filter at a time and requires excessive frequency search. Finally, the third technique optimizes the overall computation by pruning unlikely branches of the search paths in partial sums. Such a block accumulating coherent integration boosts the signal power while reducing noise despite unknown data bit transitions and other variations that may occur during the extended coherent integration intervals.

[0031] The present invention concerns the device and method for a GNSS receiver capable of acquiring weak satellite signals and extracting time, frequency and other parameters therefrom as an integral part of the receiver's baseband signal processor operations. Although the present invention system and method can be used for the acquisition of various signals used in the GNSS, the present invention system and method are particularly well suited for use with the acquisition of signals from GPS satellites. Accordingly, an exemplary embodiment of the present invention will be described in an application of acquiring weak signals from GPS satellites.

[0032] Referring to FIG. 1, an incoming GPS signal is received at a GPS receiver's RF front-end 7 where it is converted to a digital signal by an analog to digital converter (not shown) and then stored in a digital sample buffer 10. The digital sample buffer 10 can be connected to the RF front-end 7 directly or indirectly via a wireline or wireless data link for real-time computation or for off-line post-processing. The techniques for design and construction of GPS antennas 5, RF front-ends 7, and data link modems that possess the characteristics relevant to the present invention are well known to those of ordinary skill in the art.

[0033] As shown in FIG. 1, signal samples in the digital sample buffer 10 are processed within a signal acquisition channel processing block 20. A multiplicity of similar signal acquisition channel processing blocks may be configured to operate in parallel, each assigned to process signals from a specific GPS satellite. In an alternative embodiment, one signal acquisition channel processing block is used to sequentially process signals from multiple GPS satellites. In yet another embodiment, a number of signal acquisition channel processing blocks can be arranged in a sequential-parallel fashion to process signals from various GPS satellites. As an example of illustration, but not limitation, a single signal acquisition channel processing block is described in detail below.

[0034] Within each signal acquisition channel processing block 20, the digital signal samples pass through a baseband converter 22 and then to a despread correlator 24 with the resulting correlations held in a correlation buffer 26. The baseband converter 22 translates the center frequency of the incoming signal from an intermediate frequency (the nominal frequency plus unknown Doppler frequency and clock drift) to near baseband (zero frequency) by mixing it with a reference carrier produced by a complex carrier generator 36. Since the Doppler frequency is unknown, a time and frequency search director 32 divides the time and frequency uncertainty zone into a grid of search points and steps through in an orderly fashion. Prior information 38 is used to delimit the uncertainty zone and determine the step size. In addition, external aiding information 38, if available, is used to further reduce the uncertainty zone. There are many search strategies that can be adapted for the present invention and an exemplary approach is disclosed in U.S. patent application Ser. No. 11/123,861 filed May 6, 2005 entitled Efficient and Flexible GPS Receiver Baseband Architecture, by co-inventors of this invention, which is hereby incorporated by reference.

[0035] For each search grid point, the test frequency (called a frequency bin) is used by the complex carrier generator 36 to produce the reference carrier used in the baseband converter 22. At the same time, the test code phase (called a code lag) is used by the reference code generator 34 to produce a reference PRN code, which is used in turn in the despread correlator 24 to yield a correlation to be stored in the correlation buffer 26. The time spent at each search grid point is called the dwell time. Conventional receivers typically use a short dwell time on the order of 1 millisecond for coherent integration and several milliseconds for non-coherent integration so as to expedite the signal acquisition process. This choice works fine so long as the incoming signal is around the nominal strength. However, in weak signal cases, the dwell time somehow has to be extended to a rather much longer time interval over which the weak signal is accumulated in strength while the noise is averaged out. The short-length correlations stored in the correlation buffer 26 are processed in a block-accumulating coherent integrator over extended length 28, which will be discussed in more detail below.

[0036] The accumulated correlation over an extended length is then power-tested by a signal detector 30 to determine if a GPS signal of interest is present at the particular search grid point. If the correlation power is below a preset threshold, the search point director 32 moves the acquisition to another search grid point and repeats the whole process. If the correlation power is above the detection threshold, the signal is declared to be acquired and the signal detector 30 initiates the process for handover to tracking 40 with all relevant information associated with the search grid point.

[0037] In the exemplary schematic shown in FIG. 1, the baseband converter 22 is placed ahead of the despread correlator 24. In an alternative arrangement, the despread correlator 24 can be placed ahead of the baseband converter 22, in which case the integration interval of the despread correlator 24 is shortened so as to accommodate large Doppler frequency errors.

[0038] In both cases, either hardware correlators or software correlators can be used to implement the despreading integration. Although the block accumulating coherent integrator 28 is placed within search loops operating on search grid points sequentially, it can be used in conjunction with massive parallel hardware correlators or with a Fast Fourier Transform (FFT)-implemented correlation function. The details of a frequency-domain GPS receiver with FFT are disclosed in U.S. Pat. No. 6,407,699 B1 issued Jun. 18, 2002 to one of the present inventors, which is hereby incorporated by reference.

[0039] One major difficulty encountered in correlation over a long periods of time is the change of the sign of data bits in the middle of a correlation interval. Data bit sign change is also equivalently referred to as data bit transition or data bit sign reversal. Prior to data bit synchronization, correlation can be destroyed even with perfect code phase alignment if the data bit reverses its sign in the middle of an integration interval. Two prior art techniques widely used to deal with a possible data bit transition within a 20 millisecond coherent integration are illustrated in FIG. 2a and FIG. 2b, respectively. The first prior art technique, as shown in FIG. 2a, consists of running two consecutive 10 millisecond coherently integrated sums. If there is a data bit transition in the first 10 millisecond segment, the second 10 millisecond segment is guaranteed to be free of data bit transition, thus allowing for the 1 millisecond short-length correlations added up constructively.

[0040] The second prior art technique, as shown in FIG. 2b, consists of maintaining twenty running sums, each delayed by 1 millisecond relative to its predecessor, wherein only four running sums are depicted to simplify the illustration. These running sums actually extend over two data bit intervals. As shown, the samples in the first sample window of one data bit long fill the first sum and each new sample from the second sample window generates a new delayed sum. If there is a transition, the sum that aligns with the transition produces the maximum value. This prior art technique is useful when the residual frequency error is small. However, when the frequency error is large, it becomes less attractive unless the frequency error is compensated for by proper phase rotation.

[0041] A novel technique used in one embodiment of the present invention is illustrated in FIG. 2c wherein twenty running sums are maintained but each sum successively reverses the sign of one sample of the previous sum. The matched reversal rectifies all samples to the same sign, thus producing the maximum value for the sum. In contrast to the technique using sliding sums over two data bits illustrated in FIG. 2b, this technique allows for the determination of a data bit transition, if any, over one data bit alone.

[0042] Another major difficulty faced by correlation over an extended period of time is the frequency error between the incoming signal and the reference carrier. In the following description, second-order effects will be omitted for simplicity and, consequently, the unknown signal frequency is assumed to be constant over any working interval. To satisfy the frequency error requirement of Eq. (1), a very fine frequency search step size may be imposed for a long coherent integration interval. This amounts to a large number of search steps. For example, if the residual frequency error is 250 Hz for the 1 millisecond correlation, a refined frequency search step of around 2 Hz for an extended coherent integration of 256 milliseconds may be used, corresponding to 128 steps.

[0043] A “brute force” approach would walk through the frequency uncertainty interval one step at a time. At each frequency step, the successive 1 millisecond complex correlation values would be phase-rotated to the desired baseband, followed by adding up twenty phase-rotated short-length correlations every 20 milliseconds, thus reducing the correlations over a data bit into one data point. However, twenty sums would be needed per frequency step, each corresponding to a possible location of data bit transition within the 20 millisecond interval. To go beyond 20 milliseconds, the sums of 20 millisecond-averaged data points would be power-combined over the entire extended integration interval. Tests would then be conducted to determine the most likely sequence of data bits. The maximum sum value among all search steps that is above a preset threshold would provide the best bit sync, bit sequence, and frequency step estimates. This prior art approach is shown as Option 1 in FIG. 3.

[0044] Instead of stepping through the frequency uncertainty interval, a more efficient prior art technique is shown in FIG. 3 as Option 2. This prior art technique attempts to obtain a coarse estimate of the unknown frequency in the presence of data bits. One approach consists of first eliminating the binary phase modulation by squaring the signal samples and then uncovering the signal frequency by bandpass filtering. Squaring further degrades the SNR, which is already at a very low level, and this loss is expected to be compensated for in the subsequent coherent integration once the frequency is successfully estimated after squaring. With this technique, the extended signal samples are processed several times, thus requiring a substantial amount of memory to hold data during the processing. Another approach estimates the unknown frequency in the frequency domain by explicitly accounting for the spreading of 50 Hz navigation data across the frequency bins. The underlying frequency may also be estimated off board at a nearby base station with the frequency estimate sent over via a data link. Similarly, it can also be estimated from an independent source such as an inertial measurement unit (IMU) to expedite the frequency search process.

[0045] FIG. 4 illustrates the major steps of a block accumulating coherent integration technique in accordance with one embodiment of the present invention. A decision is made for every block to ascertain if a GPS signal of interest is present or not. The technique does not need to hold all signal samples in memory and can terminate the acquisition process as soon as the signal is detected without waiting until the very end of the full length. The incoming data samples are processed in blocks; each block is typically 20 milliseconds long and contains twenty 1 millisecond complex correlations over the length of 1 data bit. There are five major steps. The first step selects a data point (i.e., the start of a 1 millisecond short-length correlation) as the tentative bit edge (i.e., bit transition to reverse sign) and then groups the incoming data stream into successive blocks, each block with 20 data points and each data point being a 1 millisecond complex correlation, which is delivered by the despread correlator 24 into the correlation buffers 26 as illustrated in FIG. 1. Since there are 20 possible locations for a data bit to make transition over a data bit length, there are 20 possible bit edges to test. Twenty running sums are therefore created in this step, each in sync with a tentative bit edge. The following steps are applied to each running sum in an orderly fashion.

[0046] As shown in FIG. 4, the second step operates on a block-to-block basis. Assume that the desired extent of the coherent integration interval is L blocks of 20 data points. For each block, this step pads zeros around the data block to the desired length of 20L, which corresponds to a duration of 20L ms assuming each data point is 1 ms. Depending on the location in the sequence, a particular block may require pre-padding and/or post-padding of zeros as shown in FIG. 4 so as to keep the timing (phase) relationship among data points intact. Zero-padding can be used to make the number of data points equal to a power of two for efficient use of the FFT algorithm. More importantly, the resulting frequency resolution after zero padding becomes Δf=1/20L, thus satisfying the coherent integration requirement as specified in Eq. (1). In addition, it maintains coherency among successive blocks when they are accumulated consecutively.

[0047] The third step as shown in FIG. 4 applies a 20L-point FFT to the zero-padded blocks. An efficient implementation of the FFT can take advantage of the large amount of zeros by eliminating those stages of butterfly inside the FFT implementation that correspond to zero input. The resulting complex value at each frequency bin is equivalent to integrating the data points in the block after phase-rotation at this frequency bin (i.e., eliminating the residual Doppler frequency of this value). Although this step is computationally intensive, a number of techniques can be used to reduce the overall computational burden. In conjunction with pruning decisions made in subsequent steps, there may be no need to apply the full-length FFT but rather the discrete Fourier transform (DFT) for few selected frequency bins only. In one example, a 256-point FFT over 256 milliseconds results in 256 frequency bins with a frequency resolution about 4 Hz, covering the frequency range of 1 kHz (±500 Hz). If the residual frequency error is within ±250 Hz, the initial frequency uncertainty is covered with ±64 bins. The calculation of DFT for these bins requires about 64×2×20=2560 multiplications whereas the full length FFT requires about 256×log₂256=2048 multiplications. It is clear that when the number of frequency bins is reduced to less than 50 by pruning, the use of DFT starts to become computationally advantageous.

[0048] As shown in FIG. 4, the fourth step conducts two operations. The first operation attempts to detect the data bit sign for a tentative bit edge. In one approach, the complex value calculated with FFT on the current data block is added to the partial sum of the preceding blocks at the same selected frequency bin. Prior to the addition, the complex value is corrected with two possible signs (i.e., ±1) and the sign that results in a bigger sum is retained. Different decision criteria formulated for bit detection are presented later in this specification. In the second operation, a decision is made as to whether the signal of interest is present. In one approach, the updated partial sums for all selected frequency bins are tested against two predefined thresholds. The upper threshold confirms the acquisition of a GPS signal, and when successful it triggers the transition to tracking. The lower threshold is used to retain those partial sums that are above the threshold for further accumulation with the remaining data blocks and to abort search at those grid points with below-threshold partial sums before reaching the end. Additional criteria may be incorporated to eliminate the most unlikely frequency bins and/or data bit sequences.

[0049] In conjunction with the signal detector 30 of FIG. 1, if a signal is detected, the acquisition for the satellite is terminated by initializing tracking with the estimated bit sync, bit sequence, phase, and frequency as shown in the fifth step of FIG. 4. Otherwise, the search is declared unsuccessful, and the acquisition process continues at the next search grid point as coordinated by the time and frequency search director 32 of FIG. 4.

[0050] Referring to FIG. 4, the tentative bit transition is tested at each of the twenty possible positions in the first step. At a first glance, it might seem necessary to repeat the third step twenty times, each requiring the time-consuming FFT or DFT operations. However, when the bit transition is processed with the technique of the present invention as illustrated in FIG. 2c (i.e., successively reversing the sign of one sample at a time over a data bit), the FFT/DFT of a new bit transition sequence can be constructed from its predecessor with few simple additions, thus making it computationally viable.

[0051] Denote the samples in the m-th block by
x_m={x_m[0], x_m[1], . . . , x_m[19]}={x_m[n]:n=0, . . . , 19}
where x_m[n] is the n-th short-length correlation within the m-th block. The index for the n-th sample of the m-th block in the original data sequence is therefore given by 20(m−1)+n for m=1, . . . , L. The same sequence with a bit transition at the δ-th sample for δ=0, . . . , 19 is represented by x_m^δ={−x_m[0], . . . , −x_m[δ−1],x_m[δ], . . . , x_m[19]} where the sign of the first δ samples is reversed.

[0052] Denote the DFT of x_m by X_m=DFT{x_m}={X_m[k]:k=0, . . . , 20L−1} where

[0053] $\begin{array}{cc}{X}_m\left[k\right]=\sum _{n=0,\dots ,19}{x}_m\left[n\right]\exp \left\{-\mathrm{j2\pi }k\left[{\left(m-1\right)}^{*}20+n\right]/20L\right\}k=0,1,\dots ,20L-1;m=1,\dots ,L& \left(3\right)\end{array}$

[0054] It is easy to show that the DFT of x_m^δ+1 is related to that of x_m^δ by:
X_m^δ+1[k]=X_m^δ[k]−2x_m[d] exp {−j2πk[20(m−1)+d]/20L}δ=0, . . . , 19;k=0, . . . , 20L−1;m=1, . . . , L  (4)

[0055] The first term on the right hand side of Eq. (4) has been evaluated in X_m⁰[k]=X_m[k]. If saved in memory, it can be recalled for re-use. As a result, additions alone are sufficient to obtain the FFT/DFT for the 19 possible sequences in bit alignment search. Furthermore, only those k's that have been retained by previous partial sums need to be evaluated.

[0056] The block-accumulating coherent integration technique in accordance with the present invention utilizes the successive sign reversal method to rectify different data bit signs as illustrated in FIG. 2c in contrast to the prior art parallel sliding sum method and half-length sum method as shown in FIGS. 2b and 2a, respectively. With the present technique, each data block has 20 milliseconds worth of samples (i.e., 20 data points), each being the 1 millisecond complex correlation. When the tentative bit edge is set at the very first data point of the block, the data bit transition is thus assumed to coincide with this 20 millisecond block. For this aligned block, there are only two sign possibilities, either positive or negative. FIGS. 5a, 5b and 5c show the time diagram, state machine diagram, and trellis diagram, respectively, for the situation with aligned blocks. The truth table for this case is shown in FIG. 5d.

[0057] However, when the tentative bit edge is set at one of the remaining 19 data points of the block, the data bit transition does not coincide with a 20 millisecond data block but occurs somewhere within the block, thus having 19 possible positions (from the 2nd to 20th data points). Furthermore, the bit transition may not take place (not visible) in unaligned blocks if two consecutive bits are of the same sign. As a result, an unaligned block faces four possibilities. The first two correspond to no bit transition while the other two represent one bit transition, as illustrated in the time diagram of FIG. 6a. The four states are defined as (1) State 1: All positive; (2) State 2: All negative; (3) State 3: Transition from negative to positive; and (4) State 4: Transition from positive to negative.

[0058] According to this definition and from the time diagram of FIG. 6a, there are two branches into and out of a state, which is better illustrated by the state machine diagram of FIG. 6b with the truth table listed in FIG. 6c. From the state machine diagram in FIG. 6b and the truth table in FIG. 6c, it is easy to verify that State 1 and State 3 share the same transition patterns; so do State 2 and State 4. Furthermore, State 2 is the same as State 1 except for a sign difference. So is State 4, which is the same as State 3 except for a sign difference. Therefore, only a two-state machine, rather than a four-state machine, is needed to represent bit transitions, thus saving about a half of the memory and computation. The sign ambiguity associated with the two-state machine is of no consequence so long as the sign is taken consistent throughout the extended interval.

[0059] The trellis diagrams for a four state transition with the initial state being State 1, State 2, State 3, and State 4 are shown in FIGS. 7a, 7b, 7c, and 7d, respectively. After two blocks, possible transitions populate all the states, from which point on a decision is made every step to select the most likely path that has arrived at the current state.

[0060] When bit transitions are modeled by a trellis diagram as shown in FIG. 5c or FIG. 7, the selection of a best sequence is cast into the classic problem of a traveling salesman trying to find the shortest path between two cities. Two popular solutions exist. One is the forward dynamic programming, simply known as dynamic programming, and the other is the reverse dynamic programming, best known as the Viterbi algorithm. The dynamic programming technique finds the solution in a backward-search forward-evaluation (to the end) fashion typically used in optimal control, whereas the Viterbi algorithm finds the solution in a forward-search backward evaluation (from the start) manner widely used in sequence estimation as in the present invention's formulation. Both are based on the Bellman principle of optimality.

[0061] Compared to conventional state machines or trellis diagrams used in Viterbi algorithm implementation, the data bit detection for weak signals, however, lacks the values assigned to transition branches as costs or weights. In a typical implementation of the Viterbi algorithm for sequence estimation, the squared error between the observation value and the value assigned to each transition branch provides a cost for that transition. The sequence of states that offers the minimum cost is considered to be the most likely one.

[0062] Some prior art techniques use the expected signal levels as the assigned values to transition branches and as such, the Viterbi algorithm can be applied directly in a conventional manner. Once the data bit sequence is derived from the Viterbi algorithm, the final signal level is obtained as a part of the residual frequency and phase estimation process. However, how to select the expected signal levels is a difficult problem that may make the prior art algorithms highly sensitive to initialization errors. In addition, some prior art techniques use sequential frequency search and phase-rotation to deal with large frequency errors for coherency between blocks, which is computationally too demanding.

[0063] Since it is difficult, if not impossible, to predict signal levels under weak conditions with large uncertainties, instead of using the minimum cost seeking scheme as in prior art techniques with the conventional Viterbi algorithm, the present invention sets forth the maximum performance index finding scheme where the performance index is defined as the block-accumulated correlations. In one embodiment, after processing each new block of data (call it a stage), four possible states are updated; and each updated state retains a surviving path ended at this state (accompanied with a sequence of estimated data bit signs). In an alternative embodiment, only two states are updated because there are only two possible bit transitions for the second block given the data bit in the first block. The use of this conditional bit transition constraint can reduce the amount of computations by half.

[0064] For all paths leading to a state at the present stage, only the path that produces the largest performance index up to this stage is kept while all others are pruned off. This is because no matter what happens hereafter, the largest performance index path at this stage remains to be the largest for the rest of stages.

[0065] Conventional Viterbi algorithms preserve the paths for all states over a data window of finite length. When the data path length grows to the window length, the state with the lowest cost (or the highest performance index) is selected. The path leading to this best state is back tracked and the first state or branch in the window is taken as the output. At the next stage, the window slides over by one data point and all the paths are extended with the new data point. Then all paths are evaluated, the best path is selected, and a single output is produced. The process repeats.

[0066] However, this sliding output of the initial state per window length is not appropriate for the weak signal acquisition case because a decision has to be made within an extended integration interval (a data window of 256 milliseconds for instance) and there is no luxury to perform a sliding operation at each search grid unless the decision interval of 256 milliseconds is divided into smaller test intervals. One example is to have a window length of 4 blocks (or 80 milliseconds). However, maintaining a window length longer than 1 block requires additional memory and computation to keep track of possible paths from stage to stage for all states. This may not yield a proportional performance improvement.

[0067] A preferred embodiment in accordance with the present invention (1) adopts the maximum performance index (i.e., summed correlations) as the optimization criterion in contrast to the prior art minimum cost function, (2) implements a two-state machine with State 1/State 3 and State 2/State 4, thus reducing the memory and computation by half, and (3) makes a decision every stage by keeping only one state that possesses a surviving path with the maximum performance index among all states. The latter is equivalent to having a unity window length in the conventional Viterbi algorithm parlance.

[0068] Referring back to FIG. 4, the fourth and fifth steps may be skipped altogether for some bit alignment sequences if their partial sums stay below a threshold (i.e., to exclude those bit transitions at unlikely d's). As the coherent integration continues, the minimum SNR level as expected from the data blocks already integrated may be used to set up the thresholds for subsequent detection. As the pruning progressively trims down the number of search paths when integrated into more and more blocks, the overall computation load is therefore maintained, thus making the technique fast and efficient.

[0069] Referring to FIG. 4, in the fourth step, for each tentative bit alignment, the sign of data bit for a block can be found such that it maximizes the partial sum across all the frequency bins:
b=arg max_b=±1{|Sum fb[k]+b*fb[k]|: for all k}  (5)
where fb[·] stands for the FFT of the current block, Sum fb[·] is the accumulated FFT up to the previous block (partial sum), k is the index of frequency bin, |·| stands for the magnitude of the enclosed complex vector, and b is the best estimate of the data bit sign b for the current block.

[0070] Instead of determining a data bit sign for all frequency bins, an alternative approach applies the decision rule on individual frequency bins:
b_k=arg max_bk=±1{|Sum fb[k]+b_k*fb[k]|: for each k}  (6)
where b_k is the best estimate of the data bit sign b_k for the current block at the frequency bin k. Working on each and every frequency bin, the alternative approach needs more memory to keep track of all the data bit sequences but offers better performance at the cost of more computation.

[0071] FIG. 8 shows a flow chart which captures the five major steps illustrated in FIG. 4 of a block accumulating coherent integration technique in accordance with an embodiment of the present invention. A block of twenty consecutively 1 millisecond correlations is collected at step 50 from the correlation buffer 26 of FIG. 1. Successive blocks of twenty correlations are so collected and delivered for processing at the next step.

[0072] At step 52, each block of twenty data points is pre-padded and/or post-padded with blocks of zeros to the length of 20L where L is the number of blocks for the desired length of extended coherent integration. Zero-padding is done in such a way that the relative timing of a block in the original sequence is preserved over the entire extended length.

[0073] Next at step 54, a 20L-point FFT is taken over the zero-padded block of 20L data points. Alternatively, a DFT can be calculated for those frequency bins that have survived the pruning process applied to the preceding blocks if the computation of the DFT at the selected frequency bins is less demanding than that of a full-blown FFT.

[0074] By assuming that the bit transition coincides with the first data sample in the block, the first tentative bit edge placement deals with an aligned block. As such, the FFT or DFT calculated at step 54 can be used directly. However, any of the remaining nineteen tentative bit edge placements has to handle an unaligned block. At step 56, the FFT or DFT for a new bit edge placement is calculated from that of the preceding placement by reversing the sign of successive data points, one for each bit edge recursively. Step 56 is repeated for all twenty possible bit edges, as shown by the decision box at step 64.

[0075] Next at step 58, the best data bit sign for the current block at a given tentative data bit edge is determined for selected frequency bins. For unaligned blocks, the possible bit transitions are constrained by the state of the previous block. The use of conditional bit transitions thus reduces the amount of computation and memory otherwise required. To the partial sum accumulated over the preceding blocks is added the complex correlation of the current block with its sign corrected for possible conditional bit transitions. Only the largest one is kept with the corresponding sign as the most likely one while the others are discarded. Step 58 is repeated for all selected frequency bins, as shown by the decision box at step 62.

[0076] The pruning operation may be withheld during the initial accumulation at step 60. After few blocks, the most likely path is kept while the unlikely ones are pruned off to keep the overall computation within a manageable size.

[0077] At step 66, the updated partial sums are compared to a preset threshold. If a partial sum exceeds the detection threshold, the signal is declared “detected” or “acquired” and the signal parameters associated with the partial sum are passed on for handover to tracking 40. The signal parameters include the coarse time and frequency values at the search grid point, the most likely bit edge within a block, and the sequence of data bits. Since the threshold test at step 66 is done every block, the signal acquisition process may be terminated whenever a signal is detected without the need to wait until the very end of an extended interval. Without any partial sum exceeding the threshold, the process moves on to the next block, as shown by the decision box at step 68. If there is still no detection when the end of a desired extended coherent interval is reached, the whole process is moved to an option step of non-coherent power combination 70. The non-coherent integration may be carried out over several coherent integration intervals. If there is still no detection, the whole process is moved to the next search grid point by the time and frequency search director 32.

[0078] Although the above description contains much specificity, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. For example, the present invention provides a generic signal processing architecture of versatility wherein many processing blocks can be tailored to achieve a desired combination of functionalities.

[0079] Reference has been made mostly to the GPS signals with the C/A-codes but the techniques of present invention are equally applicable to the Russian GLONASS and European GALILEO signals, ground and space-based augmentation signals, and other components of the GNSS in general. Similarly, the techniques of the present invention are disclosed in connection with correlator-based GPS receivers but it can work equally well with matched filter-based receivers. If the matched filters are used to operate on the full C/A-code epoch of 1 millisecond, the receiver architecture is similar to that of the correlator-based receiver disclosed above. However, techniques of the present invention can be used in different receiver architectures. As an example, when subinterval correlation is supported for despreading integration with either a correlator or a matched filter, code stripping can be placed ahead of carrier down-conversion. In addition, the integration can be done sequentially one code phase at a time or in parallel for all possible code phases at the same time. Placing time search in the outer loop may render the pre-correlation frequency search unnecessary if the subinterval is judiciously chosen. If the maximum frequency uncertainty due to Doppler and clock drift is about ±10 kHz, the conventional full integration over 1 millisecond requires the frequency error to be within 500 Hz, dictating 20 frequency search steps in each direction. However, if the subinterval integration is set at 0.05 milliseconds (the equivalent bandwidth is 20 kHz), there is no need to perform frequency search prior to integration because this subinterval integration can tolerate the maximum frequency error of ±10 kHz. This leads to twenty 0.05 millisecond subintervals per a C/A-code epoch of 1 millisecond, 400 data points per data bit interval of 20 milliseconds. If the reference code is aligned within a half chip to the underlying signal, the subinterval correlation output is effectively sampled at the rate of 20 kHz, a real-valued sine wave. This sine wave has an unknown frequency up to 10 kHz and is bi-phase modulated by an unknown sequence of 50 Hz navigation data bits. The disclosed techniques of the present invention can be applied at this point to perform the extended coherent integration directly except with more data points per block.

[0080] It is understood that the figures and associated description above illustrate only the preferred embodiments of the present invention system and method. A person skilled in the art can therefore make numerous alterations and modifications to the described embodiments utilizing functionally equivalent components and method steps to those shown and described. All such modifications are intended to be included within the scope of the present invention as defined by the appended claims.