Time delay control scheme for a power supply with multiple outputs

[0001] 1. Field of the Invention

[0002] The present invention relates to a control scheme for a power supply, and more specifically to a time delay synchronous control scheme for a power supply, which has multiple outputs and tight output regulations.

[0003] 2. Description of the Related Art

[0004] In the design of switching mode power supplies (SMPS) with multiple outputs, it is important to meet the requirements for the cross regulation of the multiple outputs. Additionally, with the development of the SMPS, it is imperative to consider high efficiency and low cost.

[0005] FIG. 1 illustrates a block diagram of the conventional implementation for SMPS with multi-outputs. This implementation includes a front-end DC/DC converter 1 and is cascaded with two post buck converters 2 and 3. One of the outputs is achieved as Vo3 directly from the front-end DC/DC converter 1. Both of the post buck converters 2 and 3 have an input filter with a LC structure, cascading the output capacitor Cf of the front-end DC/DC converter 1.

[0006] The conventional SMPS as shown in FIG. 1 can achieve tight multiple output regulations because the front-end DC/DC converter 1 and the post buck converters 2 and 3 operate respectively and independently. However, the additional cost of the input filters of the post buck converters 2 and 3 are not what was anticipated. Furthermore, although the input filter is added for each of the post buck converters 2 and 3, a ripple current with a considerable rms (root mean square) value is still obtained on the output capacitor Cf of the front-end DC/DC converter 1 because of the inherent pulsating input traits of the post buck converters 2 and 3. This will significantly increase the current stress and the loss dissipated on the output capacitor. To alleviate the pressure due to the loss rise, the use of a higher number of capacitors or alternatively, high quality capacitors are inevitable. This will lead to a higher cost for this architecture, especially in the case when the outputs have large output currents.

[0007] It is therefore attempted by the applicant to provide a new architecture with a new control scheme, which can overcome the defects of the prior art for SMPS with multiple output application.

[0008] A new power architecture used for a switching mode power supply (SMPS) with multiple outputs is thereby proposed in the present invention. It should be noted that the front-end DC/DC converter is specified as the one with a current mode output, which rectifies a pulse current to the output capacitor, such as a flyback converter. Additionally, unlike the prior art, the post buck converters directly cascade the output capacitor of the front-end DC/DC converter and the input filters of post buck converters are eliminated. A time delay synchronous control circuit is proposed in the SMPS of the present invention, which serves as the controller for the post buck converters. The proposed time delay synchronous control circuit at least has following functions. First, realize the synchronization of the front-end DC/DC converter and the post buck converters. Secondly, provide and modulate a pulse width of a drive signal for post buck converters to achieve tight multiple regulations. Thirdly, based on the principle to obtain a minimized rms value of a ripple current on the output capacitor, the delay time between the front-end DC/DC converter and the post buck converters can be controlled.

[0009] Thus, the post buck converter can directly draw the pulse input current at the time when the DC/DC converter has pulse output current to the output capacitor of the front-end DC/DC converter. Therefore, the high conversion efficiency can be anticipated due to low loss on the output capacitor Cf₁. Furthermore, the input filter in the prior art can be eliminated so as to achieve a relatively lower cost.

[0010] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a time delay synchronous control scheme for a power supply with multiple outputs. The power supply includes a front-end converter with a current mode output and a first buck converter and a second buck converter. Both of the buck converters directly cascade the output capacitor of the front-end converter. In the time delay synchronous control scheme, a delay time between the time the front-end converter begins to have the pulse output current to its output capacitor and the time the first buck switch or the second buck switch is turned on is adjusted. Both of the first buck switch and the second buck switch draw pulsating input current during the time when the front-end converter has the pulse output current to its output capacitor.

[0011] In an alternative embodiment of the time delay synchronous control scheme, after the delay time behind the time when the front-end converter begins to provide the pulse output current, the first buck switch and the second buck switch are sequentially turned on and then the second buck switch is turned off before the first buck switch being turned off. In an embodiment, the first buck switch is turned off before the pulse output current of the front-end converter reaches to zero.

[0012] In an alternative embodiment of the time delay synchronous control scheme, after the delay time behind the time when the front-end converter begins to provide the pulse output current, the first buck switch is turned on and then the first buck switch is turned off. At the time the first buck switch being turned off, the second buck switch is sequentially turned on. In an embodiment, the second buck switch is turned off before the pulse output current of the front-end converter reaches to zero.

[0013] In an alternative embodiment of the time delay synchronous control scheme, if a zero current time interval exists between every two of the output current pulses of the front-end converter, the first buck switch and the second buck switch are sequentially turned on and then the first buck switch is turned off before the second buck switch being turned off. An overlap exists between the period of the first buck switch being on and that of the second buck switch being on.

[0014] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a time delay synchronous control scheme for a power supply with multiple outputs. The power supply includes a front-end converter for sequentially providing a current mode output and a first buck converter and a second buck converter. Both of the first buck converter and the second buck converter cascade a first output capacitor of the front-end converter. The front-end converter is used for providing a first output of the power supply and the first buck converter and the second buck converter for providing a second output of the power supply. In the time delay synchronous control scheme, the first buck switch and the second buck switch alternative draw one of the two pulse currents from the first output capacitor during the time when every two pulses of the output current are provided.

[0015] In the above time delay synchronous control scheme, a delay time exists between the time the pulse output current of the front-end converter is provided and the time the first buck switch or the second buck switch is turned on. Both of the first and second buck switches are turned off before the pulse output current of the front-end converter reaches to zero. To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a time delay synchronous control scheme for a power supply with multiple outputs. The power supply includes a flyback converter with a diode rectifier or a synchronous rectifier and an output capacitor. The power supply further includes a buck converter, directly cascading the output capacitor of the flyback converter. In the time delay synchronous control scheme, the buck switch begins to turn on synchronously with the rectifier at the time the flyback converter turns off and turn off at the time before the time when the flyback converter turns on.

[0016] Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0030] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0031] A new power architecture used for a switching mode power supply (SMPS) with multiple outputs is thereby proposed in the present invention. It should be noted that the front-end DC/DC converter is specified as the one with current mode output. Additionally, unlike the prior art, the post buck converters are cascaded directly from the output capacitor of the front-end DC/DC converter and the conventional input filter of post buck converters are eliminated. A time delay synchronous control circuit is proposed in the SMPS of the present invention, which serves as the controller for the post buck converters. The proposed time delay synchronous control circuit at least has following functions. First, realize the synchronization of the front-end DC/DC converter and the post buck converters. Secondly, provide and modulate a pulse width of a drive signal for post buck converters to achieve tight multiple regulations. Thirdly, based on the principle to obtain a minimized rms value of a ripple current on the output capacitor, the delay time between the front-end DC/DC converter and the post buck converters can be controlled.

[0032] Thus, the post buck converter can directly draw the pulse input current at the time when the DC/DC converter has pulse output current to the output capacitor of the front-end DC/DC converter. Therefore, the high conversion efficiency can be anticipated due to low loss on the output capacitor Cf₁. Furthermore, the input filter in the prior art can be eliminated so as to achieve a relatively lower cost.

[0033] In an alternative embodiment of the present invention, as shown in FIG. 2, which illustrates a block diagram of a switching mode power supply with a delay time control for the synchronous post buck converters. The architecture used for a switching mode power supply with multiple outputs includes a front-end DC/DC converter 210, two post buck converters 220 and 230, and a time delay synchronous control circuit 240. The front-end DC/DC converter 210 is specified as the one with current mode output. Unlike the conventional architecture, the two post buck converters 220 and 230 are cascaded directly from an output capacitor Cf₁ of the front-end DC/DC converter 210 and the input filters of post buck converters are eliminated.

[0034] The time delay synchronous control circuit 240 is proposed in the architecture of the SMPS of the present invention, which serves as the controller for the post buck converters. The proposed time delay synchronous control circuit 240 at least has following functions. First, realize the synchronization of the front-end DC/DC converter and the post buck converters. Secondly, provide and modulate a pulse width of a drive signal for post buck converters to achieve tight multiple regulations. Thirdly, based on the principle to obtain a minimized rms value of a ripple current on the output capacitor, the delay time between the front-end DC/DC converter and the post buck converters can be controlled.

[0035] In an alternative embodiment of the present invention, as shown in FIG. 3, a preferred embodiment of the proposed architecture is illustrated with an LLC-SRC (Series Resonant Converter, SRC) as the front-end DC/DC converter 210 of FIG. 2. To improve the poor regulation characteristics of the series resonant converter (SRC), if the magnetizing inductor of the transformer in SRC takes part in the resonance process, an LLC-SRC is obtained. In the proposed architecture, an LLC-SRC 110 employing a full-wave rectifier 120 is adopted as the front-end DC/DC converter and the time delay synchronous control circuit 170 is used to synchronize and modulate two post buck converters 130 and 140 to achieve tightly regulated multiple outputs. The LLC-SRC 110 includes a bridge circuit 150 including a pair of power switches S₁ and S₂ that drive a resonant tank 160 composed of a series resonant inductor Ls, a series resonant capacitor Cs and a magnetizing inductor Lm of a transformer TX. The series resonant inductor Ls can be discrete component or is replaced by leakage inductance of the transformer TX. The three resonant components constitute two characteristic frequencies f_s and f_m for the resonant LLC tank, which can be obtained using the following equations:

[0036] $\begin{array}{cc}\mathrm{fs}=\frac{1}{2\pi \sqrt{\mathrm{Ls}·\mathrm{Cs}}}& \left(1\right)\\ \mathrm{fm}=\frac{1}{2\pi \sqrt{\left(\mathrm{Ls}+\mathrm{Lm}\right)·\mathrm{Cs}}}& \left(2\right)\end{array}$

[0037] The half bridge circuit 150 is further illustrated with an input voltage Vin and a bus capacitor Cb. The transformer TX, including a primary winding n_p and two secondary windings n_s1 and n_s2 connected in series in phase, isolates the bridge circuit 150 and the resonant tank 160 from the full-wave rectifier 120.

[0038] The full wave rectifier 120 comprises of a pair of rectifier diodes D₁ and D₂ connected to the output capacitor Cf₁. Cathodes of the rectifier diodes D₁ and D₂ are connected through the output capacitor Cf₁ to an output filter composed of Lo₃ and Co₃ to get an output Vo3. An anode of the rectifier diode D₁ is connected to a nominal terminal of the secondary winding n_s1 and an anode of the rectifier diode D₂ is connected to a reverse terminal of the secondary winding n_s2. A connection terminal of the windings n_s1 and n_s2 is connected to the output as the ground of the secondary side.

[0039] A power switch Q₁, a freewheeling diode D₃, an output inductor Lo₁ and an output capacitor Co₁ forms the post buck converter 130, which is directly cascaded from the output capacitor Cf₁. In addition, the output capacitor Cf₁ is directly cascaded with the other post buck converter 140 including a power switch Q₂, a freewheeling diode D₄, an output inductor Lo₂ and an output capacitor Co₂.

[0040] The LLC-SRC features that under appropriate parameter design, it can achieve Zero Voltage Switching (ZVS) for the primary side switches and Zero Current Switching (ZCS) for the secondary side switches.

[0041] An operation state of LLC-SRC and the timing sequence of the time delay synchronous control is illustrated in FIG. 4. It occurs under influence of the switching frequency for switches S₁ and S₂ satisfying the following condition:
fm≦f≦fs  (3)

[0042] At t=t₀, because a primary current i_r is negative, the main switch S₁ turns on under the ZVS condition. During the time period from t₀ to t₁, the rectifier diode D₁ draws the output current, which causes the voltage on the magnetizing inductor L_m to be clamped to a constant value by the output voltage. Therefore, the magnetizing inductor L_m does not take part in the resonant process and increases linearly during this period of time. Referring to FIG. 4, the current i_d1 in the rectifier diode D₁, is a quasi-sine shape due to the resonance of L_s and C_s.

[0043] At t=t₁, since the switching period is longer than the resonant period of L_s and C_s, i_r drops and equals i_m before the switch S₁ turns off. Therefore the rectifier diode D₁ stops drawing the output current. The resonance now happens through C_s, L_s, and L_m.

[0044] At t=t₂, the switch S₁ turns off. The body diode of the switch S₂ begins to conduct. At time at t=t₃, the switch S₂ turns on under ZVS condition.

[0045] The same operation process can be analysed in time intervals t₃<t<t₄ and t₄<t<t₅, for which the same operation state is achieved for the current i_d2 of the rectifier diode D₂ as shown in FIG. 4.

[0046] The sum of i_d1 and i_d2 constitutes a quasi-sine rectified current i_rec that flows to one of the output Vo3 through the output capacitor Cf₁. If the LLC-SRC 110 operates at the switching frequency f_s, the dead time when either of the rectifier diodes D₁ and D₂ has conduction current, will be cancelled. Under such conditions, the current i_rec will be in a rectified sine wave shape.

[0047] In the embodiment described in FIG. 3, the basic conception of the time delay synchronous control circuit 170 is to make sure the buck switches Q₁ and Q₂ of the post buck converters 130 and 140 draws pulse currents from the output capacitor Cf₁ only during the time when the diode D₁ or D₂ has conduction current. And through adjusting the delay time between the turn-on time of either diode of D₁ or D₂ and that of the post buck converters, the minimized rms ripple current for the output capacitor Cf₁ can be achieved. To explain further using FIG. 4, the time delay synchronous control circuit 170 aids in determining the turn-on time t_d1 of the switch Q₁, the turn-on time t_d2 of the switch Q₂, and to be certain of the turn-off time of the switch Q₂ before the turn-off time of D₁ t_d3.

[0048] Refer to FIG. 5, which illustrates a principle and a process of ripple current reduction for the output capacitor Cf₁ according to an embodiment of the present invention. To illustrate with simplicity and clarity, the results of the analysis, the following deduction and calculation are based on the premise that the quasi-sine wave rectified current i_rec is approximated to a sinusoidal shape and the LLC-SRC operates at the switching frequency fs. If the synchronous post buck converters do not work, there is only one output current I_o3′. Therefore, a ripple current i_cf1′ on the output capacitor Cf₁ is achieved by i_rec minus I_o3′. The rms value of the ripple current i_cf1′ is obtained as:
I_cf1,rms′=√{square root over (I_rec,rms²−I_o3′²)}  (4)

[0049] Where I_rec,rms is the rms value of i_rec and can be expressed as:

[0050] $\begin{array}{cc}{I}_{\mathrm{rec},\mathrm{rms}}=\frac{\sqrt{2}}{2}{I}_{\mathrm{rec},p}& \left(5\right)\end{array}$

[0051] Where I_rec,p is the peak current of i_rec.

[0052] Since, the current i_rec is the average value of i_rec, I_rec,p is rewritten as:

[0053] $\begin{array}{cc}{I}_{\mathrm{rec},p}=\frac{\pi }{2}{I}_{\mathrm{o3}}^{\prime }& \left(6\right)\end{array}$

[0054] From equations (4), (5) and (6), the rms value of the ripple current i_cf1′ is expressed as:

[0055] $\begin{array}{cc}{I}_{\mathrm{Cf1},\mathrm{rms}}^{\prime }=I_{p_{\mathrm{o3}}}^{\prime }\sqrt{\frac{{\pi }^2}{8}-1}=0.483I_{\mathrm{o3}}^{\prime }& \left(7\right)\end{array}$

[0056] It can be deduced from equation (7) and FIG. 5, that there exists large amplitude of the ripple current on the output capacitor Cf₁, if the time delay synchronous control scheme is not being used for the synchronous post buck converters. A ripple current with much higher amplitude than that shown in equation (7) also exists on the output capacitor Cf₁, which is found in the conventional SMPS implementation of FIG. 1. Since, the post buck converters have pulsating input currents. To reduce the ripple current on the output capacitor Cf₁, an alternative time delay synchronous control scheme for the synchronous post buck converters of FIG. 3 is illustrated in FIG. 5.

[0057] The buck switch Q₁ is set to turn on at time t₁ with a delay time behind the time t₀ when the current i_rec begins to increase from zero. Then at time t₂, the buck switch Q₂ turns on. The switch Q₂ turns off at t=t₃ before the time t₄ when the buck switch Q₁ turns off. And the buck switch Q₁ turns off before the time t₅ when the current i_rec decreases to zero. From the onset of time t₄, the same switching process occurs for the switches Q₁ and Q₂ in another half-wave of i_rec. Therefore, the switching frequency of the switches Q₁ and Q₂ is double of that of the LLC-SRC.

[0058] From FIG. 5, it can be observed that, after currents are drawn by the switches Q₁ and Q₂ during every half wave of i_rec, a current with abundant high order harmonics i_rec′ is left to supply the third output I_o3 through the output capacitor Cf₁. Separated from the DC component I_o3, an AC ripple current i_cf1, is achieved from i_rec′ on the capacitor Cf₁. Compared with the former i_cf1′, this ripple current has a significantly reduced rms value.

[0059] Refer to FIG. 6, which illustrates an alternative time delay synchronous control scheme for the synchronous post buck converters of FIG. 3.

[0060] Furthermore, to simplify the process of the analysis under the condition of not affecting the analysis results, the input currents i_Q1 and i_Q2 of the buck switches Q1 and Q2 are deemed in a square shape. A typical situation, in which both of the buck converters have the same output currents, is showed in FIG. 6. Assuming the output power is the same as in the former situation, with no synchronous post buck converters. Furthermore, the loss in the post synchronous post buck converters is neglected. The rectified current i_rec should be in the same shape with the same amplitude as the former.

[0061] The buck switch Q₁ is set to turn on at time t₁ with a delay time behind the time t₀ when the current i_rec begins to increase from zero. At time t₂, the buck switch Q₁ turns off and the buck switch Q₂ begins to turn on. The switch Q₂ turns off at t=t₃ before the time t₄ when the current i_rec decreases to zero. From the onset of time t₄, the same switching process occurs for the switches Q₁ and Q₂ in another half-wave of i_rec. Therefore, the switching frequency of the switches Q₁ and Q₂ is double that of the LLC-SRC.

[0062] From FIG. 6, it can be observed that, after currents are drawn by the switches Q₁ and Q₂ during every half wave of i_rec, a current with abundant high order harmonics i_rec′ is left to supply the third output I_o3 through the output capacitor Cf₁. Separated from the DC component I_o3, an AC ripple current i_cf1, is achieved from i_rec′ on the capacitor Cf₁. Compared with the former i_cf1′, this ripple current has a significantly reduced rms value.

[0063] This process of the ripple current reduction on the output capacitor Cf₁ can be illustrated by an example of a 235 W prototype, as shown in Table 1. The example has the same architecture as FIG. 3 and three output voltages: +12V for Vo3, +5.5V for Vo1 and +3.3V for Vo2. All are obtained from two synchronous post buck converters.

[0064]

	TABLE 1
	Load
	1	2	3	4	5	6	7	8
(Vo3)	155 W	90 W	0 W	155 W
12 V
(Vo1)	40 W	80 W	14 W	125 W	79 W	125 W	79 W	0 W
5.5 V
(Vo2)	40 W	0 W	66 W	20 W	66 W	20 W	66 W	0 W
3.3 V

[0065] If all of the 235 W power is delivered to +12V output, the rms value of the ripple current i_cf1′ is achieved from equation (7) as:
I_cf1,rms′=0.483×235/12=9.46A

[0066] If 79 W is distributed to the +5V output, and +66 W is distributed to the +3.3V output, it can be deduced that I_o1 is 15.8 A and I_o2 is 20 A, the rest of the power 90 W is distributed to +12V output. When the time interval between t₀ to t₁ equals to that from t₃ to t₄, the rms value of the ripple current I_cf1,rms can be calculated as 5.34 A, which is significantly reduced from the former 9.46 A in the situation without the synchronous post buck converters.

[0067] In the situation when the switching frequency of LLC-SRC satisfies equation (3), the rectified current i_rec includes a dead conduction time during the time interval from t₁ to t₂ as shown in FIG. 4. If still adopting the timing sequence shown in FIG. 6, the sum of the conduction time of i_Q1 and i_Q2 may go beyond each pulse duration of the rectified current i_rec, which will cause a significant rise for the rms value of the ripple current i_cf1. Referring to FIG. 7, to ensure the buck switch Q₁ and Q₂ to draw currents within the pulse duration of every half wave, the i_Q1 and i_Q2 may have an overlap. This implies that the switch Q₂ turns on at the time of t₂ before the time of t₃ when the switch Q₁ begins to turn off. Hence, the switch Q₂ can be turned off at the time of t₄ before the time of t₅ when the current i_rec reaches zero. In this scheme of the time delay synchronous control for the two post buck converters, the rms value of the ripple current i_cf1 should also have a significant reduction compared with the former i_cf1′ from its waveform shape shown in FIG. 7.

[0068] Refer to FIG. 8, which illustrates a situation when the switching mode power supply has two outputs, an output voltage Vo3 directly from the LLC-SRC 110 and an output Vo1 with a very low voltage compared with Vo3. Under such conditions, if the scheme shown in FIG. 3 is still being considered, the rms value of the output capacitor Cf₁ can not be reduced, because the conduction time of the buck switches Q1 and Q2 will be very narrow, and the post buck converters 130 and 140 will have a very high pulse input current. Therefore, an interleaved structure of two synchronous post buck converters 130 and 140 is adopted in FIG. 8, and the scheme of the time delay synchronous control is shown in FIG. 9.

[0069] In each half wave of the current i_rec, the buck switches Q₁ and Q₂ alternately draws the input pulse current through the output capacitor Cf₁ and has the same delay time from their relative half wave of i_rec. The switching frequency of Q₁ and Q₂ here is the same as that of the front-end LLC-SRC 110. The pulse width of Q₁ and Q₂ is broadened to double that in the aforementioned case. The current stress on the capacitor Cf₁ is thereby alleviated greatly.

[0070] Refer to FIG. 10, which shows another preferred embodiment of the present invention, in which the front-end DC/DC converter is a flyback converter 901. The flyback converter includes a bus capacitor Cb, a flyback transformer TX₁, a main switch S₁, a rectifier diode D₁ and an output capacitor Cf₁, together with an output filter composed of an inductor Lo₂ and a capacitor. A buck converter 902, made up of a buck switch Q₁, a freewheeling diode D₂, an output inductor Lo1 and an output capacitor Co₁, cascades directly from the output capacitor Cf₁.

[0071] Refer to FIG. 11, which illustrates a scheme of the time delay synchronous control for the post buck converter 902. The buck switch Q₁ begins to turn on at time t₁ when the flyback converter has a pulse current to the output capacitor and turn off at time t₂ before the time of t₃ when the main switch S₁ of the flyback converter 901 turns on. Thus, as FIG. 11 shows, a final ripple current i_cf1 on the output capacitor Cf₁ is achieved with a significantly reduced rms value compared with the original i_cf1′ without the post buck converter.

[0072] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.