Phase-locked loop bandwidth calibration

[0001] This disclosure relates to phase-locked loops and, more particularly, to the bandwidth of a phase-locked loop.

[0002] The increasing demand for low cost, miniaturized, power efficient communication systems is driving demand for higher levels of functionally to be incorporated within integrated circuits. Phase-locked loop circuits are not immune to these demands. A phase-locked loop (PLL) is a circuit that maintains a signal in a fixed phase relationship to another signal, known as the reference signal. A type of closed-loop feedback control system, PLLs may be dispersed throughout a design to support various system functions.

[0003] A PLL circuit may consist of a reference signal, a phase detector and a voltage-controlled oscillator (VCO), arranged in a negative feedback configuration. Additionally, a filter, a charge pump, and a divider may be present. The VCO generates a periodic output signal that is fed back into the phase detector (or, alternatively, a phase frequency detector). When the output signal is not phase-aligned with the reference signal, the phase detector sends a pulse to the VCO (or intervening circuitry), causing the frequency of the output signal to change. The frequency shift persists until the phase of the output signal is back into alignment with the reference. In reality, the frequency shift will not be instantaneous, and will result in an overshoot of the phase correction. Eventually, the phase and frequency of the loop will both settle to the correct value, but there will be several perturbations back and forth of the relative phase of the reference and output signal.

[0004] In FIG. 1, for example, a graph shows a voltage over time, which may represent the analog voltage fed into the VCO of the PLL circuit. At a time, t₁, the voltage changes from a steady-state voltage to a voltage greater than the steady-state voltage; at time t₂, the voltage crosses the steady-state voltage line and is less than the steady-state voltage; at time, t₃, the voltage again crosses the steady-state voltage and is greater than the steady-state voltage. The voltage thus oscillates across the steady-state voltage, until finally achieving the steady-state voltage at approximately time, t₁₁.

[0005] The PLL circuit design involves two competing phenomena: locking speed and jitter. The locking speed is how fast the PLL is able to lock the output signal to the reference signal litter is a variation of the signal over time, and may include phenomena such as signal skew and coupled noise. The bandwidth of the PLL, a process variant parameter, together with the VCO phase noise and the reference chain noise, determines what the locking speed and the jitter of the PLL will be. A PLL with a high loop bandwidth provides a fast lock time; however, jitter on the reference signal passes through to the output signal with little or no attenuation. A PLL with a low loop bandwidth filters out the jitter in the reference signal, but is slower to lock the output signal to the reference signal. Such a PLL will also not attenuate the phase jitter of the VCO by much. Knowing the PLL loop bandwidth may facilitate the design of the PLL, whatever the system requirements.

[0006] Some PLL designs place tight restrictions upon the tolerance of the PLL components. This ensures that the PLL loop bandwidth falls within an acceptable window. Component variables within the PLL that contribute to PLL closed loop bandwidth include the tuning sensitivity of the VCO, component values of the loop filter, values programmed Into the feedback divider, and the gain of the phase detector (or phase frequency detector) and the charge pump. Some prior art designs rely upon schemes such as injecting test signals into strategic circuit nodes and measuring the resultant sidebands at the PLL output.

[0016] In accordance with the embodiments described herein, a novel circuit is disclosed for obtaining the loop bandwidth of a phase-locked loop circuit. The novel circuit adjusts a phase of a signal, causing the phase-locked loop circuit to react by adjusting the frequency of a voltage-controlled oscillator to try to recover a phase lock between the signal and a second signal. The novel circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.

[0017] In the following detailed description, reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the described subject matter may be practiced. However, it is to be understood that other embodiments will become apparent to those of ordinary skill in the art. The following detailed description is, therefore, not to be construed in a limiting sense.

[0018] FIG. 2 is a block diagram of a novel circuit 50, according to some embodiments. The novel circuit 50 includes a phase-locked loop (PLL) circuit 20 and loop bandwidth calibration logic 30. As described below, the loop bandwidth calibration logic 30 generates a time value, or duration, from which the closed loop bandwidth of the PLL 20 may be inferred. The time value thus enables system designers to automatically or manually calibrate the PLL 20 according to the system design.

[0019] The closed loop of the PLL circuit 20 includes a phase frequency detector 10, a charge pump 12, a loop filter 14, a voltage-controlled oscillator (VCO) 18, and a programmable divider 16. A reference signal, s_ref, having a frequency, f_ref, and a phase, φ_ref, is received into the phase frequency detector 10 while the VCO 18 generates an output signal, s_out, having a frequency, f_out and a phase, φ_out. During operation, the output signal, s_out, becomes locked with the reference signal, s_ref, such that the output phase, φ_out, is substantially similar to the reference phase, φ_ref. The novel circuit 50 may be operable with PLL circuits having fewer or more features than those specifically depicted in FIG. 2.

[0020] The phase frequency detector 10 receives the reference signal, s_ref, as well as the output signal, s_out, the latter of which may have been modified by the programmable divider 16 (shown as s_feedback) before being received into the phase frequency detector 10. The phase frequency detector 10 thus compares the two signals, s_ref and s_feedback. When the two signals are substantially similar in phase, the PLL circuit 20 is locked. When the two signals are not substantially similar in phase, the phase frequency detector 10 generates a voltage pulse whose duration is proportional to the difference in phase between s_ref and s_feedback, in other words, a difference between φ_ref and φ_feedback. Where φ_ref is greater than φ_feedback an up pulse (p_up) is generated; where φ_ref is less than φ_feedback, a down pulse (p_down) is generated.

[0021] The charge pump 12 receives the voltage pulse, p_up or p_down, from the phase frequency detector 10 and converts the pulse into a current pulse, i. The current pulse, i, is then sent to the loop filter 14. There, the current pulse is converted into an analog voltage, v. The loop filter 14 also filters out high-frequency noise transmitted to the VCO 18. The analog voltage controls the frequency of an oscillator, updating the characteristics of the output signal, s_out. The output signal, s_out, is fed into the programmable divider 16, to generate the signal, s_feedback, which is fed back into the phase frequency detector 10, for subsequent comparison with the reference signal, s_ref. The closed loop of the PLL 20 is thus completed.

[0022] The PLL correction continues until the reference signal, s_ref, and the feedback signal, s_feedback, are substantially similar in phase. At this point, the PLL 20 is said to be in phase lock with the reference signal, s_ref. In this state, the phase frequency detector 10 produces short charge refill pulses (p_up or p_down) of substantially equal magnitude every reference period. This maintains the locked state, but linearizes the response of the phase detector to prevent a dead zone near the locked state. A dead zone is a band where the charge pump does not show any response to small deviations in phase difference between the reference signal, s_ref, and the feedback signal, s_feedback. Dead zones are caused by finite turn-on times of the charge pump. Use of short refill pulses of substantially equal magnitude and opposite sign ensures that the charge pumps have time to turn on, eliminating the dead zone.

[0023] From control systems theory, it is known that the timed step response and frequency bandwidth of a closed loop system are related. This is so provided that the step applied to the control system does not cause the control system to operate outside its linear operating range. Thus, by measuring the time it takes for the PLL to overshoot in response to a step change in input phase, it is possible to measure of the PLL's closed loop bandwidth. The loop bandwidth calibration logic 30 in FIG. 2 is designed with this principle in mind.

[0024] In FIG. 2, the loop bandwidth calibration logic 30 is shown coupled to the programmable divider 16 and the phase frequency detector 10. The loop bandwidth calibration logic 30 is depicted more fully in the block diagrams of FIGS. 3A and 3B, according to some embodiments. The logic 30 includes phase overshoot detection logic 26, a counter 24, and adjust logic 28. A clock 22 controls the counter 24, which generates a time value, T_cal. The logic elements of the loop bandwidth calibration logic are representative of the functional aspects of the logic 30, and are not necessarily indicative of its actual structure. Each of these functional units is described in more detail in the description of FIG. 4, below.

[0025] The loop bandwidth calibration logic 30 operates by modifying either the feedback phase, φ_feedback (FIG. 3B), or the reference phase, φ_ref (FIG. 3A), of a PLL that is in its stable state (“locked stage”). The modification will cause the PLL 20 to commence recovery of the signal, as described above. The loop bandwidth calibration logic 30 calculates the time it takes for the PLL 20 to reach what is known herein as an “overshoot stage” of operation. The time, or duration, of the PLL loop bandwidth may then be used to automatically or manually calibrate the PLL 20 according to system design specifications.

[0026] FIG. 5 is a timing diagram depicting three phases of the PLL operation: a locked stage, a recovery stage, and an overshoot stage. The overshoot stage is a time period in which the PLL 20 has achieved a “lock” between the phases, φ_ref and φ_feedback, of the signals, s_ref and s_feedback, as described above. The recovery stage is a time period in which the PLL 20 has identified a mismatch between the phase signals, φ_ref and φ_feedback and is changing the voltage, v, that is fed into the VCO 18, causing the phase signal, φ_feedback to track the phase signal, φ_ref. The recovery stage, however, ends when the voltage, v, which is fed into the VCO 18 changes from being greater than a steady-state voltage to being less than a steady-state voltage (or vice-versa). In other words, the voltage crosses a steady-state voltage and changes from a phase lead to a phase lag, or vice-versa. For example, in FIG. 1, such a steady-state voltage crossing first occurs at time, t₂, then occurs subsequently at times t₃, t₄, t₅, t₆, t₇, etc. (Alternatively, the recovery stage may be described as a period of time between when the phase-locked loop is in the locked stage and when the voltage, v, fed into the VCO 28 first reaches its steady-state value.) At the steady-state crossing point, the PLL 20 is in a first overshoot stage. Although not depicted in FIG. 5, there may be subsequent overshoot stages before the phase signals, φ_ref and φ_feedback, become locked. The loop bandwidth calibration logic 30 thus measures the length (time) of the recovery stage of the PLL 20.

[0027] In FIG. 4, flow diagram 200 shows the operation of the novel circuit 50, including the loop bandwidth calibration logic 30, according to some embodiments. The operations depicted in the flow diagram 200 may occur in an order different than is depicted, and some operations may be combined or performed simultaneously. System designers of ordinary skill in the art will recognize a number of possible implementations represented in the flow diagram 200 of FIG. 4.

[0028] In the embodiment of FIG. 3A, the reference phase, φ_ref, is adjusted; in the embodiment of FIG. 3B, the feedback phase, φ_feedback is adjusted. Both embodiments are described herein. In FIG. 3A, the adjust logic 28 of the loop bandwidth calibration logic 30 sends an adjustment signal to an inverter 32, indicating that the phase, φ_ref, of the reference signal, s_ref, is to be changed (block 202). (Although shown in FIG. 3A as being inside the phase frequency detector 10, the inverter 32 may be thought of as part of the adjust logic 28.) This causes the phase, φ_ref, to change to a new signal, shown in FIG. 3A as φ_adjust1 (block 204). The adjustment to the signal may vary. In the embodiment of FIG. 3, the phase, φ_ref, is inverted, for a 180° shift in the φ_adjust1 signal. However, the phase, φ_ref, may be adjusted by amounts other than 180°. In FIG. 3B, the programmable divider 16 is shown with an inverter 46. The adjust logic 28 sends a signal to the inverter 46, causing the phase of the feedback signal, φ_feedback, to be adjusted (shown in FIG. 3B as φ_adjust2). Again, the adjustment may be by an amount other than 180°. Thus, in the first example (FIG. 3A), φ_ref is replaced with φ_adjust1; in the second example (FIG. 3B), φ_feedback is replaced with φ_adjust2. For either adjustment, the change in phase of one of the signals being compared by the phase frequency detector 10 causes the PLL 20 to leave the locked phase and enter the recovery stage. Accordingly, the counter 24 is reset (block 206), allowing the loop bandwidth calibration logic 30 to track the recovery stage duration. The counter 24 is controlled by a clock 22, whose frequency may be adjusted according to the desired level of accuracy. The counter 24 increments at each cycle of the clock 22 (block 208).

[0029] During the recovery stage, the voltage pulses p_up (p_down) fed into the charge pump 12 expand, indicating that the signals, s_adjust1 and s_feedback (or s_ref and s_adjust2), are not locked (block 210). In the timing diagram of FIG. 5, the phase, φ_feedback, lags the phase, φ_ref, by 180°; the up pulse, p_up, fed into the charge pump 12 is wide while the down pulse, p_down, fed into the charge pump is small. The charge pump 12 converts the pulse into a current pulse, i, which is sent to the loop filter 14. The loop filter 14 integrates the current pulse, causing the voltage, v, into the VCO 18 to be incremented (decremented), which, in turn, causes the signal, s_out, to increase (decrease) (block 212).

[0030] At some point, the voltage, v, being fed into the VCO 18 will be too great, causing the PLL 20 to enter the overshoot stage (block 214). This is because the PLL 20 is under-damped. (Recall from FIG. 1 the voltage characteristic of an under-damped system.) In FIG. 5, the timing diagram shows that the phase, φ_ref, leads the phase, φ_feedback, during the recovery stage. Once the PLL 20 is in the overshoot stage, the phase, φ_feedback, slightly leads the phase, φ_ref. Thus, the voltage being fed into the VCO 18 goes from being greater than the steady-state voltage to becoming less than the steady-state voltage (or vice-versa). Once the PLL 20 is in the overshoot stage, the counter 24 is stopped (block 216). Accordingly, the loop bandwidth calibration logic 30 generates a time value, T_cal, from which the loop bandwidth of the PLL 20 may be inferred.

[0031] Once the loop bandwidth of the PLL is known, the adjustable features of the PLL 20 may be modified. This may be done automatically or manually, as desired. The PLL closed loop bandwidth is proportional to the current, i, of the charge pump 12. The charge pump 12 may include some programmable registers that enable its characteristics to be changed. Accordingly, in some embodiments, once the PLL loop bandwidth is known, the characteristics of the charge pump 12 may be changed, then a new PLL loop bandwidth may be calculated. In this manner, it is possible to conform the PLL 20 to the desired design specifications. Other PLL components may be modified, as desired, using the PLL loop bandwidth as a guide for calibrating the PLL.

[0032] The novel circuit 50 provides several benefits, according to some embodiments. The loop bandwidth calibration logic 30 involves minimal additional hardware for automatically obtaining the loop bandwidth of the PLL 20. Thus, the design adds little to the die area or power consumption of the PLL circuit 20. Further, the PLL 20 may be calibrated during system design, rather than relying upon factory trimming of components. This may reduce the production time and maximize the manufacturing throughput, in some embodiments. The calibration of the PLL 20 may be repeated at will, such as following a change in the operating conditions, such as when the temperature of a device changes. Also, the accuracy of the PLL loop bandwidth calculation may be as high as desired, limited by the calibration time (frequency of the clock 22) and the length of the counter 24 (FIG. 3).

[0033] FIG. 6 is a flow diagram 300 depicting a method for using the novel circuit 50, according to some embodiments. As described above, the novel circuit 50 is capable of inferring the closed loop bandwidth of the PLL 20 (block 302), based upon the calculated duration of the recovery stage of the PLL. From this information, the system designer is able to adjust one or more parameters of the PLL circuitry, such as the charge pump 12 (block 304). The PLL loop bandwidth may again be calculated (block 306). This process may be repeated until the PLL loop bandwidth meets the system specification (block 308).

[0034] The value of being able to gauge the closed loop bandwidth of the PLL 20 to optimize the bandwidth has several benefits, according to some embodiments. For example, the settling time of the PLL may be accurately controlled. This may guarantee carrier frequency accuracy in packet data systems, as one example. The PLL loop bandwidth may be adjusted to accurately convey modulation. The PLL loop bandwidth may be adjusted to match another control loop, such as a loop conveying amplitude information. The PLL loop bandwidth may be adjusted to minimize the sum contribution of all PLL noise sources. The PLL loop bandwidth may be calculated again and again, for whatever purpose.

[0035] Some system designs employ “polar transmission schemes”in order to extend the battery life of a portable transceiver. Such transmitters rely upon splitting the signal modulation into amplitude and phase components, which are processed in separate loops and combined at the power amplifier. The accurate control and matching of the PLL loop bandwidth in the novel circuit 50 may be applied to such designs to efficiently ensure modulation accuracy.

[0036] FIG. 7 is a block diagram of a processor-based system 400 utilizing the novel circuit 50 of FIG. 2, according to some embodiments. The processor-based system 400 includes a processor 402 coupled to a memory 404 and a chipset 406. The chipset 406 may support a myriad of functions not depicted in FIG. 7 for simplicity. One of the functions supported by the chipset is a wireless transceiver 408 coupled to a dipole antenna 410. The wireless transceiver 408 is controlled by PLL that is automatically calibrated using the novel circuit 50. The processor-based system 400 represents one example of the many applications in which the novel circuit 50 may be used.

[0037] While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the disclosed subject matter.