US 7,499,358 B2Grant
Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
Issue Date:2009-03-03
•20 Claims
•25 Drawing Sheets
Abstract
There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by read circuitry to read the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.
Metadata
Assignee
- Innovative Silicon ISi SA
Inventor
- Philippe Bauser
Application Information
Application Number:US 12/070,499
Filing Date:2008-02-19
Priority Date:2005-09-19
Art Unit:2824
Classifications
IPC:
G11C7/02
Patent Drawings (25 sheets)
Description
Related Application
[0001] This application is a divisional application of application Ser. No. 11/515,667, filed Sep. 5, 2006 now U.S. Pat. No. 7,355,916. This application and the '667 application claim priority to U.S. Provisional Application Ser. No. 60/718,417, entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell Having an Electrically Floating Body Transistor, and Device Implementing Same”, filed Sep. 19, 2005. The contents of this provisional application are incorporated by reference herein in their entirety.
Background
[0002] The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell, array and device; and more particularly, in one aspect, to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body wherein an electrical charge is stored therein.
[0003] There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.
[0004] One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
[0005] With reference to FIGS. 1A , 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.
[0006] Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
[0007] The memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18. (See, for example, the N-channel transistor in FIGS. 2A and 2B ). In this regard, conventional write techniques may accumulate majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 by, for example, impact ionization near source region 20 and/or drain region 22. (See, FIG. 2A ). The majority carriers 30 may be emitted or ejected from body region 18 by, for example, forward biasing the source/body junction and/or the drain/body junction. (See, FIG. 2B ).
[0008] Notably, for at least the purposes of this discussion, logic high or logic “1” corresponds to, for example, an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic low or logic “0”. In contrast, logic low or logic “0” corresponds to, for example, a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or logic “1”.
[0009] Conventional reading is often performed by applying a small drain bias and a gate bias above the transistor threshold voltage. A sense amplifier senses, detects and/or samples the drain current which is determined or influenced by the charge stored in the electrically floating body of the transistor of the memory cell thereby giving a possibility to distinguish between the data states (for example, state “1” and state “0”). A floating body memory device may have two different current “states” corresponding to the two different logical states “1” and “0”.
[0010] Notably, when the difference in electrical characteristic between two states is small and/or variable, a tracking reference may be employed for correct recovery of the stored digital data during a read operation. In this regard, a midpoint reference is often used so as to position the reference halfway between the characteristics of two adjacent digital states. This midpoint reference is classically constructed using two memory cells storing the two adjacent digital states. For instance, in a dynamic random access memory (DRAM) making use of Silicon-On-Insulator (SOI) floating body memory cells, a cell storing state “0” and a cell storing state “1” are placed in parallel and biased appropriately such as to provide a sum of the two corresponding currents. This term is then divided by two to generate a midpoint reference level used to discriminate the state of a read memory cell inside the array. (See, FIG. 3 ).
[0011] However, unavoidable variations typically exist in commercial devices because of mismatch in memory cell characteristics as well as mismatch in the transistors that comprise the circuitry (for example, the sense amplifier circuitry) which is responsible for sensing, sampling, detecting and/or discriminating between the data states. This tends to reduce the margin of operation (for example, the read window margin). To minimize this issue, a common practice is the use of a plurality of reference cells in parallel, thus decreasing the overall variance of the reference characteristic. (See, FIG. 3 ).
[0012] Notably, the concerns regarding mismatch are often exacerbated when implementing deep sub-micron technologies. It has been reported that the variance of an electrical characteristic increases with the absolute value of the electrical characteristic (although diminishing in relative terms). (See for example: “Understanding MOSFET Mismatch for Analog Design” by Drennan et al., IEEE J. Solid-State Circuits, vol. 38, pp. 450-456, March 2003). As a result, the variance of the various electrical characteristics corresponding to the different digital states may not be constant. With that in mind, in relation to the SOI floating body DRAM example, these current corresponding to a read operation of the memory cells storing state “1”, the reference, and state “0” affected by their respective variance and measured at the sense amplifier level are depicted in FIG. 4 . Prior art midpoint reference positioning may also exhibit the drawback of having unequal read margins toward state “0” and state “1”, this latter case demonstrates a lower margin. This lower margin may eventually translate into more failures during the read operations (and/or an overall reduction in the read window margin).
Summary of the Inventions
[0013] There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.
[0014] In one aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) including a reference current generation circuit to generate a reference current for data sensing circuitry. In one embodiment, the reference current generation circuit comprises a plurality of reference networks, wherein each reference network includes a current driver, including a transistor having an output which is coupled to a signal line, and a reference cell network. The reference cell network includes a plurality of reference cells, and wherein each reference cell is programmed to one of a plurality of data states (for example, via storing one of the plurality of data states in an electrically floating body region of a transistor). In this embodiment, (i) a majority of the reference cells of at least one of the reference cell networks are programmed to a second data state and (ii) a minority of the reference cells of the at least one of the reference cell network is/are programmed to a first data state. In addition, an equal number of the reference cells of at least one of the reference cell networks are programmed to a first data state and to a second data state. The reference current generation circuit also includes a reference current driver including a transistor which is coupled to the plurality of reference networks via the signal line to generate the reference current.
[0015] In one embodiment, a majority of the reference cells of a plurality of the reference cell networks are programmed to the second data state and a minority of the reference cells of the at least one of the reference cell network is/are programmed to the first data state. In another embodiment, all of the reference cells of the at least one reference cell network are programmed to the second data state.
[0016] The reference current generation circuit may also include control data signal lines, coupled to the at least one reference cell network, to program the reference cells of the at least one reference cell network. A memory circuitry (for example, one or more registers and/or fuses or anti-fuses), coupled to the control data signal lines, may store control data which is applied to the control data signal lines to program the reference cells of the at least one reference cell network. The reference current generation circuit may include control circuitry, coupled to the control data signal lines, to determine the control data which is applied to the control data signal lines to program the reference cells of the at least one reference cell network.
[0017] In one embodiment, the control data may be fixed. In another embodiment, the control data may be applied to the control data signal lines to program the reference cells of the at least one reference cell network during start-up and/or initialization and/or operation.
[0018] In one embodiment, the device geometry of the transistor of the current driver is more than twice the geometry device of the transistor of the reference current driver. In one embodiment, the device geometry of the transistor of each current driver is at least substantially the same. In another embodiment, the device geometry of the transistor of the current driver of at least one reference network is substantially different from a device geometry of the transistor of the current driver of each of a plurality of the reference networks.
[0019] In another aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) including a reference current generation circuit to generate a reference current for data sensing circuitry, the reference current generation circuit includes a plurality of reference networks and a reference current driver coupled to the plurality of reference networks via a signal line to generate the reference current. In this aspect of the present inventions, each reference network includes: (i) a current driver having an output coupled to the signal line, and (ii) a reference cell network wherein the reference cell network includes a plurality of reference cells. Further, in this aspect of the present inventions, each reference cell is programmed in (i) a first data state which corresponds to a first charge in the body region of the transistor of the reference cell, or (ii) a second data state which corresponds to a second charge in the body region of the transistor of the reference cell. Moreover, a majority of the reference cells of at least one of the reference cell networks are programmed to a second data state and a minority of the reference cells of the at least one of the reference cell network is/are programmed to a first data state. In addition, an equal number of the reference cells of at least one of the reference cell networks are programmed to a first data state and to a second data state.
[0020] In one embodiment, a majority of the reference cells of a plurality of the reference cell networks are programmed to the second data state and a minority of the reference cells of the at least one of the reference cell network is/are programmed to the first data state. In another embodiment, all of the reference cells of the at least one reference cell network are programmed to the second data state.
[0021] The reference current generation circuit may also include control data signal lines, coupled to the at least one reference cell network, to program the reference cells of the at least one reference cell network. A memory circuitry (for example, one or more registers and/or fuses or anti-fuses), coupled to the control data signal lines, may store control data which is applied to the control data signal lines to program the reference cells of the at least one reference cell network. The reference current generation circuit may include control circuitry, coupled to the control data signal lines, to determine the control data which is applied to the control data signal lines to program the reference cells of the at least one reference cell network.
[0022] In one embodiment, the control data is fixed. The control data may be applied to the control data signal lines to program the reference cells of the at least one reference cell network during start-up and/or initialization and/or operation.
[0023] In one embodiment, the device geometry of the transistor of the current driver is more than twice the geometry device of the transistor of the reference current driver. In another embodiment, the device geometry of the transistor of each current driver is at least substantially the same. In yet another embodiment, the device geometry of the transistor of the current driver of at least one reference network is substantially different from a device geometry of the transistor of the current driver of each of a plurality of the reference networks.
[0024] In yet another aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) including a reference current generation circuit to generate a reference current for data sensing circuitry, the reference current generation circuit including a plurality of reference networks, wherein each reference network includes a current driver including a transistor having an output which is coupled to a signal line and a reference cell network. The reference cell network, in this aspect of the invention, includes a plurality of reference cells, and wherein each reference cell is programmed to one of a plurality of data states and includes a transistor having an electrically floating body region. Each transistor of each reference cell is programmed in (i) a first data state which corresponds to a first charge in the body region of the transistor of the reference cell, or (ii) a second data state which corresponds to a second charge in the body region of the transistor of the reference cell. Further, each transistor of a majority of the reference cells of at least one of the reference cell networks is programmed to the second data state and each transistor of a minority of the reference cells of the at least one of the reference cell network is/are programmed to the first data state. The reference current generation circuit further includes a reference current driver including a transistor which is coupled to the plurality of reference networks via the signal line to generate the reference current for the data sensing circuitry.
[0025] In one embodiment, the transistors of an equal number of the reference cells of a plurality of reference cell networks are programmed to a first data state and to a second data state. In another embodiment, the transistors of all of the reference cells of the at least one reference cell network are programmed to a second data state.
[0026] The reference current generation circuit may further include memory circuitry may store control data which is applied to at least one reference cell network to program the transistor of each reference cell of at least one reference cell network. Indeed, the reference current generation circuit may include control circuitry to determine the control data which is applied to at least one reference cell network to program the transistor of each reference cell of at least one reference cell network.
[0027] In one embodiment, the control data is fixed. The control data may be applied to the control data signal lines to program the reference cells of the at least one reference cell network during start-up and/or initialization and/or operation. Indeed, the data state of the transistor of each reference cell of the plurality of reference cell networks may be fixed.
[0028] In one embodiment, the device geometry of the transistor of the current driver is more than twice the geometry device of the transistor of the reference current driver. In another embodiment, the device geometry of the transistor of each current driver is at least substantially the same. In yet another embodiment, the device geometry of the transistor of the current driver of at least one reference network is substantially different from a device geometry of the transistor of the current driver of each of a plurality of the reference networks.
[0029] In another aspect, the present inventions are directed to a reference current generation circuit to generate a reference current for data sensing circuitry disposed on an integrated circuit device (for example, logic or discrete memory device). The reference current generation circuit of this aspect of the inventions includes a plurality of reference networks, wherein each reference network includes (i) a current driver including a transistor having an output which is coupled to a signal line, wherein the transistor of each current driver includes a device geometry and (ii) a reference cell network wherein the reference cell network includes a plurality of reference cells. The reference cells are programmed to one of a plurality of data states and each include a transistor having an electrically floating body region wherein each transistor is programmed in (i) a first data state which corresponds to a first charge in the body region of the transistor of the reference cell, or (ii) a second data state which corresponds to a second charge in the body region of the transistor of the reference cell. The reference current generation circuitry further includes a reference current driver including a transistor which is coupled to the plurality of reference networks via the signal line to generate the reference current for the data sensing circuitry. In this aspect of the present inventions, the device geometry of the transistor of each current driver is more than twice the geometry device of the transistor of the reference current driver.
[0030] In one embodiment, the transistor of each current driver of each reference network includes a device geometry which is at least substantially the same.
[0031] In another embodiment, each transistor of a majority of the reference cells of at least one of the reference cell networks is programmed to the second data state and each transistor of a minority of the reference cells of the at least one of the reference cell network is/are programmed to the first data state. Indeed, in another embodiment, an equal number of the transistors of the reference cells of the reference cell networks are programmed to a first data state and to a second data state.
[0032] Notably, the present inventions may be implemented in conjunction with any memory cell technology, whether now known or later developed. For example, the memory cells may include one or more electrically floating body transistors, one transistor-one capacitor architecture, electrically floating gate transistors, junction field effect transistors (often referred to as JFETs), or any other memory/transistor technology whether now known or later developed. All such memory technologies are intended to fall within the scope of the present inventions.
[0033] Further, the present inventions may be implemented in conjunction with any type of memory (including discrete or integrated with logic devices), whether now known or later developed. For example, the memory may be a DRAM, SRAM and/or Flash. All such memory types are intended to fall within the scope of the present inventions.
[0034] Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner. Indeed, many other embodiments, which may be different from and/or similar to, the embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions.
Brief Description of the Drawings
[0035] In the course of the Detailed Description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions.
[0036] Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.
[0037] FIG. 1A is a schematic representation of a prior art electrically floating body SOI DRAM array including a plurality of memory cells, each memory cell including an electrically floating body transistor (N-type transistor);
[0038] FIG. 1B is a three dimensional view of an exemplary prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS);
[0039] FIG. 1C is a cross-sectional view of the prior art memory cell of FIG. 1B , cross-sectioned along line C-C′;
[0040] FIGS. 2A and 2B are exemplary schematic illustrations of the charge relationship, for a given data state, of the floating body, source and drain regions of a prior art memory cell having an electrically floating body transistor (N-type transistor);
[0041] FIG. 3 is a schematic representation of a prior art reference current generator which is combined by connecting a plurality of midpoint current generators in parallel;
[0042] FIG. 4 is an illustration of the current variance pertaining to state “1”, reference, and state “0” in an electrically floating body SOI DRAM in conjunction with the impact of, for example, various mismatching and/or manufacturing tolerances of the memory cell, reference current generation, and/or transistors of the sense amplifier;
[0043] FIG. 5 is a graphical representation of the evolution of one-sigma margins on state “1” and state “0” as a function of the mismatch proportionality coefficient;
[0044] FIG. 6 is a schematic representation of one embodiment of one aspect of the present inventions whereby the reference current level (employed during a read operation) is adjusted, set, determined and/or controlled via transistor “ratioing”, according to an exemplary embodiment of an aspect of the present inventions;
[0045] FIG. 7 is a schematic block diagram of an exemplary embodiment of an integrated circuit device including, among other things, a memory cell array, data sensing circuitry, reference current generation circuitry, and memory cell selection and control circuitry, according certain aspects of the present inventions;
[0046] FIG. 8 is a schematic representation of an exemplary embodiment of reference current generation circuitry including a plurality of pairs of reference cells, which are programmed and/or controlled via control data, providing digital control of the reference current level (employed during a read operation) according to an exemplary embodiment of an aspect of the present inventions;
[0047] FIGS. 9A-9D are schematic representations of other exemplary embodiments of reference current generation circuitry (including a plurality of pairs of reference cells, which are programmed and/or controlled via control data) in conjunction with a control circuitry and/or memory circuitry, according to an exemplary embodiment of an aspect of the present inventions;
[0048] FIG. 10 is an exemplary algorithm that may be employed to determine a value of the digital control word which controls, impacts and/or determines the level of the reference current employed during a read operation;
[0049] FIGS. 11A-11E are schematic representations of certain embodiments of reference current generation circuitry (including a plurality of reference current generation circuits) in conjunction with, for example, data sensing circuitry, memory cell array, a control circuitry and/or memory circuitry, according to an exemplary embodiment of an aspect of the present inventions;
[0050] FIGS. 12A and 12B are schematic block diagram illustrations of exemplary integrated circuit devices in which the memory cell array (and certain peripheral circuitry) may be implemented, according to certain aspects of the present inventions, wherein FIG. 12A is a logic device (having logic circuitry and resident memory) and FIG. 12B is a memory device (having primarily of a memory array);
[0051] FIGS. 13 and 14A are schematic representations of exemplary embodiments of reference current generation circuitry having a plurality of current drivers having different device geometries, according to an exemplary embodiment of an aspect of the present inventions; and
[0052] FIGS. 14B and 14C are schematic representations of exemplary embodiments of reference current generation circuitry including a plurality of pairs of reference cells, wherein (among other things) at least one pair of reference cells is programmed and/or controlled to store the same logic state, according to an exemplary embodiment of an aspect of the present inventions.
Detailed Description
[0053] There are many inventions described and illustrated herein. In one aspect the present inventions are directed to techniques for reading, controlling and/or operating a memory cell, array, architecture and/or integrated circuit device wherein the memory cell(s) include electrically floating body transistors in which an electrical charge is stored in the body of the transistor. The present inventions are also directed to memory cell, array, architecture and device that implement circuitry to implement such reading, controlling and/or operating techniques. Notably, the memory cell and/or memory cell array may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory).
[0054] In one aspect, the present inventions control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., the absolute or relative amount) of the reference current which is employed by sensing circuitry during a read operation of one or more memory cells. In this regard, assuming Gaussian distributions and a conventional, general or typical mismatch model whereby the standard deviation affecting a characteristic is proportional to its absolute value, the standard deviation of state “1”, reference state, and state “0” may be expressed as:
-
- [0055] For state “1”, a level of ξ1 affected by a standard deviation αξ1
- [0056] For the reference state, a level of ξRef affected by a standard deviation αξRef/√N (N Pairs of Reference Placed in Parallel)
- [0057] For state “0”, a level of ξ0 affected by a standard deviation αξ0
[0058] With that in mind, where the reference level is placed classically midway between state “1” and state “0” levels (i.e. if ξRef=(ξ1+ξ0)/2), the one sigma difference between state “1” and “reference” distribution levels may be characterized as:
Δ1−Ref=ξ1(0.5−α(1+1/√N))−ξ0(0.5+α/2√N)
while the one sigma difference between the “reference” and “0” distribution levels may be characterized as:
ΔRef−0=ξ1(0.5−α/2√N)−ξ0(0.5+α(1+1/√N))
The particular case where α=0 leads to symmetrical one-sigma distribution differences equal to:
Δ1−Ref=ΔRef−0=0.5*(ξ1−ξ0).
Δ1−Ref=ξ1(0.5−α(1+1/√N))−ξ0(0.5+α/2√N)
while the one sigma difference between the “reference” and “0” distribution levels may be characterized as:
ΔRef−0=ξ1(0.5−α/2√N)−ξ0(0.5+α(1+1/√N))
The particular case where α=0 leads to symmetrical one-sigma distribution differences equal to:
Δ1−Ref=ΔRef−0=0.5*(ξ1−ξ0).
[0059] Setting α=0 may be considered an “ideal” situation, and under this circumstance, the “positioning” the reference level midway between state “1” and state “0” levels is “ideal or “perfect”. However, in practice or reality α≠0, with reference to the relationships set forth above, as well as illustrated in the chart/graph of FIG. 5
Δ1−Ref−ΔRef−0.
As such, more reading failures are typically expected when reading memory cells storing a state “1” than when reading memory cells storing a state “0”.
Δ1−Ref−ΔRef−0.
As such, more reading failures are typically expected when reading memory cells storing a state “1” than when reading memory cells storing a state “0”.
[0060] The present inventions control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry. All such implementations and techniques, whether now known or later developed, are intended to fall within the present inventions.
[0061] In one embodiment, the reference current level (employed during a read operation) is adjusted, set, determined and/or controlled via transistor “ratioing”. Here, the division by 2 employed to obtain the midway reference in a conventional approach is replaced by a division by “k” (k>2) via current source scaling. The determination of “k” may be controlled, set and/or a function of, for example, the characteristic of the design and its technology implementation.
[0062] For example, with reference to FIG. 6 , in one embodiment, reference current generator circuitry 36 includes a plurality of reference networks 38a-38t. In this embodiment, reference networks 38a-38t include current driver 40a-40t, respectively. Each current driver 40a-40t includes a transistor having a geometry multiplier of “n”. In this regard, nX makes reference to an “n” times a basic geometry (for example, “n” times a width/length ratio of “X”).
[0063] In this embodiment, each reference network 38 includes a reference cell circuit 42 having a plurality of reference cells 42xy (for example, reference network 38a includes reference cell circuit 42a having more reference cells 42a1 and 42a2). Notably, in the illustrative embodiment, each reference cell circuit 42 includes reference cell 42x1 (for example, an electrically floating body type transistor) which is programmed to logic “1” and reference cell 42x2 (for example, an electrically floating body type transistor) which is programmed to logic “0”. The reference cells 42x1 and 42x2 may be programmed via switch circuitry 44x. In this regard, each reference cell 42x may be accessed individually by controlling switch circuitry 44x to isolate one or the other of reference cells 42x and applying appropriate programming voltages to the gate, drain region and source region of the transistor of reference cell 42.
[0064] Notably, as mentioned above, the present inventions may be implemented in conjunction with any memory cell technology, whether now known or later developed. For example, the memory cells may include one or more electrically floating gate transistors, one transistor-one capacitor architecture (1T-1C), JFETS, electrically floating body transistors, or any other memory/transistor technology whether now known or later developed. Typically, reference cells 42 are the same as or representative of the memory cell employed in the integrated circuit device (for example, a logic device, such as, a microcontroller or microprocessor, or a memory device, such as, a discrete memory). Indeed, such reference cells 42 are often disposed in the memory cell array.
[0065] The reference current generator circuitry 36 further includes reference current driver 46. The current driver 46 includes a geometry multiplier of “m” and, as such, in this configuration generates reference current 48 which is “Iref/k” where k=n/m and k>2. The reference current 48 is provided to data sensing circuitry 50 (for example, a cross-coupled sense amplifier). The data sensing circuitry 50 employs reference current 48 to determine, sense and/or sample the data state of a memory cell 12 having an electrically floating body transistor 14.
[0066] In one embodiment, data sensing circuitry 50 includes data sense amplifier circuitry, for example, circuitry including a cross-coupled sense amplifier. Briefly, with reference to FIG. 7 , in one embodiment, the data sense amplifier circuitry receives at least one bit line (having a plurality of memory cells 12 coupled thereto) and the reference current generated by reference generator circuitry 36. The data sense amplifier circuitry senses the data state stored in memory cell 12 and/or writes-back data into memory cell 12. In this regard, the data sense amplifier circuitry may compare the current from the selected memory cell to the reference current generated by reference generator circuitry 36. From that comparison, it may be determined whether memory cell 12 contained logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18).
[0067] Notably, the present inventions may employ any type or form of data sense amplifier circuitry and/or data sensing circuitry 50, whether now known or later developed, to read the data stored in memory cells 12 and/or write data in memory cells 12. For example, in one embodiment, the data sense amplifier circuitry may be a cross-coupled type sense amplifier as described and illustrated in the Non-Provisional U.S. Patent Application Ser. No. 11/299,590 (U.S. Patent Application Publication US 2006/0126374), filed by Waller and Carman, on Dec. 12, 2005, and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read Data from Memory Cells”, the application being incorporated herein by reference in its entirety.
[0068] It may be advantageous to implement or employ a digital technique to adjust, define, set, determine and/or control the reference voltage or current level used to read the state of the memory cell including adjusting defining, setting, determining and/or controlling the reference voltage or current level applied to the sense amplifier in such a way as to adjust, define, set, determine and/or control the weight on the memory cells storing state “0” relative to the memory cells storing state “1”.
[0069] For example, with reference to FIG. 8 , reference current generator circuitry 36 includes one or more selectively programmable reference cells (for example, a pair of reference cells) that are programmed, controlled and/or configured using control data (for example, a control bit, bits or word). In one embodiment, reference cells are programmed, controlled and/or configured to opposite data states (for example, where there are two reference cells, one of the/reference cells is programmed to logic state “1” and another reference cell is programmed to logic state “0”). In another embodiment, reference cells may be programmed, controlled and/or configured to the same data state (for example, where there are two reference cells, both reference cells are programmed to logic state “1” or logic state “0”).
[0070] Notably, in certain embodiments, the current generated by a reference cell programmed to logic state “1” is greater than the current generated by a reference cell programmed to logic state “0”. Under these circumstances, it may be advantageous to lower the reference level (shift, adjust, control and/or change the reference level towards the “0” state) to “re-balance”, control, adjust or shift the read margins. (See, for example, FIG. 4 ). As such, in this embodiment, all (or a majority) of the reference cells 42xx (for example, both reference cell 42xx and reference cell 42xx+1 of reference cell circuit 42x) of one or more of the reference cell circuits 42 are programmed to logic state “0” to adjust, control, shift and/or change the read margins.
[0071] In particular, with reference to FIG. 8 , in one embodiment, reference current generator circuitry 36 includes a plurality of reference networks 38a-38t. Each reference network 38 includes current driver 40 and reference cell circuit 42 having one or more reference cells 42xy (each reference cell including, for example, an electrically floating body type transistor). In this embodiment, current driver 40 includes a geometry multiplier of “n” (for example, 2×). The reference cells 42 may include one or more reference cells 42xy which are similar to (or the same, substantially the same as, representative or substantially representative of) the memory cells of the memory cell array. In this illustrative embodiment, reference network 38 includes an associated pair of reference cells 42x1 and 42x2 each including an electrically floating body type transistor.
[0072] The reference current generator circuitry 36 further includes row line write control circuitry 52 and bit line write control circuitry 54 (circuitry 52 and 54 may be, for example, controllable or configurable signal generators, switches and/or multiplexers). The row line write control circuitry 52 and bit line write control circuitry 54 facilitate programming, controlling and/or configuring of reference cell circuit 42. In this regard, in response to control data (for example, a control bit, bits or word) applied on control signal lines 56, row line write control circuitry 52 and bit line write control circuitry 54 program, control and/or configure reference cell circuit 42 to a given and/or predetermined state. As noted above, in one embodiment, the reference cells of reference cell circuit 42 are programmed, controlled and/or configured to opposite data states (for example, one of the reference cells is programmed to logic state “1” and another reference cell is programmed to logic state “0”). In another embodiment, reference cells of reference cell circuit 42 are programmed, controlled and/or configured to the same data state (for example, where there are two reference cells, both reference cells are programmed to logic state “1” or logic state “0”).
[0073] In one embodiment, one or more bits of the control data may be employed to program, control and/or configure the reference cells of reference cell circuit 42. For example, with reference to FIG. 8 , in response to the one or more control bits, row line write control circuitry 52 and bit line write control circuitry 54 may program, control and/or configure reference cell 42a1 to logic state “1” and reference cell 42a2 to logic state “0”. Alternatively, such control bits may indicate that reference cell 42a1 and reference cell 42a2 are programmed to the same logic state (logic state “1” or logic state “0”). In this embodiment, both reference cells reference cell 42a1 and reference cell 42a2 are written to the same logic state in order to, for example, provide a desired, predetermined and/or suitable weighting such that reference current generator circuitry 36 generates a desired, predetermined and/or suitable reference current 48.
[0074] Where the reference cells of reference cell circuit 42 include electrically floating body transistors that store data states in the electrically floating body region of the transistor, selectively writing logic “1” and logic “0” to a particular reference cell may be implemented by controlling the appropriate or associated bit and word lines and applying suitable writing voltages thereon. Indeed, any technique to program the data state of one or more reference cells, whether now known or later developed, is intended to fall within the scope of the present inventions.
[0075] In particular, in one embodiment, each reference cell circuit 42 includes electrically floating body transistor 42x1 programmed to logic “1” and electrically floating body transistor 42x2 programmed to logic “0”. The transistors 42x1 and 42x2 may be programmed via row line write control circuitry 52 and bit line write control circuitry 54. In this regard, each transistor 42x may be individually accessed, via control data, and appropriate programming voltages applied to the gate, drain region and source region of the electrically floating body transistors 42x1 and 42x2 of reference cell circuit 42.
[0076] With continued reference to FIG. 8 , reference current generator circuitry 36 further includes reference current driver 46. The reference current driver 46 includes a geometry multiplier of “m” (for example, 1×). The reference current 48 is provided to data sensing circuitry 50 (for example, a cross-coupled sense amplifier). The data sensing circuitry 50 employs reference current 48 to determine, sense and/or sample the data state of a memory cell 12 having an electrically floating body transistor 14. The data sensing circuitry 50 is discussed in detail herein, for example, above in relation to the exemplary embodiment of FIG. 6 .
[0077] Thus, where this embodiment is implemented in conjunction with a conventional type data sensing circuitry 50 (which employs a conventional sensing scheme), when connecting N pairs of reference cells 42x to provide reference current 48, the reference current is proportional to the relationship of the device geometry (for example, gate width and/or gate length) of current driver 40 (for example, 2×) and the device geometry (for example, gate width and/or gate length) of reference current driver 46 (for example, 1×). As such, when “r” number of reference cells 42 are set to a first state (for example, logic state “1”) via, for example, “r” control bits which are set to a first state and “k” number of reference cells 42 are set to a second state (for example, logic state “0”) via “k” control bits which are set to a second state, reference current 48, as measured at the sense-amplifier level, may be characterized as:
[0078]
[0079] Notably, in one embodiment, the r+k control bits of the control data may be implemented as a thermometric code. In this embodiment, an important parameter may be the number of bits corresponding to a given or each data state.
[0080] In one embodiment, the programmed states of reference cells 42xy may be altered so that a given reference cell 42xy and/or given reference cell circuit 42 (for example, an associated pair of reference cells 42xy and 42xy+1) are always written to a particular logic state (for example, a pair of reference cells are always or only written to logic state “0”). In this embodiment, the control data may include one or more additional bits which instruct row line write control circuitry 52 and bit line write control circuitry 54 to change and/or swap the data states of the reference cells of a reference cell circuit 42 (for example, swap the data state of a pair of reference cells). In this way, the logic state stored in one or more reference cells 42 may be changed (for example, periodically or intermittently) to enhance the long term stability and “placement” (relative or absolute) of reference current 48.
[0081] With continued reference to FIG. 8 , the control data for controlling and/or configuring reference cell circuits 42 may be fixed and/or predetermined. In one embodiment, the control data may be provided to reference cell bank 58 at start-up/power-up and/or during an initialization sequence. For example, the control data may be determined via a particular configuration of the state of a certain pin or pins on the package of the device (for example, stand-alone memory device or logic device) and/or provided by external circuitry.
[0082] With reference to FIG. 9A , the fixed or predetermined, preset or pre-programmed reference current control word may be permanently, semi-permanently or temporarily (i.e., until re-programmed) by way of memory circuitry 60 (for example, a register, plurality of DRAM, SRAM, ROM, PROM, EPROM, EEPROM cells that are resident on (i.e., integrated in) the device or off-chip (for example, disposed on a memory card on which the device resides). Moreover, memory circuitry 60 may be fuses or anti-fuses which are integrated in the device or off-chip to store the control data.
[0083] With reference to FIG. 9B , in another embodiment, control circuitry 62 may be employed to implement the setting, calibration and/or tuning techniques for one, some or all of the reference cell banks 58 within the device. In this regard, the control data provided to reference cell bank 58 may be determined for one, some or all reference cells 42xy of reference cell circuits 42 of reference cell bank 58. As such, control circuitry 62 may program or re-program one, some or all reference cells 42xy of reference cell circuits 42. The control circuitry 62 may set, calibrate and/or tune one, some or all of reference cells 42xy and/or reference cell circuits 42 of reference cell bank 58 as described immediately above.
[0084] The control circuitry 62 may be, for example, a microprocessor, microcontroller, state machine, discrete logic (for example, CMOS logic), and/or programmable gate array (PGA). The control circuitry 62 may be integrated on the same substrate in which the memory cell and/or memory cell array resides (or is fabricated in). In addition, or in lieu thereof, control circuitry 62 may be integrated on a substrate that is physically separate from (and electrically coupled to or connected with) the substrate in which the associated memory cell and/or memory cell array resides.
[0085] The control circuitry 62 may employ any programming algorithm whether now known or later developed. For example, control circuitry 62 may implement the exemplary control word programming algorithm of FIG. 10 . Notably, in one embodiment, an exemplary algorithm of FIG. 10 may be implemented and/or executed at power up (i.e., before using the memory device), and/or intermittently or periodically during normal operation to compensate for, for example, drift due to temperature variations and/or aging.
[0086] In one embodiment, control circuitry 62 determines and/or calculates the control data. In this embodiment, “initial” control data may be provided at start-up/power-up and/or during an initialization sequence (internally via, for example, memory circuitry 60 (see, for example, FIG. 9C ), and/or externally via, for example, control circuitry 62 which may be stored in memory circuitry 60 (see, for example, FIG. 9D )). Thereafter, control circuitry 62 may determine and/or calculate the control data (and one, some or all of one, some or all of reference cells 42xy and/or reference cell circuits 42 and/or reference cell bank 58 re-programmed) during operation to optimize, enhance, compensate and/or adjust reference current 48. For example, reference current 48 may be adjusted during operation to address and/or compensate for variations in operating conditions (for example, to compensate for aging, changes in temperature, and/or response time parameters or characteristics).
[0087] Further, in yet another embodiment, the control data may be fine-tuned to enhance the performance of the reference current generator circuitry 36. In this regard, after (or during) the performance of an initialization or re-initialization process, the system (via, for example, control circuitry 62) may implement fine adjustments to the predetermined, preset or pre-programmed control data (which is stored in, for example, memory circuitry 60 and/or provided externally). The adjustments to the control data may be accomplished using any techniques. Notably, all techniques for determining, modifying, changing and/or adjusting the control data, whether now known or later developed, are intended to be within the scope of the present inventions.
[0088] For example, in those embodiments where control circuitry 62 programs and/or re-programs one, some or all of reference cells 42xy and/or reference cell circuits 42 of reference cell bank 58, control circuitry 62 may implement a successive approximation approach to determine control data that, in conjunction with reference current generator circuitry 36, provides an optimized, enhanced, compensated and/or adjusted reference current 48. In this embodiment, control circuitry 62 may store the control data in successive approximation registers.
[0089] Notably, in one aspect of the inventions, reference current generator circuitry 36 provides an improved reference current positioning by taking into consideration the sub-micron matching characteristics by, for example, shifting the reference level of electrical characteristic toward the lower magnitude level to provide Δ1−Ref=ΔRef−0 notwithstanding α≠0.
[0090] With reference to FIGS. 7 and 11A , in one embodiment, the integrated circuit device may include reference current generation circuitry 36 which includes a plurality of reference current generation circuits 36a-36x. The reference current generation circuits 36a-36x generate one or more reference currents which are employed by data sense amplifier circuitry of data sensing circuitry 50 to determine the data states of one or more memory cells 12 of a memory cell array 10. In this embodiment, reference current generation circuits 36a-36x may include any of the embodiments of reference current generation circuitry described herein (for example, the exemplary embodiments illustrated in FIGS. 6 , 8 and 9A-9D).
[0091] In one embodiment, the control data employed by reference current generator circuits 36a-x to generate reference currents 48a-x, respectively (via, among other things, reference cell banks 58a-58x, respectively), may be fixed and/or predetermined for one, some or all reference current generator circuits 36a-x. The control data provided to a given bank 58 may be the same or different for other banks 58. In one embodiment, control data may be provided to reference current generator circuits 36a-x at start-up/power-up and/or during an initialization sequence. In this embodiment, control data may be determined via a particular configuration of the state of a certain pin or pins on the package of the device and/or provided by external circuitry.
[0092] Further, with reference to FIG. 11B , the fixed or predetermined, preset or pre-programmed reference current control word may be permanent, semi-permanent or temporary (i.e., until re-programmed) by way of memory circuitry 60. The memory circuitry 60 may be, for example, a register, plurality of DRAM, SRAM, ROM, PROM, EPROM, EEPROM cells that are resident on (i.e., integrated in) the device or off-chip (for example, disposed on a memory card on which the device resides). Moreover, memory circuitry 60 may be fuses or anti-fuses which are integrated in the device or off-chip to store the control data.
[0093] With reference to FIG. 11C , in another embodiment, control circuitry 62 may be employed to implement the setting, calibration and/or tuning techniques for one, some or all of reference cell banks 58a-58x in reference current generation circuits 36a-36x, respectively. In this regard, the control data provided to a given reference cell bank 58 may be determined for one, some or all reference cells of the reference cell circuits of that reference cell bank 58. As such, control circuitry 62 may program or re-program one, some or all reference cells. The control circuitry 62 may set, calibrate and/or tune one, some or all of reference cells and/or reference cell circuits of one, some or all reference cell banks 58a-58x, as described immediately above.
[0094] As noted above, in one embodiment, control circuitry 62 determines and/or calculates the control data. In this embodiment, an “initial” reference current control word may be provided at start-up/power-up and/or during an initialization sequence (internally via, for example, memory circuitry 60 (see, for example, FIG. 11D ), and/or externally via, for example, control circuitry 62 which may be stored in memory circuitry 60 (see, for example, FIG. 11E )). Thereafter, control circuitry 62 may determine and/or calculate the control data (and one, some or all of reference cells and/or reference cell circuits and/or reference cell banks 58a-x re-programmed) during operation to optimize, enhance, compensate and/or adjust reference currents 48a-x. For example, the reference current may be adjusted during operation to address and/or compensate for variations in operating conditions (for example, to compensate for aging, changes in temperature, and/or response time parameters or characteristics).
[0095] Further, in yet another embodiment, control circuitry 62 may fine-tune the control data to enhance the performance of one or more of reference current generator circuits 36a-x of reference current generator circuitry 36. In this regard, after (or during) the performance of an initialization or re-initialization process, control circuitry 62 may implement fine adjustments to the predetermined, preset or pre-programmed control data (which is stored in, for example, memory circuitry 60 and/or provided externally). The adjustments to the control data may be accomplished using any technique. Notably, all techniques for determining, modifying, changing and/or adjusting the control data, whether now known or later developed, are intended to be within the scope of the present inventions.
[0096] For example, in those embodiments where control circuitry 62 programs and/or re-programs one, some or all of reference cells and/or reference cell circuits of reference cell banks 58a-x, control circuitry 62 may implement a successive approximation approach to determine control data that, in conjunction with reference current generator circuitry 36, provides an optimized, enhanced, compensated and/or adjusted reference current 48. In this embodiment, control circuitry 62 may store the control data in successive approximation registers.
[0097] In addition, the reference current provided by one or more of reference current generator circuit 36a-x may be periodically and/or intermittently “refreshed” in order to provide an enhanced, optimum, desired, predetermined and/or “minimum” reference current. In this regard, in one embodiment, control circuitry 62 may periodically and/or intermittently connect one or more (or all of) pairs of reference cells of a given reference cell bank 58, via a switch (or a multiplexer), to one or more banks of the reference cells. In this way, in the event that the reference current provided by one or more banks of reference cells may not be (currently or impending) providing an enhanced, optimum, desired, predetermined and/or “minimum” reference current, for example, after a predetermined or given period of time (during operation or after setting, calibration and/or tuning), the control circuitry may “refresh” those or selected reference cell bank(s) 58.
[0098] Moreover, it may be advantageous to alternate the programming of associated reference cells 42 to reduce and/or minimize any memory effect that may result from continuously programming certain reference cells 42 to the same state. As such, in this embodiment, the logic state stored in one or more reference cells 42 may be changed to enhance the long term stability of reference current 48.
[0099] As noted above, control circuitry 62 may employ any programming algorithm whether now known or later developed. For example, control circuitry 62 may implement the exemplary control data algorithm of FIG. 10 . Notably, in one embodiment, an exemplary algorithm of FIG. 10 may be implemented and/or executed at power up (i.e., before using the memory device), and/or intermittently or periodically during normal operation to compensate for, for example, drift due to temperature variations.
[0100] The control circuitry 62, as mentioned above, may program one or more of the reference cell banks 58 of reference current generator circuits 36a-x. In this embodiment, “initial” control data may be provided at start-up/power-up and/or during an initialization sequence. Thereafter, control circuitry 62 may re-program one or more reference current generator circuits 36a-x during operation to optimize, enhance, compensate and/or adjust the reference current. For example, the reference current provided to data sensing circuitry 50 may be adjusted during operation of the device to address and/or compensate for variations in operating conditions (for example, to compensate for changes in temperature or response time parameters or characteristics).
[0101] Further, in yet another embodiment, the control data for one or more of reference current generator circuits 36a-x may be fine-tuned to enhance the performance/operation. In this regard, after (or during) the performance of an initialization or re-initialization process, the device may implement fine adjustments to the predetermined, preset or pre-programmed control data. The adjustments to the control data may be accomplished using any techniques; notably, all techniques, whether now known or later developed, are intended to be within the scope of the present inventions. For example, in those embodiments where control circuitry 62 programs or re-programs one, some or all of the reference current generator circuits 36a-x, control circuitry 62 may implement a successive approximation approach to determine control data that, in conjunction with the reference cell banks of reference current generator circuits 36a-x, and provide an optimized, enhanced, compensated and/or adjusted reference current. In this embodiment, control circuitry 62 may store the control data in successive approximation registers.
[0102] Again, as mentioned above, in one aspect of the inventions, an improved reference positioning takes sub-micron matching characteristics into account by shifting the reference level of electrical characteristic toward the lower magnitude level to provide Δ1−Ref=ΔRef−0 notwithstanding α≠0.
[0103] There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions.
[0104] For example, it may be advantageous to determine an appropriate, optimum and/or enhanced reference current to be output or provided by one or more (but less than all of reference current generator circuit 36a-x and provide the control data that is representative of the appropriate, optimum and/or enhanced reference current to other reference current generator circuit 36. For example, with reference to FIGS. 11A-E , an appropriate reference current control word may be determined for reference current generator circuit 36a and provided to reference current generator circuits 36 (for example, neighboring reference current generator circuit 36b). In this regard, the reference cell banks 58a and 58b may be the same general vicinity (for example, neighboring) such that banks 58a and 58b are provided by the same or the substantially same control word. In this way, a considerable amount of calibration and/or adjustment routine may be eliminated and/or avoid.
[0105] Moreover, in another embodiment, control data may be determined for one, some or all reference cell banks 58a-58x using, for example, any of the techniques described herein, and thereafter intermittently and/or periodically “tuned” or “tweaked” to account or compensate for changes in the performance of the device (for example, changes due to changes in temperature). As such, in one embodiment, at start-up, initialization or re-initialization, control circuitry 62 may determine control data that, in conjunction with one or more reference cell banks 58 and provide a suitable, predetermined, optimum and/or enhanced reference current 48, as described using any of the techniques above. Thereafter, the reference current may be adjusted during operation of the device by determining a relative adjustment to that “initial” control data (determined during, for example, at start-up/power-up and/or an initialization sequence).
[0106] The relative adjustment(s) may be determined (in any manner described herein or any manner now known or later developed) by examining one or more of reference cell banks 58 of one or more of reference current generator circuit 36a-x (for example, one or more reference cell banks in a sub array of memory cells and/or memory or sense bank). After determining the relative adjustment(s), control circuitry 62 may implement the change to the control data for other or all of the reference cell banks 58 of reference current generator circuits 36a-x (even those reference current generator circuits 36a-x that were not directly “analyzed” by control circuitry 62). In this way, changes, modifications and/or programming of the reference currents 48a-x may be accomplished more quickly so that normal operation of the device is not affected. Indeed, intermittently and/or periodically “tuning” or “tweaking” to compensate for changes in the performance of the device may be performed in a manner similar to refresh operation of a DRAM so that there is little to no impact on the normal operation of the device.
[0107] It should be noted that control circuitry 62 may include a plurality of control circuits or circuitry. One or more control circuits or circuitry may be associated with one or more sense amplifiers, memory or sense amplifier banks and/or arrays. In this way, calibration, programming and/or adjustment of the reference cell banks 58 may be performed more quickly as well as more often (without impacting the performance of the device).
[0108] As mentioned above, the reference current “repositioning” may be implemented in many different and diverse reference current generation techniques and embodiments (whether analog and/or digital techniques). For example, the present inventions may be employed in the read circuitry, architecture and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same” (now U.S. Pat. No. 6,912,150). In this regard, the read circuitry and techniques of the '902 application may include a “repositioned” reference current whereby one data state includes a greater “weight” than another state. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations) are incorporated by reference herein in its entirety.
[0109] Notably, the present inventions may be implemented in conjunction with any memory cell technology, whether now known or later developed. For example, the memory cells may include one or more electrically floating gate transistors, one transistor-one capacitor architecture, electrically floating gate transistors, JFETS, or any other memory/transistor technology whether now known or later developed. All such memory technologies are intended to fall within the scope of the present inventions.
[0110] Further, the present inventions may be implemented in conjunction with any type of memory (including discrete or integrated with logic devices), whether now known or later developed. For example, the memory may be a DRAM, SRAM and/or Flash. All such memories are intended to fall within the scope of the present inventions.
[0111] As mentioned above, the memory cells of the memory cell array may include at least one electrically floating body transistor which stores an electrical charge in the electrically floating body region of the transistor. Where an electrically floating body transistor is implemented, it may be programmed (written to), controlled and/or read using the techniques of the present inventions. Moreover, it may employ any electrically floating body memory cell, and/or memory cell array architecture, layout, structure and/or configuration employing such electrically floating body memory cells. In this regard, an electrically floating body transistor, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional U.S. patent applications:
[0112] (1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662);
[0113] (2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890);
[0114] (3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163);
[0115] (4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” (U.S. Patent Application Publication No. 2004/0228168);
[0116] (5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device & Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (U.S. Patent Application Publication No. 2005/0063224);
[0117] (6) application Ser. No. 11/509,188, which was filed by Okhonin et al. on Aug. 24, 2006 and entitled “Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same”;
[0118] The entire contents of these six (6) U.S. non-provisional patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety.
[0119] Notably, the memory cells may be controlled (for example, programmed or read) using any of the control circuitry described and illustrated in the above-referenced six (6) U.S. patent applications. For the sake of brevity, those discussions will not be repeated; such control circuitry is incorporated herein by reference. Indeed, all memory cell selection and control circuitry for programming, reading, controlling and/or operating memory cells including electrically floating body transistors, whether now known or later developed, are intended to fall within the scope of the present inventions.
[0120] For example, the data stored in memory cells 12 of DRAM array/device 10 may be read using many well known circuitry and techniques, including those described in the above-referenced six (6) non-provisional U.S. patent applications. Further, as mentioned above, the present inventions may also employ the read circuitry and techniques described and illustrated in U.S. patent application Ser. No. 11/299,590, which was filed by Waller et al. on May 7, 2004, and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read from Memory Cells” (U.S. Patent Application Publication No. 2006/0126374).
[0121] Moreover, a sense amplifier (not illustrated herein detail) may be employed to read the data stored in memory cells 12. The sense amplifier may sense the data state stored in memory cell 12 using voltage or current sensing techniques. In the context of a current sense amplifier, the current sense amplifier may compare the memory cell current to the reference current, for example, the current of a reference cells as illustrated above in the exemplary embodiments. From that comparison, it may be determined whether memory cell 12 contained a logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18). Such sensing circuitry and configurations thereof are well known in the art.
[0122] Notably, where a reference voltage is employed by sensing circuitry 50, reference current 48 may be translated and/or converted to a reference voltage using well known techniques. Such a reference voltage configuration is intended to fall within the scope of the present inventions.
[0123] The reference current generator 36 of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example, FIG. 12A ), or an integrated circuit device that is primarily a memory device (see, for example, FIG. 12B ). Indeed, the present inventions may be implemented in any device having one or more memory cells 12 (having electrically floating body transistors) and/or memory cell arrays 10.
[0124] The electrically floating memory cells, transistors and/or memory array(s) may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the electrically floating memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon, germanium, silicon/germanium, gallium arsenide or any other semiconductor material (whether bulk-type or SOI) in which transistors may be formed. As such, the electrically floating memory cells may be disposed on or in (collectively “on”) SOI-type substrate or a bulk-type substrate.
[0125] Indeed, the electrically floating transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication No. 2005/0017240), provisional patent application entitled “One Transistor Memory Cell having Mechanically Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,060, by Bassin, and/or provisional patent application entitled “Memory Cell, Array and Device, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,061, by Okhonin et al. (hereinafter collectively “Integrated Circuit Device Patent Applications”). The contents of the Integrated Circuit Device Patent Applications are hereby incorporated by reference herein.
[0126] In another aspect, the present inventions are directed to techniques for programming, reading, controlling and/or operating a semiconductor memory cell, array, architecture and device including electrically floating body transistors, having, for example, fully depleted (FD), surrounding-gate, double-gate, triple-gate and/or FinFET characteristics, in which electrical charge is stored in the body of the transistor. The present inventions are also directed to semiconductor memory cell, array, architecture and device that implement circuitry to implement such reading, controlling and/or operating techniques. The programming/reading technique may employ any of the techniques described and/or illustrated herein.
[0127] Further, memory array(s) 10 may be comprised of N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. In addition, although certain circuitry illustrated herein is indicated as P-channel or N-channel type transistors, the other type of transistor may be employed. For example, reference cells 42 may include P-channel type transistors, or reference current driver 46 may include an N-channel type transistor.
[0128] Further, reference current generator circuit 36 may include partially and/or fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890)). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.
[0129] Notably, electrically floating body transistor 14 may be a symmetrical or non-symmetrical device. Where transistor 14 is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor 14 is a non-symmetrical device, the source or drain regions of transistor 14 have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable.
[0130] As mentioned above, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated.
[0131] In another embodiment, reference network 38 may include current driver 40a having a device geometry (for example, gate width and/or gate length) of “a” which is different from the device geometry (for example, gate width and/or gate length) of one or more other current drivers 40 of reference network 38. (See, for example, FIG. 13 ). The different device geometries of current drivers 40a-40t provide additional flexibility to generate, obtain and/or provide a desired, predetermined and/or suitable reference current 48. In this embodiment, a desired, predetermined and/or suitable weighting of a given reference network 38 may be determined using a predetermined device geometries of current drivers 40a-40t.
[0132] Notably, the embodiment of FIG. 6 may also employ current drivers 40 having different device geometries (for example, gate width and/or gate lengths). In this regard, current driver 40a may include a device geometry (for example, gate width) of “a” which is different from the device geometry (for example, gate width) of one or more other current drivers 40t (which includes a geometry of “k”). (See, for example, FIG. 14A ). Again, as mentioned above, in this embodiment, the different device geometries of current drivers 40a-t provide additional flexibility to generate, obtain and/or provide a desired, predetermined and/or suitable reference current 48. As such, a desired, predetermined and/or suitable weighting of a given reference network 38 may be determined using a predetermined geometry(ies) of current drivers 40a-40t.
[0133] As mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments (for example, both reference cells 42 of reference cell circuits 42a-t in the embodiment illustrated in FIG. 6 may be programmed to the same data state—as discussed above in connection with the embodiment of FIG. 8 ). (See, FIGS. 14B and 14C ). For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments.
[0134] Moreover, the above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above.
[0135] It should be further noted that the term “circuit” may mean, among other things, a single component (for example, electrical/electronic and/or microelectromechanical) or a multiplicity of components (whether in integrated circuit form or otherwise), which are active and/or passive, and which are coupled together to provide or perform a desired operation. The term “circuitry” may mean, among other things, a circuit (whether integrated or otherwise) and/or a group of circuits. The term “data” may mean, among other things, a current or voltage signal(s) whether in an analog or a digital form.
Claims
What is claimed is:
1. A method of controlling a reference current generation circuit that generates a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein the reference current generation circuit includes (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver, the method comprising:
programming at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states;
programming at least one of the reference cells of the second reference cell circuit to one of a plurality of predetermined states, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of the predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
2. The method of claim 1 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of the at least one reference cell of the first reference cell circuit.
3. The method of claim 1 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes programming the at least one of the reference cells of the first reference cell circuit during an initialization sequence.
4. The method of claim 1 further including re-programming the at least one of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
5. The method of claim 4 further including re-programming the at least one of the reference cells of the second reference cell circuit to a different one of the plurality of predetermined states.
6. The method of claim 1 further including programming at least one reference cell of a third reference cell circuit to one of a plurality of predetermined states wherein the third reference cell circuit is one of the plurality of reference cell circuits.
7. The method of claim 1 wherein at least one reference cell of one of the plurality of reference cell circuits is fixed in a predetermined state.
8. A method of controlling a reference current generation circuit to generate a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein the reference current generation circuit includes (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver to generate the predetermined reference current, the method comprising:
programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states;
programming each reference cell of the second reference cell circuit to one of a plurality of predetermined states, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
9. The method of claim 8 wherein programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of each reference cell of the first reference cell circuit.
10. The method of claim 8 wherein programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states includes programming each reference colt of the first reference cell circuit during an initialization sequence.
11. The method of claim 8 further including re-programming at least one of the inference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
12. The method of claim 11 further including re-programming all of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
13. The method of claim 11 further including re-programming at least one of the reference cells of the second reference cell circuit to a different one of the plurality of predetermined states.
14. The method of claim 8 further including re-balancing a read margin by programming at least one of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
15. The method of claim 8 further including re-balancing a read margin by programming at least one of the reference cells of the first reference cell circuit to one of the plurality of predetermined states.
16. The method of claim 5 further including re-balancing a read margin by:
programming at least one of the reference cells of the first reference cell circuit to one of the plurality of predetermined states; and
programming at least one of the reference cells of the second reference cell circuit to one of the plurality of predetermined states.
17. The method of claim 5 further including programming at least one reference cell of a third reference cell circuit to one of a plurality of predetermined states wherein the third reference cell circuit is one of the plurality of reference cell circuits.
18. The method of claim 8 wherein at least one reference cell of one of the plurality of reference cell circuits is fixed in a predetermined state.
19. A method of generating a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein predetermined reference current is generated by a reference current generation circuit having (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver, the method comprising:
storing a control word in memory circuitry;
programming one or more reference cells of the first reference cell circuit to one of a plurality of predetermined states in accordance with the control word;
programming one or more reference cells of the second reference cell circuit to one of a plurality of predetermined states in accordance with the control word, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of the predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
20. The method of claim 19 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of the at least one reference cell of the first reference cell circuit.
Patent Citations (238)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3439214(A) | 1969-04-01 | Kabell | Applicant |
| US3997799(A) | 1976-12-01 | Baker | Applicant |
| US4032947(A) | 1977-06-01 | Kesel et al. | Applicant |
| US4250569(A) | 1981-02-01 | Sasaki et al. | Applicant |
| US4262340(A) | 1981-04-01 | Sasaki et al. | Applicant |
| US4298962(A) | 1981-11-01 | Hamano et al. | Applicant |
| US4371955(A) | 1983-02-01 | Sasaki | Applicant |
| US4527181(A) | 1985-07-01 | Sasaki | Applicant |
| US4630089(A) | 1986-12-01 | Sasaki et al. | Applicant |
| US4791610(A) | 1988-12-01 | Takemae | Applicant |
| US4979014(A) | 1990-12-01 | Hieda et al. | Applicant |
| US5144390(A) | 1992-09-01 | Matloubian | Applicant |
| US5258635(A) | 1993-11-01 | Nitayama et al. | Applicant |
| US5388068(A) | 1995-02-01 | Ghoshal et al. | Applicant |
| US5446299(A) | 1995-08-01 | Acovic et al. | Applicant |
| US5448513(A) | 1995-09-01 | Hu et al. | Applicant |
| US5466625(A) | 1995-11-01 | Hsieh et al. | Applicant |
| US5489792(A) | 1996-02-01 | Hu et al. | Applicant |
| US5528062(A) | 1996-06-01 | Hsieh et al. | Applicant |
| US5568356(A) | 1996-10-01 | Schwartz | Applicant |
| US5593912(A) | 1997-01-01 | Rajeevakumar | Applicant |
| US5606188(A) | 1997-02-01 | Bronner et al. | Applicant |
| US5627092(A) | 1997-05-01 | Alsmeier et al. | Applicant |
| US5631186(A) | 1997-05-01 | Park et al. | Applicant |
| US5696718(A) | 1997-12-01 | Hartmann | Applicant |
| US5740099(A) | 1998-04-01 | Tanigawa | Applicant |
| US5778243(A) | 1998-07-01 | Aipperspach et al. | Applicant |
| US5780906(A) | 1998-07-01 | Wu et al. | Applicant |
| US5784311(A) | 1998-07-01 | Assaderaghi et al. | Applicant |
| US5811283(A) | 1998-09-01 | Sun | Applicant |
| US5877978(A) | 1999-03-01 | Morishita et al. | Applicant |
| US5886376(A) | 1999-03-01 | Acovic et al. | Applicant |
| US5886385(A) | 1999-03-01 | Arisumi et al. | Applicant |
| US5897351(A) | 1999-04-01 | Forbes | Applicant |
| US5929479(A) | 1999-07-01 | Oyama | Applicant |
| US5930648(A) | 1999-07-01 | Yang | Applicant |
| US5936265(A) | 1999-08-01 | Koga | Applicant |
| US5939745(A) | 1999-08-01 | Park et al. | Applicant |
| US5943258(A) | 1999-08-01 | Houston et al. | Applicant |
| US5943581(A) | 1999-08-01 | Lu et al. | Applicant |
| US5960265(A) | 1999-09-01 | Acovic et al. | Applicant |
| US5968840(A) | 1999-10-01 | Park et al. | Applicant |
| US5977578(A) | 1999-11-01 | Tang | Applicant |
| US5982003(A) | 1999-11-01 | Hu et al. | Applicant |
| US6018172(A) | 2000-01-01 | Hidaka et al. | Applicant |
| US6081443(A) | 2000-06-01 | Morishita | Applicant |
| US6096598(A) | 2000-08-01 | Furukawa et al. | Applicant |
| US6097056(A) | 2000-08-01 | Hsu et al. | Applicant |
| US6111778(A) | 2000-08-01 | MacDonald et al. | Applicant |
| US6121077(A) | 2000-09-01 | Hu et al. | Applicant |
| US6157216(A) | 2000-12-01 | Lattimore et al. | Applicant |
| US6171923(B1) | 2001-01-01 | Chi et al. | Applicant |
| US6177300(B1) | 2001-01-01 | Houston et al. | Applicant |
| US6177708(B1) | 2001-01-01 | Kuang et al. | Applicant |
| US6214694(B1) | 2001-04-01 | Leobandung et al. | Applicant |
| US6225158(B1) | 2001-05-01 | Furukawa et al. | Applicant |
| US6245613(B1) | 2001-06-01 | Hsu et al. | Applicant |
| US6252281(B1) | 2001-06-01 | Yamamoto et al. | Applicant |
| US6292424(B1) | 2001-09-01 | Ohsawa | Applicant |
| US6297090(B1) | 2001-10-01 | Kim | Applicant |
| US6300649(B1) | 2001-10-01 | Hu et al. | Applicant |
| US6320227(B1) | 2001-11-01 | Lee et al. | Applicant |
| US6333532(B1) | 2001-12-01 | Davari et al. | Applicant |
| US6350653(B1) | 2002-02-01 | Adkisson et al. | Applicant |
| US6351426(B1) | 2002-02-01 | Ohsawa | Applicant |
| US6359802(B1) | 2002-03-01 | Lu et al. | Applicant |
| US6384445(B1) | 2002-05-01 | Hidaka et al. | Applicant |
| US6391658(B1) | 2002-05-01 | Gates et al. | Applicant |
| US6403435(B1) | 2002-06-01 | Kang et al. | Applicant |
| US6421269(B1) | 2002-07-01 | Somasekhar et al. | Applicant |
| US6424011(B1) | 2002-07-01 | Assaderaghi et al. | Applicant |
| US6424016(B1) | 2002-07-01 | Houston | Applicant |
| US6429477(B1) | 2002-08-01 | Mandelman et al. | Applicant |
| US6440872(B1) | 2002-08-01 | Mandelman et al. | Applicant |
| US6441435(B1) | 2002-08-01 | Chan | Applicant |
| US6441436(B1) | 2002-08-01 | Wu et al. | Applicant |
| US6466511(B2) | 2002-10-01 | Fujita et al. | Applicant |
| US6492211(B1) | 2002-12-01 | Divakaruni et al. | Applicant |
| US6518105(B1) | 2003-02-01 | Yang et al. | Applicant |
| US6531754(B1) | 2003-03-01 | Nagano et al. | Applicant |
| US6538916(B2) | 2003-03-01 | Ohsawa | Applicant |
| US6544837(B1) | 2003-04-01 | Divakaruni et al. | Applicant |
| US6548848(B2) | 2003-04-01 | Horiguchi et al. | Applicant |
| US6549450(B1) | 2003-04-01 | Hsu et al. | Applicant |
| US6552398(B2) | 2003-04-01 | Hsu et al. | Applicant |
| US6556477(B2) | 2003-04-01 | Hsu et al. | Applicant |
| US6566177(B1) | 2003-05-01 | Radens et al. | Applicant |
| US6567330(B2) | 2003-05-01 | Fujita et al. | Applicant |
| US6590258(B2) | 2003-07-01 | Divakauni et al. | Applicant |
| US6590259(B2) | 2003-07-01 | Adkisson et al. | Applicant |
| US6617651(B2) | 2003-09-01 | Ohsawa | Applicant |
| US6621725(B2) | 2003-09-01 | Ohsawa | Applicant |
| US6632723(B2) | 2003-10-01 | Watanabe et al. | Applicant |
| US6650565(B1) | 2003-11-01 | Ohsawa | Applicant |
| US6819589(B1) | 2004-11-01 | Aakjer | Examiner |
| US6912150(B2) | 2005-06-01 | Portmann et al. | Applicant |
| US7061806(B2) | 2006-06-01 | Tang et al. | Applicant |
| US7071771(B2) | 2006-07-01 | Takano et al. | Applicant |
| US7085156(B2) | 2006-08-01 | Ferrant et al. | Applicant |
| US7355916(B2) | 2008-04-01 | Bauser | Applicant |
| US2001/0055859(A1) | 2001-12-01 | Yamada et al. | Applicant |
| US2002/0030214(A1) | 2002-03-01 | Horiguchi | Applicant |
| US2002/0034855(A1) | 2002-03-01 | Horiguchi et al. | Applicant |
| US2002/0036322(A1) | 2002-03-01 | Divakauni et al. | Applicant |
| US2002/0051378(A1) | 2002-05-01 | Ohsawa | Applicant |
| US2002/0064913(A1) | 2002-05-01 | Adkisson et al. | Applicant |
| US2002/0070411(A1) | 2002-06-01 | Vermandel et al. | Applicant |
| US2002/0072155(A1) | 2002-06-01 | Liu et al. | Applicant |
| US2002/0076880(A1) | 2002-06-01 | Yamada et al. | Applicant |
| US2002/0086463(A1) | 2002-07-01 | Houston et al. | Applicant |
| US2002/0089038(A1) | 2002-07-01 | Ning | Applicant |
| US2002/0098643(A1) | 2002-07-01 | Kawanaka et al. | Applicant |
| US2002/0110018(A1) | 2002-08-01 | Ohsawa | Applicant |
| US2002/0114191(A1) | 2002-08-01 | Iwata et al. | Applicant |
| US2002/0130341(A1) | 2002-09-01 | Horiguchi et al. | Applicant |
| US2002/0160581(A1) | 2002-10-01 | Watanabe et al. | Applicant |
| US2002/0180069(A1) | 2002-12-01 | Houston | Applicant |
| US2003/0003608(A1) | 2003-01-01 | Arikado et al. | Applicant |
| US2003/0015757(A1) | 2003-01-01 | Ohsawa | Applicant |
| US2003/0035324(A1) | 2003-02-01 | Fujita et al. | Applicant |
| US2003/0057487(A1) | 2003-03-01 | Yamada et al. | Applicant |
| US2003/0057490(A1) | 2003-03-01 | Nagano et al. | Applicant |
| US2003/0102497(A1) | 2003-06-01 | Fried et al. | Applicant |
| US2003/0112659(A1) | 2003-06-01 | Ohsawa | Applicant |
| US2003/0123279(A1) | 2003-07-01 | Aipperspach et al. | Applicant |
| US2003/0146488(A1) | 2003-08-01 | Nagano et al. | Applicant |
| US2003/0151112(A1) | 2003-08-01 | Yamada et al. | Applicant |
| US2003/0156457(A1) | 2003-08-01 | Ooishi | Applicant |
| US2003/0185037(A1) | 2003-10-01 | Hibino | Applicant |
| US2004/0108532(A1) | 2004-06-01 | Forbes | Applicant |
| US2005/0017240(A1) | 2005-01-01 | Fazan | Applicant |
| US2005/0063224(A1) | 2005-03-01 | Fazan et al. | Applicant |
| US2005/0169038(A1) | 2005-08-01 | Inoue et al. | Applicant |
| US2005/0226070(A1) | 2005-10-01 | Ohsawa | Applicant |
| US2005/0232043(A1) | 2005-10-01 | Ohsawa | Applicant |
| US2006/0091462(A1) | 2006-05-01 | Okhonin et al. | Applicant |
| US2006/0092689(A1) | 2006-05-01 | Braun et al. | Applicant |
| US2006/0098481(A1) | 2006-05-01 | Okhonin et al. | Applicant |
| US2006/0126374(A1) | 2006-06-01 | Waller et al. | Applicant |
| US2006/0131650(A1) | 2006-06-01 | Okhonin et al. | Applicant |
| US2007/0023833(A1) | 2007-02-01 | Okhonin et al. | Applicant |
| US2007/0058427(A1) | 2007-03-01 | Okhonin et al. | Applicant |
| EP30856 | 1981-06-01 | Applicant | |
| EP350057 | 1990-01-01 | Applicant | |
| EP354348 | 1990-02-01 | Applicant | |
| EP362961 | 1990-04-01 | Applicant | |
| EP202515 | 1991-03-01 | Applicant | |
| EP207619 | 1991-08-01 | Applicant | |
| EP175378 | 1991-11-01 | Applicant | |
| EP253631 | 1992-04-01 | Applicant | |
| EP513923 | 1992-11-01 | Applicant | |
| EP300157 | 1993-05-01 | Applicant | |
| EP564204 | 1993-10-01 | Applicant | |
| EP579566 | 1994-01-01 | Applicant | |
| EP362961 | 1994-02-01 | Applicant | |
| EP599506 | 1994-06-01 | Applicant | |
| EP359551 | 1994-12-01 | Applicant | |
| EP642173 | 1995-03-01 | Applicant | |
| EP366882 | 1995-05-01 | Applicant | |
| EP465961 | 1995-08-01 | Applicant | |
| EP694977 | 1996-01-01 | Applicant | |
| EP333426 | 1996-07-01 | Applicant | |
| EP727820 | 1996-08-01 | Applicant | |
| EP739097 | 1996-10-01 | Applicant | |
| EP245515 | 1997-04-01 | Applicant | |
| EP788165 | 1997-08-01 | Applicant | |
| EP801427 | 1997-10-01 | Applicant | |
| EP510607 | 1998-02-01 | Applicant | |
| EP537677 | 1998-08-01 | Applicant | |
| EP858109 | 1998-08-01 | Applicant | |
| EP860878 | 1998-08-01 | Applicant | |
| EP869511 | 1998-10-01 | Applicant | |
| EP878804 | 1998-11-01 | Applicant | |
| EP920059 | 1999-06-01 | Applicant | |
| EP924766 | 1999-06-01 | Applicant | |
| EP642173 | 1999-07-01 | Applicant | |
| EP727822 | 1999-08-01 | Applicant | |
| EP933820 | 1999-08-01 | Applicant | |
| EP951072 | 1999-10-01 | Applicant | |
| EP971360 | 2000-01-01 | Applicant | |
| EP980101 | 2000-02-01 | Applicant | |
| EP601590 | 2000-04-01 | Applicant | |
| EP993037 | 2000-04-01 | Applicant | |
| EP836194 | 2000-05-01 | Applicant | |
| EP599388 | 2000-08-01 | Applicant | |
| EP689252 | 2000-08-01 | Applicant | |
| EP606758 | 2000-09-01 | Applicant | |
| EP682370 | 2000-09-01 | Applicant | |
| EP1073121 | 2001-01-01 | Applicant | |
| EP726601 | 2001-09-01 | Applicant | |
| EP731972 | 2001-11-01 | Applicant | |
| EP1162663 | 2001-12-01 | Applicant | |
| EP1162744 | 2001-12-01 | Applicant | |
| EP1179850 | 2002-02-01 | Applicant | |
| EP1180799 | 2002-02-01 | Applicant | |
| EP1191596 | 2002-03-01 | Applicant | |
| EP1204146 | 2002-05-01 | Applicant | |
| EP1204147 | 2002-05-01 | Applicant | |
| EP1209747 | 2002-05-01 | Applicant | |
| EP744772 | 2002-08-01 | Applicant | |
| EP1233454 | 2002-08-01 | Applicant | |
| EP725402 | 2002-09-01 | Applicant | |
| EP1237193 | 2002-09-01 | Applicant | |
| EP1241708 | 2002-09-01 | Applicant | |
| EP1253634 | 2002-10-01 | Applicant | |
| EP844671 | 2002-11-01 | Applicant | |
| EP1280205 | 2003-01-01 | Applicant | |
| EP1288955 | 2003-03-01 | Applicant | |
| EP1560221 | 2005-08-01 | Applicant | |
| FR2197494 | 1974-03-01 | Applicant | |
| GB1414228 | 1975-11-01 | Applicant | |
| JP62-272561 | 1987-11-01 | Applicant | |
| JP2-294076 | 1991-02-01 | Applicant | |
| JP3171768 | 1991-07-01 | Applicant | |
| JP8213624 | 1996-08-01 | Applicant | |
| JP8-274277 | 1996-10-01 | Applicant | |
| JP9046688 | 1997-02-01 | Applicant | |
| JP9-82912 | 1997-03-01 | Applicant | |
| JP10242470 | 1998-11-01 | Applicant | |
| JP11-87649 | 1999-03-01 | Applicant | |
| JP247735 | 2000-08-01 | Applicant | |
| JP274221 | 2000-09-01 | Applicant | |
| JP389106 | 2000-12-01 | Applicant | |
| JP180633 | 2001-06-01 | Applicant | |
| JP2002-94027 | 2002-03-01 | Applicant | |
| JP2002-176154 | 2002-06-01 | Applicant | |
| JP2002-246571 | 2002-08-01 | Applicant | |
| JP2002-0981 | 2002-11-01 | Applicant | |
| JP2002-329795 | 2002-11-01 | Applicant | |
| JP2002-343886 | 2002-11-01 | Applicant | |
| JP2002-353080 | 2002-12-01 | Applicant | |
| JP2003-31693 | 2003-01-01 | Applicant | |
| JP2003-86712 | 2003-03-01 | Applicant | |
| JP2003-100641 | 2003-04-01 | Applicant | |
| JP2003-100900 | 2003-04-01 | Applicant | |
| JP2003-132682 | 2003-05-01 | Applicant | |
| JP2003-203967 | 2003-07-01 | Applicant | |
| JP2003-243528 | 2003-08-01 | Applicant |
Non-Patent Literature (73)
- “A Capacitorless Double-Gate DRAM Cell”, Kuo et al., IEEE Electron Device Letters, vol. 23, No. 6, Jun. 2002, pp. 345-347.Applicant
- “The Multi-Stable Behaviour of SOI-NMOS Transistors at Low Temperatures”, Tack et al., Proc. 1988 SOS/SOI Technology Workshop (Sea Palms Resort, St. Simons Island, GA, Oct. 1988), p. 78.Applicant
- “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, Tack et al., IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1990, pp. 1373-1382.Applicant
- “Mechanisms of Charge Modulation in the Floating Body of Triple-Well nMOSFET Capacitor-less DRAMs”, Villaret et al., Proceedings of the INFOS 2003, Insulating Films on Semiconductors, 13th Bi-annual Conference, Jun. 18-20, 2003, Barcelona (Spain), (4 pages).Applicant
- “A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's”, Ohsawa et al., 2003 Symposium on VLSI Circuits Digest of Technical Papers (4 pages).Applicant
- FBC (Floating Body Cell) for Embedded DRAM on SOI, Inoh et al., 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003 (2 pages).Applicant
- “Toshiba's DRAM Cell Piggybacks on SOI Wafer”, Y. Hara, EE Times, Jun. 2003.Applicant
- “Memory Design Using a One-Transistor Gain Cell on SOI”, Ohsawa et al., IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.Applicant
- “Opposite Side Floating Gate SOI FLASH Memory Cell”, Lin et al., IEEE, Mar. 2000, pp. 12-15.Applicant
- “Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography”, Yamanaka et al., IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995, pp. 1305-1313.Applicant
- “Soft-Error Characteristics in Bipolar Memory Cells with Small Critical Charge”, Idei et al., IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991, pp. 2465-2471.Applicant
- “An SOI 4 Transistors Self-Refresh Ultra-Low-Voltage Memory Cell”, Thomas et al., IEEE, Mar. 2003, pp. 401-404.Applicant
- “Design of a SOI Memory Cell”, Stanojevic et al., IEEE Proc. 21st International Conference on Microelectronics (MIEL '97), vol. 1, NIS, Yugoslavis, Sep. 14-17, 1997, pp. 297-300.Applicant
- “Effects of Floating Body on Double Polysilicon Partially Depleted SOI Nonvolatile Memory Cell”, Chan et al., IEEE Electron Device Letters, vol. 24, No. 2, Feb. 2003, pp. 75-77.Applicant
- “MOSFET Design Simplifies DRAM”, P. Fazan, EE Times, May 14, 2002 (3 pages).Applicant
- “One of Application of SOI Memory Cell—Memory Array”, Loncar et al., IEEE Proc. 22nd International Conference on Microelectronics (MIEL 2000), vol. 2, NIS, Serbia, May 14-17, 2000, pp. 455-458.Applicant
- “A SOI Current Memory for Analog Signal Processing at High Temperature”, Portmann et al., 1999 IEEE International SOI Conference, Oct. 1999, pp. 18-19.Applicant
- “Chip Level Reliability on SOI Embedded Memory ”, Kim et al., Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 135-139.Applicant
- “Analysis of Floating-Body-Induced Leakage Current in 0.15 μm SOI DRAM”, Terauchi et al., Proceedings of 1998 IEEE International SOI Conference, Oct. 1996, pp. 138-139.Applicant
- “Programming and Erase with Floating-Body for High Density Low Voltage Flash EEPROM Fabricated on SOI Wafers”, Chi et al., Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 129-130.Applicant
- “Measurement of Transient Effects in SOI DRAM/SRAM Access Transistors”, A. Wei. IEEE Electron Device Letters, vol. 17, No. 5, May 1996, pp. 193-195.Applicant
- “In-Depth Analysis of Opposite Channel Based Charge Injection in SOI MOSFET's and Related Defect Creation and Annihilation”, Sinha et al., Elsevier Science, Microelectronic Engineering 28, 1995, pp. 383-386.Applicant
- “Dynamic Effects in SOI MOSFET's ”, Giffard et al., IEEE, 1991, pp. 160-161.Applicant
- “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”, Fazan et al., IEEE 2002 Custom Integrated Circuits Conference, Jun. 2002, pp. 99-102.Applicant
- “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMs”, Lee et al., Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 114-115.Applicant
- “An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application”, Furuyama et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 388-393.Applicant
- “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply”, Yamauchi et al., IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp. 1169-1178.Applicant
- “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SiMOX Technology”, Suma et al., 1994 IEEE International Solid-State Circuits Conference, pp. 138-139.Applicant
- “A Capacitorless DRAM Cell on SOI Substrate”, Wann et al., IEEE IEDM, 1993, pp. 635-638.Applicant
- “The Multistable Charge Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., IEEE Workshop on Low Temperature Electronics, Aug. 7-8, 1989, University of Vermont, Burlington, pp. 137-141.Applicant
- “High-Endurance Ultra-Thin Tunnel Oxide in MONOS Device Structure for Dynamic Memory Application”, Wann et al., IEEE Electron Device Letters, vol. 16, No. 11, Nov. 1995, pp. 491-493.Applicant
- “Hot-Carrier Effects in Thin-Film Fully Depleted SOI MOSFET's”, Ma et al., IEEE Electron Device Letters, vol. 15, No. 6, Jun. 1994, pp. 218-220.Applicant
- “Design Analysis of Thin-Body Silicide Source/Drain Devices”, 2001 IEEE International SOI Conference, Oct. 2001, pp. 21-22.Applicant
- “SOI MOSFET on Low Cost SPIMOX Substrate”, Iyer et al., IEEE IEDM, Sep. 1998, pp. 1001-1004.Applicant
- “Simulation of Floating Body Effect in SOI Circuits Using BSIM3SOI”, Tu et al., Proceedings of Technical Papers (IEEE Cat No. 97TH8303), pp. 339-342.Applicant
- “High-Field Transport of Inversion-Layer Electrons and Holes Including Velocity Overshoot”, Assaderaghi et al., IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 664-671.Applicant
- “Dynamic Treshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI”, Assaderaghi et al., IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, pp. 414-422.Applicant
- “Hot-Carrier-Induced Degradation in Ultra-Thin-Film Fully-Depleted SOI MOSFETs”, Yu et al., Solid-State Electronics, vol. 39, No. 12, 1996, pp. 1791-1794.Applicant
- Hot-Carrier Effect in Ultra-Thin-Film (UTF) Fully-Depleted SOI MOSFET's, Yu et al., 54th Annual Device Research Conference Digest (Cat. No. 96TH8193), pp. 22-23.Applicant
- “SOI MOSFET Design for All-Dimensional Scaling with Short Channel, Narrow Width and Ultra-thin FIlms”, Chan et al., IEEE IEDM, 1995, pp. 631-634.Applicant
- “A Novel Silicon-On-Insulator (SOI) MOSFET for Ultra Low Voltage Operation”, Assaderaghi et al., 1994 IEEE Symposium on Low Power Electronics, pp. 58-59.Applicant
- “Interface Characterization of Fully-Depleted SOI MOSFET by a Subthreshold I-V Method”, Yu et al., Proceedings 1994 IEEE International SOI Conference, Oct. 1994, pp. 63-64.Applicant
- “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications”, Kuo et al., IEEE IEDM, Feb. 2002, pp. 843-846.Applicant
- “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, Assaderaghi et al., IEEE IEDM, 1994, pp. 809-812.Applicant
- “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation”, Assaderaghi et al., IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994, pp. 510-512.Applicant
- “A Capacitorless DRAM Cell on SOI Substrate”, Wann et al., IEEE IEDM 1993, pp. 635-638.Applicant
- “Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD”, Su et al., IEEE Proceedings of the International Symposium on Quality Electronic Design (ISQED '02), Apr. 2002 (5 pages).Applicant
- “Characterization of Front and Back Si-SiO2 Interfaces in Thick- and Thin-Film Silicon-on-Insulator MOS Structures by the Charge-Pumping Technique”, Wounters et al., IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, pp. 1746-1750.Applicant
- “An Analytical Model for the Misis Structure in SOI MOS Devices”, Tack et al., Solid-State Electronics vol. 33, No. 3, 1990, pp. 357-364.Applicant
- “A Long Data Retention SOI DRAM with the Body Refresh Function”, Tomishima et al., IEICE Trans. Electron., vol. E80-C, No. 7, Jul. 1997, pp. 899-904.Applicant
- “Capacitor-Less 1-Transistor DRAM”, Fazan et al., 2002 IEEE International SOI Conference, Oct. 2002, pp. 10-13.Applicant
- “SOI (Silicon-on-Insulator) for High Speed Ultra Large Scale Integration”, C. Hu, Jpn. J. Appl. Phys. vol. 33 (1994) pp. 365-369, Part 1, No. 1B, Jan. 1994.Applicant
- “Source-Bias Dependent Charge Accumulation in P+ -Poly Gate SOI Dynamic Random Access Memory Cell Transistors”, Sim et al., Jpn. J. Appl. Phys. vol. 37 (1998) pp. 1260-1263, Part 1, No. 3B, Mar. 1998.Applicant
- “Suppression of Parasitic Bipolar Action in Ultra-Thin-Film Fully-Depleted CMOS/SIMOX Devices by Ar-Ion Implantation into Source/Drain Regions”, Ohno et al., IEEE Transactions on Electron Devices, vol. 45, No. 5, May 1998, pp. 1071-1076.Applicant
- dRAM Design Using the Taper-Isolated Dynamic RAM Cell, Leiss et al., IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 707-714.Applicant
- “Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Films on SiO2”, Tsaur et al., IEEE Electron Device Letters, vol. EDL-4, No. 8, Aug. 1983, pp. 269-271.Applicant
- “Silicon-On-Insulator Bipolar Transistors”, Rodder et al., IEEE Electron Device Letters, vol. EDL-4, No. 6, Jun. 1983, pp. 193-195.Applicant
- “Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon”, Malhi et al., IEEE Transactions on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 258-281.Applicant
- “Triple-Wel nMOSFET Evaluated as a Capacitor-Less DRAM Cell for Nanoscale Low-Cost & High Density Applications”, Villaret et al., Handout at Proceedings of 2003 Silicon Nanoelectronics Workshop, Jun. 8-9, 2003, Kyoto, Japan (2 pages).Applicant
- “Mechanisms of Charge Modulation in the Floating Body of Triple-Well NMOSFET Capacitor-less DRAMs”, Villaret et al., Handout at Proceedings of INFOS 2003, Jun. 18-20, 2003, Barcelona, Spain (2 pages).Applicant
- “Embedded DRAM Process Technology”, M. Yamawaki, Proceedings of the Symposium on Semiconductors and Integrated Circuits Technology, 1998, vol. 55, pp. 38-43.Applicant
- “3-Dimensional Simulation of Turn-off Current in Partially Depleted SOI MOSFETs”, Ikeda et al., IEIC Technical Report, Institute of Electronics, Information and Communication Engineers, 1998, vol. 97, No. 557 (SDM97 186-198), pp. 27-34.Applicant
- “Dynamic floating body control SOI CMOS for power managed multimedia ULSIs”, F. Morishita et al., Proc. CICC, pp. 263-266, 1997.Applicant
- “A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro With a Power-Down Data Retention Mode for Mobile Applications”, F. Morishita et al., J. Solid-State Circuits, vol. 40, No. 1, pp. 204-212, 2005.Applicant
- “Leakage Mechanism due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAM”, F. Morishita et al., Symposium on VLSI Technology Digest of Technical Papers, pp. 141-142, 1995.Applicant
- “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FINDRAM”, Tanaka et al., 2004 IEEE, 4 pages.Applicant
- “A Design of a Capacitorless 1-T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-Power and High-speed Embedded Memory”, Yoshida et al., 2003 IEEE, 4 pages.Applicant
- “A Study of High Scalable DG-FInDRAM”, Yoshida et al., IEEE Electron Device Letters, vol. 26, No. 9, Sep. 2005, pp. 655-657.Applicant
- “Novel Capacitorless 1T-DRAM From Single-gate PD-SOI to Double-gate FinDRAM”, ATIP Scoops, May 9, 2005, 9 pages.Applicant
- “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier”, T. Blalock, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 542-548.Applicant
- “Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in PD/SOI MOSFETs”, Pelella et al., Final Camera Ready Art, SOI Conference, Oct. 1995, 2 pages.Applicant
- “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Mandelman et al, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 136-137.Applicant
- “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, Ohsawa et al., 2005 IEEE International Solid-State Circuits Conference, Feb. 9, 2005, pp. 458-459, 609.Applicant