Method and apparatus for reducing body diode conduction of synchronous rectifiers

[0001] This application is a continuation of U.S. patent application Ser. No. 11/002,426 filed on Dec. 2, 2004. The disclosure of the above application is incorporated herein by reference.

[0002] The present invention relates generally to switching power supplies, and, more particularly, to a control circuit for synchronous rectifiers.

[0003] Manufacturers of electronic components increasingly demand switching power converters that have a very low voltage loss and a high output current. One type of a switching power converter uses a synchronous rectification technique. Synchronous rectifiers typically are implemented as metal-oxide semiconductor field-effect transistors (MOSFETs), although other switches such as bipolar junction transistors (BJTs), insulated-gate field-effect transistors (IGBTs), or other switches may be used. Synchronous rectification improves the efficiency of a power converter by substituting a transistor for a rectifier diode. This type of switching power converter is generally formed by a switching circuit, a transformer, a rectifying circuit, and at least one control circuit.

[0004] The switching circuit typically includes a bridge circuit arranged in a push-pull configuration with a transformer. For example, four switching devices (switches) may define the bridge circuit. The first and second switches are connected in series. The third and a fourth switches are also connected in series, and the series pairs are connected in parallel across a direct current (DC) voltage source. The transformer, which has a primary winding and a secondary winding, connects to the first and the second switches at one end of the primary winding. The other end of the primary winding connects to the third and the fourth switches. A rectifying circuit including two synchronous rectifiers connects to the secondary side of the transformer. A primary control circuit connects to the switching circuit. The primary control circuit generates a drive signal for each of the switches.

[0005] A secondary control circuit drives the synchronous rectifiers in accordance with drive signals output by the primary control circuit. In one configuration, the secondary control circuit includes two logical OR gates. The drive signals used to control the first and fourth switches define inputs to the first logical OR gate. The first logical OR gate outputs a drive signal to one of the two synchronous rectifiers. The drive signals used to control the second and third switches define inputs to the second logical OR gate. The second logical OR gate outputs a drive signal to the other of the two synchronous rectifiers. An example of such a configuration may be seen with respect to U.S. Pat. No. 6,504,739 issued Jan. 7, 2003, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein.

[0006] While the switching power converter described above has a low voltage loss and a high current output, it may not address all of the parasitic components that potentially exist in a synchronous rectifier circuit. For example, a zero phase shifted full bridge, zero voltage switching (ZVS) converter includes transformer leakage inductance. Transformer leakage inductance causes a delay in the actual voltage of the secondary winding relative to the voltage across the primary winding. It may also increase the time necessary for the drain current passing through the synchronous rectifier to deplete to zero with respect to the primary winding voltage. This voltage and current delay increases as the load current increases. When the synchronous rectifiers turn off, the drain current through the MOSFET transfers to the body diode of the MOSFET, thereby increasing the voltage drop across the MOSFET. These conduction losses are higher than if the drain current was able to pass through a drain-to-source on-resistance.

[0007] The present invention is directed to circuit including a secondary controller and a delay circuit coupled to the secondary controller. The delay circuit receives a first synchronous rectifier control signal from the secondary controller and a load current signal. The delay circuit applies a predetermined delay to the first synchronous rectifier control signal. A synchronous rectifier control circuit is coupled to the secondary controller and to the delay circuit. The synchronous rectifier control circuit receives the delayed first synchronous rectifier control signal and controls a synchronous rectifier in accordance with the first synchronous rectifier control signal. The delay applied to the first synchronous rectifier control signal varies in accordance with the load current signal.

[0021] The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, similar reference numbers are used in the drawings to identify similar elements.

[0022] The present invention increases the efficiency of power converters by reducing the body diode conduction due to transformer leakage inductance. This is accomplished by optimizing control of the synchronous rectifier relative to the output load current. For example, turning a synchronous rectifier to an off state is delayed until the drain current is nearly zero in the synchronous rectifier. This reduces body diode conduction through the synchronous rectifier. Moreover, the cost to manufacture a switching power converter is reduced since lower performing components may replace more expensive components while still attaining power efficiency requirements.

[0023] Although the following description generally relates to a full bridge converter, it is readily understood that the broader aspects of the present invention are applicable to other types of converter topologies (e.g. push-pull topologies, half bridge topologies, etc.) that use synchronous rectification. In particular, the present invention may be applied to soft switched full bridge, full bridge, forward half bridge, and flyback converters that use synchronous rectification.

[0024] FIG. 1 depicts a block diagram of a synchronous rectifier control circuit 10 for delaying a signal to turn off a synchronous rectifier. Synchronous rectifier control circuit 10 includes synchronous rectifier controller 12, delay selector circuit 16, and synchronous rectifier delay control circuit 18.

[0025] Primary side drive signals enter synchronous rectifier controller 12 from a primary control circuit (not shown). Synchronous rectifier controller 12 controls the application of the primary side drive signals to synchronous rectifier delay control circuit 18 and to delay selector circuit 16. A load current signal (I_SEN), which depends upon the magnitude of a load current I_LOAD, is input to delay selector circuit 16. Based upon I_LOAD, delay selector circuit 16 determines the desired delay. A delay signal is then output from delay selector circuit 16 to synchronous rectifier delay control circuit 18. Synchronous rectifier delay control circuit 18 then generates a control signal to turn off a selected synchronous rectifier.

[0026] FIG. 2 is a detailed embodiment of a zero phase shifted full bridge, zero voltage switching (ZVS) power converter 100. Power converter 100 comprises input voltage source 132 (V_IN), switching circuit 134, transformer 136, rectifying circuit 138, primary control circuit 140, secondary control circuit 142.

[0027] Switching circuit 134 includes a first switching device (switch) Q_A connected in series to a second switch Q_B to form a first switching leg. Switching circuit 134 also includes a third switch Q_C connected in series to a fourth switch Q_D to form a second switching leg. The switching legs are connected in parallel across input voltage source 132. In one embodiment, one or more of the primary switches are metal-oxide semiconductor field-effect transistors (MOSFETs) switches, although one skilled in the art will recognize that bipolar junction transistor (BJTs), insulated-gate field-effect transistors (IGBTs) or other suitable switches may also be used. Switching circuit 134 connects to transformer 136, which includes a primary side having primary winding 112 and a secondary side including secondary winding 114. One end of primary winding 112 connects to first node 116, and the other end of the primary winding 112 connects to second node 118.

[0028] Primary control circuit 140 generates drive signals for each of the switches Q_A, Q_B, Q_C, and Q_D of switching circuit 134. In one configuration, primary control circuit 140 generates drive signals of various phases to the Q_A/Q_D pair of switches and drive signals of various phases to the Q_C/Q_B pair of switches. The control signals to switch pair Q_A/Q_D are generally complementary to control signals to switch pair Q_C/Q_B. This allows diagonal switches (i.e., Q_A/Q_Dand Q_C/Q_B) to conduct alternately to effect a push-pull configuration across primary winding 112. Thus, primary control circuit 140 provides ZVS, phase shifted control over switching circuit 134.

[0029] Rectifying circuit 138 includes two synchronous rectifiers connected to a center-tapped secondary winding 114 of transformer 136. A first rectifying switch FETQ1 (also referred to as first synchronous rectifier) connects to a first end of secondary winding 114, and a second rectifying switch FETQ2 (also referred to as second synchronous rectifier) connects to the other end of secondary winding 114. An inductor L connects between a center tap of secondary winding 114 and an output terminal providing an output voltage V₀ to a load 126 in parallel with capacitor 156.

[0030] Secondary control circuit 142 connects to switches FETQ1 and FETQ2 of the rectifying circuit 138. Control signals Q_A, Q_B, QC, Q_D from primary control circuit 140 provide input signals to secondary control circuit 142 to activate and to deactivate synchronous rectifiers FETQ1, FETQ2. In a conventional drive configuration, when a first pair of diagonal switches on the primary side of transformer 136 are both conducting, one of the two synchronous rectifiers FETQ1, FETQ2 is typically in an on state. After both of the first pair of diagonal switches is driven to an off state by primary control circuit 140, secondary control circuit 142 drives the one of the two synchronous rectifiers FETQ1, FETQ2 to an off state. In an embodiment of the present invention, secondary control circuit 142 delays turn off of the control signal for the second switch of a diagonal pair to correspondingly delay turn off of the associated synchronous rectifier. More specifically, the synchronous rectifier control signal that controls the later switch to be turned off of the switch pairs Q_A/Q_D and Q_C/Q_Bis delayed by secondary control circuit 142. As described herein, active refers to active high.

[0031] FIGS. 3A-3D depict secondary control circuit 142 of FIG. 2 which includes a delay selection section 162 and delay element section 164. Except where noted, delay element section 164 includes substantially identical halves a and b, and like elements are referred to using like reference numerals having suffixes a and b. Generally, the amount of delay to turn off a synchronous rectifier depends on the delay elements operating in delay element section 164. Delay selection section 162 determines the delay elements operating in the delay element section 164.

[0032] Delay selection section 162 selects the delay element to operate in the delay element section 164 based on the magnitude of the load current flowing through the load 126 of FIG. 2. Referring to FIG. 3A, I_SEN is determined based upon I_LOAD using a conventional current sensing circuit 200 as shown in FIG. 12, as will be described in greater detail herein. I_SEN passes through resistor R101, and a capacitor C101 provides low pass filtering. The voltage at the anode of capacitor C101 is referred to as V_ISEN.

[0033] The V_ISEN voltage is applied to comparators U2 and U1 via respective resistors R103 and R107. Resistors R104 and R105 form a voltage divider for a reference voltage V_REF to provide a reference voltage applied to the inverting input of comparator U2. The output signal CON2 is determined by comparing the voltage at the inverting input to the voltage at the non-inverting input of comparator U2. When the voltage at the non-inverting input exceeds the voltage at the inverting input, CON2 is high. If the voltage at the non-inverting input is less than the voltage at the inverting input, CON2 is low. A feedback resistor R102 provides hysteresis at the non-inverting input.

[0034] The output signal CON1 from comparator U1 is similarly determined. Resistors R108 and R109 form a voltage divider for a reference voltage V_REF to provide a reference voltage applied to the inverting input of comparator U1. The output signal CON1 is determined by comparing the voltage at the inverting input to the voltage at the non-inverting input of comparator U2. If the voltage at the non-inverting input is less than the voltage at the inverting input, CON1 is low. If the voltage at the non-inverting input exceeds the voltage at the inverting input, CON1 is high. A feedback resistor R106 provides hysteresis at the non-inverting input of comparator U1. CON1 and CON2 are applied to the delay element section 164.

[0035] Delay element section 164 includes first and second delay circuits 170a, 170b. First delay circuit 170a will be described herein. One skilled in the art will recognize that second delay circuit 170b operates similarly. First delay circuit 170a connects to an input of a first OR gate 160a. Drive signal Q_Aconnects to the input of first OR gate 160a through a parallel connection of resistor R1a and D1a of first delay circuit 170a. Drive signal Q_D connects to the other input of the first OR gate 160a. First OR gate 160a outputs a drive signal to the synchronous rectifier FETQ₁. As will be described in greater detail herein, activating CON1 and/or CON2 correspondingly activates respective switches S1a and S2a to selectively introduce varying capacitances between the Q_A input of OR gate 160a and ground.

[0036] The CON1 output of comparator U1 connects to a voltage divider that includes resistors R4a, R3a, and R2a. One terminal of resistor R4aconnects to an 8 volt source and the other terminal of resistor R4a connects to resistor R3a. One node of the voltage divider connects to the gate of switch S1a. Switch S1a includes a capacitance Coss across its drain and source, which connects to ground. The capacitance Coss may be the small output capacitance of switch S1a, or it may be an external capacitance.

[0037] Similarly, CON2 connects to a voltage divider that includes resistors R7a, R6a, and R5a. One terminal of resistor R7a connects to an 8 volt source, and the other terminal of resistor R7a connects to resistor R6a. The drain of switch S2a connects to a node interconnecting capacitors C2a and C3a to provide a path from the interconnecting terminal of C3a, through switch S2a, to ground.

[0038] Delay element section 164 generates a delay that depends upon which, if any, of switches S1a, S2a are activated by respective signals CON1 and CON 2. FIGS. 3B-3D depict circuits describing the operation of secondary control circuit 142 based upon the load current signal I_SEN, which varies in accordance with the load current I_LOAD By way of example, I_LOAD may fall into one of three regions, a low load region, a mid-load region, or a high load region. The low load region (FIG. 3B) is generally between 0 ampere (A) and 30 A. The mid-load region (FIG. 3C) is generally between 30 A and 65 A. The high load region (FIG. 3D) is generally greater than 65A. These regions of the load current I_LOAD determine the amount of delay introduced prior to switching the synchronous rectifiers FETQ1, FETQ2 to an off state. One skilled in the art will recognize that load currents defining these regions and the number of regions may vary.

[0039] The arrow in FIG. 3B illustrates the circuit path through selected capacitive elements of the delay element circuit 164 when the I_LOAD is in the low load region. V_ISEN is below the threshold voltage level to turn on comparators U2 and U1. Specifically, the inverting input voltages exceed the non-inverting input voltages, thereby causing the CON1 and CON2 outputs of comparators U1 and U2 to be low. With the output signal CON1 and CON2 low, switches S1a and S2a are off. With switches S1a and S2a off, capacitors C1a, C2a, and C3a form a series connection between the input of first OR gate 160aand ground. This configuration minimizes equivalent capacitance between the input to OR gate 160a and ground, and the corresponding delay. For the circuit of FIG. 3B, the signal to turn FETQ1 to an off state has a delay of about 20 ns when I_LOAD is in the low level region. FIG. 4 depicts exemplary waveforms representing such a delay. As stated above, skilled artisans will understand that the capacitance between the drain and source off switch S1a may be implemented using the Coss of FET S1a if the timing requirements meet the design criteria.

[0040] FIG. 3C illustrates the circuit path through selected capacitive elements of delay element circuit 164 when I_LOAD is in the mid-load region. When I_LOAD is in the mid-load region, V_ISEN is above the threshold level for comparator U1 to turn on, driving CON1 high. CON1 then turns on the switch S1a, effectively, shorting capacitor C1a and placing capacitors C2a and C3a in series between the input to OR gate 160a and ground. The equivalent series capacitance of C2aand C3a exceeds the equivalent series capacitance of capacitors C1a, C2a and C3a. For the circuit of FIG. 3C, the signal to turn FETQ1 off has a delay of about 100 ns. FIG. 5 depicts exemplary waveforms representing such a delay.

[0041] FIG. 3D illustrates the circuit path through selected capacitive elements of delay element circuit 164 when I_LOAD is in the heavy load region. In this scenario, V_ISEN is above the threshold level for comparators U1 and U2 to turn on, thereby driving CON1 and CON2 is high. This activates switches S1aand S2a. Activating switch S1a causes the circuit to operate similarly as described above. Activating switch S2a provides a current path from capacitor C3a, through switch S2a, to ground. This leaves only capacitor C3a between the input to OR gate 160a and ground. The equivalent capacitance of capacitor C3aexceeds the equivalent capacitance of the series connection of capacitors C2aand/or C3a, thereby increasing the delay. For the circuit of FIG. 3D, the signal to turn FETQ1 has a delay of approximately 150 ns. FIG. 6 depicts exemplary waveforms representing such a delay.

[0042] From the description of FIGS. 3A-3D, skilled artisans will appreciate that various components of the circuits described herein may have various values. Exemplary values for selected components are provided in the attached figures. One skilled in the art will further appreciate that the values shown in the figures may vary in accordance with various design criteria for implementing the present invention.

[0043] From the embodiments described herein, it will be apparent that the turn-off delay of the synchronous rectifier control increases as the I_LOADincreases. Similarly, the turn-off delay of the synchronous rectifier decreases when I_LOAD decreases. FIG. 7 shows a graphical example of the linear relationship between the turn-off delay and the I_LOAD.

[0044] This process of delaying the signal to turn-off a synchronous rectifier reduces or eliminates the body diode conduction through the synchronous rectifier FETQ1, FETQ2, thereby increasing the efficiency of power converter 100. Referring to FIGS. 8 and 9, the power converter 100 of the present invention increases the efficiency and reduces power loss. The power converter used to generate FIGS. 8 and 9 used a 12V/110 A phase shifted ZVS full bridge power supply operating at 300 kHz. FIGS. 8 and 9 depict curves corresponding to a power converter operating without and with the delay circuit of the present invention.

[0045] One skilled in the art will recognize that numerous relationships between the load current and turn-off delay exist. FIG. 10 shows a stepped relationship between the turn-off delay and the load current. For example, one skilled in the art will recognize that N discrete steps relating load current regions and turn-off delay may be utilized. In the embodiment of FIGS. 3A-3D, three discrete steps were utilized. One skilled in the art will also recognize that both linear and non-linear relationships between turn-off delay and load current may be implemented.

[0046] FIG. 11 shows an alternate embodiment for generating a delay to turn off a synchronous rectifier. FIG. 11 is a schematic diagram of a control circuit 400 which may be substituted for delay circuits 170a, 170b of delay element section 164 of FIGS. 3A-3D. FIG. 11 utilizes BJTs in place of FETs for switches S1a and S2a. BJTs provide a relatively low output capacitance compared to the FETs. BJTs thus provide a delay that more closely attains zero current in the body diode of the synchronous rectifiers FETQ1 and FETQ2. In the configuration of FIG. 11, freewheeling diodes DS1a and DS2a provide a discharge path for the capacitors C2a and C3a.

[0047] FIG. 12 depicts a diagram of a current sensing circuit 200 used to sense I_LOAD and generate I_SEN. Current sensing circuit 200 is implemented as a half-wave capacitive-filter rectifier having an output connected to a buffer amplifier. A current transformer 190 is arranged to sense the load current I_PRI at the primary side. The secondary winding of transformer 190 connects to a diode 194 and load resistor 196. A filter capacitor 198 in parallel with resistor 196 provides filtering of the rectified signal. Buffer amplifier 192 outputs the sense signal I_SEN to the input of delay selection section 162 of FIGS. 3A-3D. Resistor R101 and capacitor C101 cooperate to provide a low pass filter function for I_SEN.

[0048] While the invention has been described in its presently preferred form, it will be understood that the invention is capable of modification without departing from the spirit of the invention as set forth in the appended claims.