Normal mode and green mode pulse width modulation controller

[0001] 1. Field of the Invention

[0002] The present invention relates to power consumption reduction. More specifically, the present invention discloses an improved pulse width modulation controller with normal mode and green mode operation that increases the efficiency of the power supply and lowers power dissipation during relatively light load or no load conditions.

[0003] 2. Description of the Prior Art

[0004] A main component of a switching mode power converter is the pulse width modulation controller. During normal operation, the controller drives the power converter at a fixed frequency. However, conventional power converters waste power during light load or no load conditions since the controller continues driving the power converter at the fixed frequency regardless of the load. At light load the power delivered to the load is “light” while the energy used to deliver the power remains about the same, thus its efficiency drops significantly in light or no load. In order to overcome this problem, green power supplies were created.

[0005] Green power supplies are power converters that reduce power consumption during light and standby modes. Commonly, this is achieved using burst mode operation or switching frequency reduction under light load or no load conditions.

[0006] In burst mode, the PWM driver sends a number of pulses depending on the load. For heavier loads more pulses are sent and for lighter loads fewer pulses are sent.

[0007] In a green power supply utilizing frequency change, the controller changes the switching frequency to a low value thereby reducing losses related to switching. This increases the efficiency of the power supply. With this type of controller the frequency of the drive signal changes while the ON time of the pulse remains constant, sometimes known as Constant ON control.

[0008] However, it can be difficult to design circuitry that provides smooth transitions between normal mode and green mode.

[0009] Additionally, in low power applications, the efficiency of the power supply becomes critical.

[0010] Therefore, there is need for an improved pulse width modulation controller that smoothly transitions between normal mode and green mode in order to increase the efficiency of the power supply and lowers power dissipation during light load or no load conditions.

[0011] To achieve these and other advantages and in order to overcome the disadvantages of the conventional method in accordance with the purpose of the invention as embodied and broadly described herein, the present invention provides a pulse width modulation controller with normal mode and green mode driver signals.

[0012] An objective of the present invention is to provide a pulse width modulation (PWM) controller that smoothly and effectively transitions between normal mode and green power mode. During heavy load conditions, the PWM controller emits a normal mode drive signal. As the load lightens, the PWM controller emits a drive signal with shorter and shorter ON-time. The PWM controller enters green mode when the ON time of the drive signal falls below an adjustable predetermined pulse width threshold. In this mode the controller begins storing the pulse ON times without releasing the pulses to the driver. When the stored ON time reaches an adjustable predetermined total ON time threshold, the green mode driver releases a drive signal with a pulse ON time equal to or related to the total ON time threshold. The release of the green mode drive signal also occurs when the output voltage of the converter falls below a predetermined value. The reduced switching reduces power consumption thereby improving the efficiency of the power converter while maintaining the converter output voltage within a specified range.

[0013] The PWM controller of the present invention basically comprises a pulse width detector, a pulse ON time measurer, pulse ON time releaser, and a driver. The driver provides a PWM signal to the converter during normal operation. The pulse width detector detects the pulse width of the PWM signal. When the load is being reduced into a light or no load condition, the ON time of the PWM signal will drop. If the ON time drops below an ON time threshold, the pulse width detector indicates to the pulse ON time measurer that the PWM controller is no longer in normal mode. During the time that the pulse width is below the ON time threshold, the normal drive signal will turn off (driver signals are not released) and the pulse ON time measurer will begin storing the pulse ON time.

[0014] When the total ON time of the pulse signal reaches a total ON time threshold the driver will emit (release) a pulse signal as a green mode drive signal. The ON time of the pulse signal is related to the total ON time threshold. When the driver sends the green mode drive signal the pulse ON time measurer will reset and again begin storing the pulse ON times. The controller remains in green mode until the ON time of the pulse rises back above the ON time threshold.

[0015] Typically the driver will only send a green mode drive signal every time the total ON time reaches the total ON time threshold. However, if the output voltage drops below a voltage limit, the driver will send (release) a green mode drive signal to the power converter regardless of whether the total ON time has reached the total ON time threshold. In this situation, the green mode drive signal comprises a pulse with an ON time equal to the total ON time or a ratio of the total ON time.

[0016] The driver will continue sending the green mode driver signal when the above green mode conditions are met until an increase in load beyond what is considered to be light load occurs. During such a condition, the green mode driver signal will be shut off and the driver will resume sending the normal mode driver signal.

[0017] By switching to green mode during low load or no load conditions, the PWM controller of the present invention effectively reduces power consumption. Additionally, the reduced switching reduces power loss.

[0018] These and other objectives of the present invention will become obvious to those of ordinary skill in the art after reading the following detailed description of preferred embodiments.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0025] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0026] Refer to FIG. 1, which is a drawing illustrating the components of a PWM controller according to an embodiment of the present invention.

[0027] As shown in FIG. 1, the PWM controller 100 of the present invention basically comprises a first logic device 110, a pulse width detector 120, a second logic device 130, a pulse width ON time measurer 140, an ON time releaser 150, and a driver 190.

[0028] The first logic device 110 performs normal mode driver functions. The pulse width detector 120 detects the pulse width of a PWM signal. If the pulse width of the PWM signal is above a pulse width threshold, the pulse width detector 120 enables the first logic device 110 and the driver 190 outputs the PWM signal as a normal mode driver signal. During heavy load conditions, the pulse width or pulse ON time will be larger. As the load lightens, the pulse ON time will become shorter. If the pulse width of the PWM signal drops to below the pulse width threshold, the pulse width detector 120 disables the first logic device 110 and the driver 190 ceases outputting the normal mode driver signal.

[0029] While the pulse width is below the pulse width threshold the pulse width detector 120 enables the second logic device 130 which directs the PWM signal to the pulse width ON time measurer 140. The pulse width ON time measurer 140 begins storing the ON time of the PWM signal. When the total ON time of the PWM signal reaches a total ON time threshold, the ON time releaser 150 outputs a drive signal with a pulse width ON time in a ratio of the total ON time threshold. Additionally, if the output voltage drops below a voltage limit, the ON time releaser 150 outputs a pulse signal to the driver 190 which outputs a green mode drive signal. The pulse width of the green mode drive signal is a ratio the stored total ON time.

[0030] When the pulse width of the PWM signal rises above the pulse width threshold, the pulse width detector 120 disables the second logic device 130 and the green mode driver signal is turned off and the normal mode driver signal is enabled.

[0031] As a result, the PWM controller 100 of the present invention smoothly transitions between normal mode and green mode.

[0032] The pulse width threshold and total ON time threshold are selectable to meet system requirements.

[0033] Refer to FIG. 2, which is a diagram illustrating components of a PWM controller according to an embodiment of the present invention.

[0034] As shown in FIG. 2, the PWM controller 100 of the present invention comprises a pulse width detector 120, a first AND gate 110, a second AND gate 130, a pulse ON time measurer 140, an ON time releaser 150, an error amplifier 160, a first comparator 170, a second comparator 180, and a driver 190.

[0035] The first AND gate 110 functions the same as the first logic device of FIG. 1.

[0036] The error amplifier comprises a positive input connected to a reference voltage Vref and a negative input connected to the output voltage for providing a feedback signal to the error amplifier 160. The output of the error amplifier 160 is connected to the negative input of the first comparator 170. A sawtooth signal is supplied to the positive input of the first comparator 170.

[0037] When the feedback signal voltage is below Vref, the error amplifier 160 outputs a ramp signal with a positive slope. When the feedback signal voltage is above Vref, the error amplifier outputs a ramp signal with a negative slope. During the time the sawtooth signal voltage is greater than the error amplifier output voltage, the first comparator outputs a logic high. During the time the sawtooth signal voltage is below the error amplifier output voltage, the first comparator outputs a logic low.

[0038] In this way, the error amplifier 160 and the first comparator 170 produce a PWM signal on the output of the first comparator 170. The output of the first comparator is connected to an input of the first AND gate 110, the second AND gate 130, and the pulse width detector 120.

[0039] The pulse width detector 120 detects the pulse width of the PWM signal. When the pulse width is above a pulse width threshold, the pulse width detector 120 outputs a logic high or one to the second input of the first AND gate 110 which enables the first AND gate to output the PWM signal to the driver 190 which outputs the signal as a normal mode driver signal. During this time, the pulse width detector 120 outputs a logic low or zero to the second input of the second AND gate 130 which holds the output of the second AND gate low and disables the pulse ON time measuring device 140.

[0040] When the pulse width is below the pulse width threshold, the pulse width detector 120 outputs a low to the first AND gate 110 which holds the output of the first AND gate low effectively disabling the first AND gate 110 and the driver 190 ceases outputting the normal mode drive signal. During this time the pulse width detector 120 outputs a high to the second AND gate 130 which enables the second AND gate 130 to supply the PWM signal to the pulse ON time measuring device 140.

[0041] At this time the pulse ON time measuring device 140 begins storing the ON times of the PWM signal. When the total ON time reaches a total ON time threshold, the ON time releaser 150 will output a pulse signal to the driver 190 which outputs the pulse as a green mode drive signal. The pulse ON time of the pulse signal is a ratio of the total ON time threshold.

[0042] Connected to a second input of the ON time releaser 150 is a second comparator 180. The positive input of the second comparator 180 is connected to the output voltage for providing a feedback signal to the second comparator 180. The negative input of the second comparator 180 is connected to a voltage limit Vlimit.

[0043] When the output voltage drops below Vlimit the ON time releaser outputs a pulse signal with a pulse ON time as a ratio of the stored total ON time. During green mode, the driver continues to output the green mode drive signal at intervals when the total ON time reaches the total ON time threshold or the output voltage drops to Vlimit.

[0044] When the pulse width detector 120 detects that the pulse width has returned to above the pulse width threshold, the pulse width detector 120 disables the second AND gate 130 and enables the first AND gate 110 and the PWM controller returns to operating in normal mode.

[0045] In this way, the PWM controller of the present invention transitions smoothly between normal mode and green mode in response to heavy load, light load, or no load conditions. As a result, the present invention efficiently reduces power consumption.

[0046] Refer to FIG. 3A, which is a timing diagram illustrating waveforms of various signals of a PWM controller during normal mode operation according to an embodiment of the present invention and to FIGS. 3B-3D, which are timing diagrams illustrating waveforms of various signals of a PWM controller during green mode operation according to an embodiment of the present invention.

[0047] During normal mode operation, the output of the logic gate (element 110 in FIGS. 1 and 2) is a PWM signal and the output of the ON time releaser (element 150 in FIGS. 1 and 2) is low or a logic zero. The output voltage Vout is a sawtooth signal with a duty cycle equal to or nearly equal to the duty cycle of the PWM driver signal. As shown in FIG. 3A, for heavy load conditions the ON time of the drive signal is greater than light load conditions. As the load lightens the ON time reduces. When the ON time of the signal is shorter than the pulse width threshold, the controller enters green mode. During green mode operation the output of the first logic gate is low since the logic gate is disabled.

[0048] In order to clarify detailed operation of the controller of the present invention, the following example is given. It should be noted that the values given in the example are only for clarity. The values can be changed to meet system requirements. For example, the 80% value for the heavy load condition could be 50%, 60%, or other value.

[0049] During heavy load as shown in FIG. 3A the ON time or pulse width of the signal could be 80% of the duty cycle. As the load lightens the ON time reduces to, for example, 20%.

[0050] Refer to FIG. 3C, when the ON time is less than the pulse width threshold, the controller enters green mode and the ON time measurer begins storing the ON time of the signal. When the total ON time of the signal reaches the total ON time threshold, the ON time releaser outputs a drive signal. The pulse width is a ratio of the ON time threshold. For example, if the ON time of the first pulse in FIG. 3C is 4% and the ON time of the second pulse is 9% and the total ON time threshold is 12%, the ON time releaser can output a signal with an ON time of 12%. The total ON time of the first pulse and second pulse equals 13% which is greater than the total ON time threshold. If the third, fourth, and fifth pulses are each 4% with a total ON time of 12%, the green mode driver can output a pulse with an ON time of 12% after the fifth pulse. The green mode driver will continue operating in this fashion as long as Vout is greater than Vlimit and the pulse width is less than the pulse width threshold.

[0051] Refer to FIG. 3B, during green mode the ON time releaser will output a signal if Vout drops below a Vlimit regardless if the total ON time threshold has been reached. If the ON time of the first pulse in FIG. 3B is 2% and the ON time of the second pulse is 4%, the total ON time is 6%. If the total ON time threshold is 10%, the threshold hasn't been reached. However, at the time Vout drops to Vlimit, the ON time releaser will output a pulse signal.

[0052] In FIG. 3D the above two green modes are combined. For the first green mode driver output pulse, the total ON time threshold has been reached. For the second green mode driver output pulse, Vout has reached Vlimit.

[0053] Due to the reduced switching of the green mode driver signal, power consumption is reduced considerably during green mode operation.

[0054] It should be noted that the AND gates illustrated in FIG. 2 can be other types of logic devices.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the invention and its equivalent.