Conversion of interlaced video streams into progressive video streams

[0001] 1. Field of the Invention

[0002] The present invention relates to digital image and video processing. More specifically, the present invention relates to methods of converting interlaced video streams into progressive (i.e., non-interlaced) video streams.

[0003] 2. Discussion of Related Art

[0004] Due to advancing semiconductor processing technology, integrated circuits (ICs) have greatly increased in functionality and complexity. With increasing processing and memory capabilities, many formerly analog tasks are being performed digitally. For example, images, audio and even full motion video can now be produced, distributed, and used in digital formats.

[0005] FIG. 1 is an illustrative diagram of a portion of interlaced digital video stream 100 most often used in television systems. Interlaced digital video stream 100 comprises a series of individual fields 100_1 to 100_N, of which the first ten fields are shown. Even fields contain even numbered rows while odd fields contain odd numbered rows. For example if a frame has 400 rows of 640 pixels, the even field would contains rows 2, 4, . . . 400 and the odd field would contains rows 1, 3, 5, . . . 399 of the frame. In general for an interlaced video stream each field is formed at a different time. For example, an interlaced video capture device (e.g. a video camera) captures and stores the odd scan lines of a scene at time T as field 100_1, then the video capture device stores the even scan lines of a scene at time T+1 as field 100_2. The process continues for each field. Two main interlaced video standards are used. The PAL (Phase Alternating Line) standard, which is used in Europe, displays 50 fields per seconds and the NTSC (National Television System Committee) standard, which is used in the United States, displays 60 fields per seconds.

[0006] Interlaced video systems were designed when bandwidth limitations precluded progressive (i.e., non-interlaced) video systems with adequate frame rates. Specifically, interlacing two 25 fps fields achieved an effective 50 frame per second frame rate because the phosphors used in television sets would remain “lit” while the second field is drawn. Progressive video streams use complete frames, including both the even and odd scan lines instead of fields. Because progressive scan provides better display quality, computer systems, which were developed much later than the original television systems, use progressive scan display systems. Furthermore, many modern televisions and television equipment are being developed to use progressive video streams. To maintain compatibility with existing interlaced video systems, modern progressive systems use deinterlacing techniques to convert interlaced video streams into progressive video streams.

[0007] FIGS. 2(a) and 2(b) illustrate a typical method of generating a progressive video stream 200 from an interlaced video stream 100. Specifically each field 100_X of interlaced video stream 100 is converted to a frame 200_X of progressive video stream 200. The conversion of a field to a frame is accomplished by generating the missing scan lines in each frame by copying or interpolating from the scan lines in the field. For example, as illustrated in FIG. 2(b) field 100_1 having odd scan lines 100_1_1, 100_1_3, 100_1_5, . . . 100_1_N, is converted into 200_1 by copying scan lines 100_1_X as odd scan lines 200_1_X, where X is an odd number and creating even scan lines 200_1_Y, where Y is an even number. Even scan lines 200_1_Y can be created by copying the preceding odd scan line 200_1_Y-1. This technique is commonly known as line repeat. Better results can be obtained using various interpolation schemes to generate the missing scan lines. For example, one interpolation scheme simply averages odd scan line 200_1_Y−1 with odd scan line 200_1_Y+1 to generate even scan line 200_1_Y. Other interpolation schemes may use weighted averages or other more complicated ways to combine data from the existing scan lines to generate the missing scan lines. Another normal mode deinterlacing technique known as 3D deinterlacing involves generating the missing scan lines by interpolating the missing pixels using data from adjacent fields. Deinterlacing by interpolation is not an integral part of the present invention. The principles of the present invention can easily be adapted to use any form of interpolation. However, many types of video streams are initially created as progressive video streams and then converted into interlaced video streams. For example, conventional motion pictures are captured and displayed using 24 frames per seconds. To display motion pictures on a PAL (interlaced 50 fields/second) display, each frame is separated into an odd field and an even field. Furthermore, PAL video devices are configured to slightly increase the field rate of the output interlaced video stream to achieve 50 fields/seconds. FIG. 3 illustrates this process. Specifically, FIG. 3 shows the first five frames M_1 to M_5 of a motion picture video stream MPVS being converted to 10 fields of an interlaced video stream 300. Field 300_1 includes the odd scan lines of frame M_1. Field 300_2 includes the even scan lines of frame M_1. Field 300_3 includes the odd scan lines of frame M_2 and Field 300_4 includes the even scan lines of frame M_2. In general a frame M_X is divided into an odd field 300_(X−1)*2+1 containing the odd lines of frame M_X and an even field 300_(X−1)*2+2 containing the even lines of frame M_X. For clarity, portions of interlaced video streams formed from an initial progressive video stream are said to be in “converted mode”.

[0008] While displaying interlaced video stream 300 on interlaced video systems provide adequate picture quality. Conventional deinterlacing techniques as described above and illustrated in FIGS. 2(a) and 2(b) can be used by a progressive scan display system to view interlaced video stream 300. However, the picture quality of a de-interlaced video stream formed from interlaced video stream 300 is much lower than the picture quality of the original progressive video stream that was used to create interlaced video stream 300.

[0009] Hence, there is a need for a deinterlacing method or system that can determine whether portions of an interlaced video stream are in normal mode (e.g. like a normal television signal) or in a converted mode (e.g. formed from an original progressive video stream). The method or system must then deinterlace the given interlaced video stream appropriately.

[0010] Accordingly, the present invention provides a method and system for deinterlacing an interlaced video stream that determines whether portions of an interlaced video stream are in normal mode or in converted mode. Interlaced video streams in converted mode are deinterlaced using converted mode deinterlacing, which involves merging two fields to form a frame. Interlaced video streams in normal mode video streams are deinterlaced using normal mode deinterlacing, which involves converting a field into a frame using line repeating or some form of interpolation to generate the missing scan lines.

[0011] Specifically, in one embodiment of the present invention, a deinterlacing system includes a buffer for storing fields of the input interlaced video stream, a mode detector for determining whether portions of the input interlaced video stream is in converted mode or normal mode, and a field merging and conversion unit to perform either normal mode deinterlacing or converted mode deinterlacing on the input interlaced video stream to create an output progressive video stream. Within the mode detector, a mode detection parameter calculation unit calculates mode detection parameters for current field using both the current field and a preceding field. The mode detection parameters are stored in a mode detection parameter FIFO. A mode analysis unit determines whether a subset of the mode detection parameters in the mode detection parameter FIFO matches an alternating peak-valley pattern which indicates that the current portion of the input interlaced video stream might be in converted mode.

[0012] In some embodiments of the present invention, the mode analysis unit includes a peak valley pattern checker. The peak valley checker detects alternating peak valley patterns using data from the mode detection FIFO. In one embodiment of the present invention, the peak valley checker includes a peak detector and a valley detector. The peak detector is configured to detect an alternating peak valley pattern having a peak at a mode detection parameter corresponding to a specific field, such as the current field or the processing field. The valley detector is configured to detect an alternating peak valley pattern having a valley at a mode detection parameter corresponding to the specific field.

[0013] The present invention will be more fully understood in view of the following description and drawings.

[0023] As explained above, interlaced video streams can be in normal mode or converted mode. Many interlaced video streams may also switch back and forth between normal mode and converted mode. To use interlaced video streams on progressive video systems, a deinterlacing system is used to convert the interlaced video stream into a de-interlaced video stream. However, different deinterlacing techniques are used depending on whether the current portion of the incoming interlaced video stream is in converted mode or normal mode.

[0024] FIG. 4 illustrates a method of generating a progressive video stream 400 from interlaced video stream 300, which is in converted mode because interlaced video stream 300 was formed using the interlacing process described above from motion picture video stream MPVS (FIG. 3). Rather than simply converting a field into a frame, embodiments of the present invention merge two fields of a converted mode video stream into a frame. For example, frame 400_1 is formed by merging fields 300_1, which includes the odd scan lines of frame MP_01 (FIG. 3), and field 300_2, which includes the even scan lines of frame MP_01. Thus, frame 400_1 should be the same as frame MP_01. Frame 400_2 can be formed in the same way by merging fields 300_1, which includes the odd scan lines of frame MP_01 (FIG. 3), and field 300_2, which includes the even scan lines of frame MP_01. Frame 400_3 is formed by merging field 300_3, which includes the odd scan lines of frame MP_02, and field 300_4, which includes the even scan lines of frame MP_02. Thus, in general a frame 400_Y, where Y is an odd integer, is formed by merging field 300_Y and 300_Y+1. As illustrated in FIG. 3, field 300_Y contains the odd scan lines of frame M_X, where X is equal to Y plus 1 divided by 2 (i.e. X=(Y+1)/2). Similarly, Field 300_Y+1 contains the even scan lines of frame M_X. Thus, a frame 400_Y formed by merging the odd and even scan lines of Frame M_X, where X is equal to Y plus 1 divided by 2 (i.e. X=(Y+1)/2). Frame 400_Y+1 can be formed by merging fields 300_Y and 300_Y+1 in the same manner as forming frame 400_Y.

[0025] Table 2 summarizes the relationship of the frames of progressive video stream 400 and the scan lines of motion picture video stream MPVS, in which Y is an odd integer.

[0026]

	TABLE 2
	Frame	Content
	400_1	ALL scan lines of MP_01
	400_2	ALL scan lines of MP_01
	400_3	ALL scan lines of MP_02
	400_4	ALL scan lines of MP_02
	400_5	ALL scan lines of MP_03
	400_6	ALL scan lines of MP_03
	400_7	ALL scan lines of MP_04
	400_8	ALL scan lines of MP_04
	400_9	ALL scan lines of MP_05
	400_10	ALL scan lines of MP_05
	400_Y	ALL scan lines of MP_((Y + 1)/2)
	400_Y + 1	ALL scan lines of MP_((Y + 1)/2)

[0027] Thus, deinterlacing of a converted mode interlaced video stream by merging appropriate fields results in a new progressive video stream that repeats each frame of the original progressive stream that was used to form the converted mode video stream. The new progressive video stream has twice the frame rate of the original progressive video stream, and the new progressive video stream has similar quality to the original progressive video stream and much higher video quality than a progressive video stream formed using standard mode deinterlacing of the converted mode interlaced video stream.

[0028] The present invention determines whether portions of an interlaced video stream is in converted mode or normal mode by calculating a mode detection parameter MDP between each field i and field i−1, i.e. the field preceding field i. By analyzing the pattern of mode detection parameters for a series of fields, the present invention can determine whether portions of the incoming interlaced video stream are in converted mode or normal mode.

[0029] For clarity, the pixels of an incoming video stream is denoted as pixel p(i,j,k), where i is a field number of the incoming video stream, j is row in the field, and k is the column position within the field. In odd fields (i.e., fields with odd scan lines), j is an odd integer. Conversely, for even fields (i.e. fields with even scan lines), j is an even integer. Thus, for example pixel p(4, 6, 40) in incoming video stream 300 refers to the 40th pixel on row 6 of field 300_4, where the rows are numbered 2, 4, 6 etc. Similarly, pixel p(5, 7, 40) refers to the 40th pixel on row 7 of field 300_5, where the rows are numbered 1, 3, 5, 7, etc. Furthermore, fields of the incoming video stream are said to have H rows of W pixels. For an odd field the H rows are numbered as 1, 3, 5, . . . 2*H−1, i.e. j is an odd integer in the range of 1 to 2*H−1, inclusive. For an even field the H rows are numbered as 2, 4, 6, . . . 2*H, i.e. j is an even integer in the range of 2 to 2*H, inclusive. For both even and odd fields, the pixels are numbered from 1 to W, inclusive, i.e. k is an integer in the range of 1 to W, inclusive.

[0030] In one embodiment of the present invention, the mode detection parameter is equal to the number of non-still pixels in a field that is significantly larger than both a corresponding pixel on a previous line in the previous field and a corresponding pixel on a next line in the previous field or significantly smaller than both corresponding pixels on the next and previous lines in the previous field. Specifically, mode detection parameter MDP(i) of a field i is equal to the number of non-still pixels in field i which satisfy the following conditions: the luminance of a non-still pixel p(i, j, k) in field i minus the luminance of a pixel p(i−1, j−1, k) in field i−1 is greater than a detection threshold T_D and the luminance of non-still pixel p(i, j, k) in field i minus the luminance of the pixel p(i−1, j+1, k) in field i−1 is greater than detection threshold T_D, or the luminance of the non-still pixel p(i, j, k) in field i minus the luminance of the pixel p(i−1, j−1, k) in field i−1 is less than negative one times detection threshold T_D and the luminance of non-still pixel p(i, j, k) in field i minus the luminance of the pixel p(i−1, j+1, k) in field i−1 is less than negative one times detection threshold T_D. As stated above, for pixel p(i, j, k), j takes the values of odd integers 1, 3, 5, . . . , 2*H−1 when field i is an odd field, and takes the values of even integers 2, 4, 6, . . . , 2*H when field i is an even field. For convenience the luminance of a pixel p(i, j, k) is referenced as luminance lp(i, j, k). Equations EQ01a and EQ01b show symbolically how to calculate mode detection parameter MDP(i) for an odd field. In equations EQ01a and EQ01b a variable n is used in place of j; however j is equal to two times n minus 1 (i.e., j=2*n−1).

[0031] $\begin{array}{cc}\mathrm{MDP}\left(i\right)=\sum _{n=2}^H\sum _{k=1}^{W}1\mathrm{diff}\left[p\left(i,2*n-1,k\right),p\left(i-1,2*n-2,k\right),p\left(i-1,2*n,k\right)\right]& \left(\mathrm{EQ}01a\right)\\ 1\mathrm{diff}=\{\begin{array}{c}1,\{\begin{array}{c}\mathrm{IF}\mathrm{pixel}p\left(i,2*n-1,k\right)\mathrm{in}\mathrm{field}i\mathrm{is}\mathrm{non}\text{-}\mathrm{still},\mathrm{AND}\\ \left[\begin{array}{c}[(1p\left(i,2*n-1,k\right)-\\ 1p\left(i-1,2*n-2,k\right)>\mathrm{T\_D})\mathrm{AND}\\ (1p\left(i,2*n-1,k\right)-\\ 1p\left(i-1,2*n,k\right)>\mathrm{T\_D})]\\ \mathrm{OR}\\ [(1p\left(i,2*n-1,k\right)-\\ 1p\left(i-1,2*n-2,k\right)<-\mathrm{T\_D})\mathrm{AND}\\ (1p\left(i,2*n-1,k\right)-\\ 1p\left(i-1,2*n,k\right)<-\mathrm{T\_D})]\end{array}\right]\end{array}\\ 0,\mathrm{Otherwise}\end{array}& \left(\mathrm{EQ}01b\right)\end{array}$

[0032] Equations EQ02a and EQ02b show symbolically how to calculate mode detection parameter MDP(i) for an even field. In equations EQ02a and EQ02b, variable n is again used in place of j. However in Equations EQ02a and EQ02b, j is equal to two times n (i.e., j=2*n).

[0033] $\begin{array}{cc}\mathrm{MDP}\left(i\right)=\sum _{n=1}^{H-1}\sum _{k=1}^{W}1\mathrm{diff}\left[p\left(i,2*n,k\right),p\left(i-1,2*n-1,k\right),p\left(i-1,2*n+1,k\right)\right]& \left(\mathrm{EQ}02a\right)\\ 1\mathrm{diff}=\{\begin{array}{c}1,\{\begin{array}{c}\mathrm{IF}\mathrm{pixel}p\left(i,2*n,k\right)\mathrm{in}\mathrm{field}i\mathrm{is}\mathrm{non}\text{-}\mathrm{still},\mathrm{AND}\\ \left[\begin{array}{c}[(1p\left(i,2*n,k\right)-\\ 1p\left(i-1,2*n-1,k\right)>\mathrm{T\_D})\mathrm{AND}\\ (1p\left(i,2*n,k\right)-\\ 1p\left(i-1,2*n+1,k\right)>\mathrm{T\_D})]\\ \mathrm{OR}\\ [(1p\left(i,2*n,k\right)-\\ 1p\left(i-1,2*n-1,k\right)<-\mathrm{T\_D})\mathrm{AND}\\ (1p\left(i,2*n,k\right)-\\ 1p\left(i-1,2*n+1,k\right)<-\mathrm{T\_D})]\end{array}\right]\end{array}\\ 0,\mathrm{Otherwise}\end{array}& \left(\mathrm{EQ}02b\right)\end{array}$

[0034] In the embodiment of the present invention that uses equations EQ01a, EQ01b, EQ02a, and EQ02b, mode detection parameter MDP(i) measures the amount of a “saw tooth” artifact that exists in a frame formed by merging field i with field i−1.

[0035] Specifically, luminance difference ldiff determines whether there is a zigzag (i.e. saw tooth) change in the luminance at a non-still pixel in field i when field i is merged with field i−1. The “saw tooth” artifacts are caused by moving edges in the field. Accordingly, luminance difference ldiff is set equal to one only for non-still pixels (i.e. moving pixels), which satisfy the conditions given in EQ01b and EQ02b.

[0036] For a converted mode interlaced video signal, proper merging of fields would result in only a small amount of saw tooth artifacts. Proper merging refers to merging an odd field and an even field that were both derived from a single frame of a progressive video stream. For example, merging field 300_2 (FIG. 3) with field 300_1 would be a proper merge. Mode detection parameter MDP(i) would be a small value if merging field i and field i−1 is a proper merge. However, improper merging of fields would result in a large amount of saw tooth artifact. Improper merging refers to merging two fields that were not both derived from a single frame of progressive video stream. For example, merging field 300_3 (FIG. 3) with field 300_2 would be an improper merge. Mode detection parameter MDP(i) would be a large value if merging field i and field i−1 is an improper merge. Merging fields from a normal mode interlaced video stream produces random results for mode detection parameter MDP(i).

[0037] A deinterlacing system according to the present invention would calculate a series of mode detection parameters for a series of consecutive fields of an interlaced video stream. Depending on the specific content of the interlaced video stream, the deinterlacing system determines whether the current portion of the interlaced video stream is normal mode or converted mode. For a converted mode interlaced video stream (such as illustrated in FIG. 3) sequential mode detection parameters would exhibit an alternating peak-valley pattern having alternating peaks and valleys and in which the smallest peak is greater than the largest valley. However as explained in more detail with regards to FIGS. 6(a) and 6(b), the sequence of mode detection parameters for a normal mode interlaced video streams may also exhibit a peak-valley pattern for a short duration of fields. Thus, most embodiments of the present invention use additional criteria to determine the mode of the input video stream.

[0038] FIGS. 5(a)-5(c) illustrate mode detection parameters MDP(i) sequences generated from converted mode interlaced video streams having three common content types. FIG. 6(a) illustrates a typical mode detection parameter sequence for a normal mode interlaced video stream. FIG. 6(b) illustrates a specific mode detection parameter sequence generated from a normal mode interlaced video stream that mimics the mode detection parameter sequences of converted mode video streams. Deinterlacing according to the present invention uses the similarities of the mode detection parameter sequences of converted mode interlaced video streams and the differences between the sequences of mode detection parameters of converted mode interlaced video streams and the sequences of mode detection parameters of normal mode interlaced video streams to determine the mode of an input interlaced video stream.

[0039] FIG. 5(a) graphs mode detection parameter MDP(i) for a converted mode interlaced video stream having a moving object moving at a relatively constant rate. In FIG. 5(a), the valleys (i.e. low points) at i equals 2, 4, 6, . . . 14 indicate fields that should be merged with the preceding field. The peaks (i.e. high points) at i equals 3, 5, 7, . . . 13 indicate fields that should not be merged with the preceding field. As explained-above, moving edges causes large saw tooth patterns and thus large mode detection parameters on improper merges. Because the moving object is moving at a constant rate, the mode detection parameters for the improper merge are all of similar values.

[0040] FIG. 5(b) graphs mode detection parameter MDP(i) for a converted mode interlaced video stream having a moving object moving at an increasing rate. In FIG. 5(b), the valleys at i equals 2, 4, 6, . . . 14 indicate fields that should be merged with the preceding field. The peaks at i equals 3, 5, 7, . . . 13 indicate fields that should not be merged with the preceding field. As explained above, moving edges causes large saw tooth patterns and thus large mode detection parameters on improper merges. Because the moving object is moving at an increasing rate, the mode detection parameters for the improper merge are also increasing.

[0041] FIG. 5(c) graphs mode detection parameter MDP(i) for a converted mode interlaced video stream having a moving object moving at an decreasing rate. In FIG. 5(c), the valleys at i equals 2, 4, 6, . . . 14 indicate fields that should be merged with the preceding field. The peaks at i equals 3, 5, 7, . . . 13 indicate fields that should not be merged with the preceding field. As explained above, moving edges causes large saw tooth patterns and thus large mode detection parameters on improper merges. Because the moving object is moving at a decreasing rate, the mode detection parameters for the improper merge are also decreasing.

[0042] Similarities between FIGS. 5(a), 5(b), and 5(c), include an alternating peak-valley pattern, i.e. a large MDP, followed by a small MDP, followed by a large MDP, followed by small MDP, etc. However, normal mode interlaced video stream, which would generate a random pattern for a series of mode detection parameters MDP(i) may also exhibit the alternating peak-valley pattern for short durations. Specifically, as illustrated in FIG. 6(a), the sequence of mode detection parameters MDP(i) starting at MDP(7), i.e. i=7 to MDP(11), i.e. i=11, also display an alternating peak-valley pattern. However, because the sequence of mode detection parameters MDP(i) for normal mode interlaced video streams are random, the alternating peak-valley pattern usually does not persist over very many fields. Furthermore, an alternating peak-valley pattern for normal mode interlaced video streams usually does not satisfy the condition that the smallest peak is greater than the largest valley. Depending on the contents of the interlaced video stream some interlaced video stream may have a persistent alternating peak-valley pattern of mode detection parameters MDP(i). Specifically, when a normal mode interlaced video stream includes an object moving at a constant rate, the mode detection parameters MDP(i) for odd fields (fields containing odd scan lines) are all roughly equal and shown as odd mode detection parameter MDP_O in FIG. 6(b). Conversely, the mode detection parameters MDP(i) for even fields are all roughly equal and shown as even mode detection parameter MDP_E. Thus, these normal mode interlaced video streams also have a persistent alternating peak-valley pattern. However, the ratio between the peaks and valleys of normal mode interlaced video streams are usually smaller than for converted mode interlaced video streams. Thus, most embodiments of the present invention detect converted mode interlaced video streams by finding persistent alternating peak-valley patterns in which the smallest peak is greater than the largest valley, and the ratio of the peaks to the valleys are large.

[0043] FIG. 7 is a simplified block diagram of a deinterlacing system 700, which receives an input interlaced video stream I_IVS and generates an output progressive video stream O_PVS in accordance with one embodiment of the present invention. Deinterlacing system 700 includes a buffer 710, a mode detector 720, and a field merging and conversion unit 730. In the embodiment of FIG. 7, buffer 710 has M field buffers 710_1, 710_2, 710_3, . . . 710_M. Buffer 710 is used as a circular buffer so that the first field of input interlaced video stream I_IVS is written into field buffer 710_1, the second field of input interlaced video stream I_IVS is written into field buffer 710_2, the third field of input interlaced video stream I_IVS is written into field buffer 710_3. This process continues to the Mth field of input interlaced video stream I_IVS, which is written into field buffer 710_M. Then the (M+1)th field of input interlaced video stream I_IVS is written into field buffer 710_1, the (M+2)th field of input interlaced video stream I_IVS is written into field buffer 710_2, the (M+3)th field of input interlaced video stream I_IVS is written into field buffer 710_3, and so forth with the (M+M)th field of input interlaced video stream I_IVS is written into field buffer 710_M. This process continues for all the fields of input interlaced video stream I_IVS.

[0044] Thus, in general buffer 710 contains the M most recent fields from input interlaced video stream I_IVS. Deinterlacing system 700 generally uses various field pointers to track which field buffer contains the earliest field. For clarity, the most recent field in buffer 710 is referenced as current field i. The field preceding current field i is referenced as field i−1, the field preceding field i−1 is referenced as field i−2, and the oldest field in buffer 710 is referenced as field i−(M−1). Circular buffers are well known in the art and are typically implemented with various pointers to allow reading and writing at desired field locations.

[0045] Field merging and conversion unit 730 processes a processing field, which is referenced using a processing field parameter PF as field i−PF, to generate an output frame for output progressive video stream O_PVS. Processing field parameter PF represents a distance between the current field (i.e., field i) and the processing field (i.e., field i−PF). Field merging and conversion unit 730, which is controlled by mode detector 720 (as explained below), can be configured to perform converted mode deinterlacing or normal mode deinterlacing. For converted mode deinterlacing, field merging and conversion unit 730 merges the processing field with either the field that precedes the processing field or the field that follows the processing field to form a frame. For normal mode deinterlacing field merging and conversion unit 730 converts the processing field into a frame using conventional techniques such as interpolation, line repeat, or 3D deinterlacing. In the embodiment of FIG. 7, for converted mode deinterlacing, field merging and conversion unit 730 merges the processing field (i.e. field i−PF) with either field i−(PF−1) or field i−(PF+1) to form a frame. For normal mode deinterlacing field merging and conversion unit 730 converts field i−PF into a frame using conventional techniques such as interpolation, line repeat, or 3D deinterlacing. In general, the processing field is the second oldest field in buffer 710 (i.e. field i−(M−2)) because field merging and conversion unit 730 requires the field that precedes the processing field and the field that follows the processing field. Thus, the oldest field can not be used as the processing field. Furthermore, using the second oldest field as the processing field allows mode detector to analyze more fields to determine how to process the processing field as compared to using more recent fields as the processing field. However, some embodiments of the present invention allow a user to define different fields to be the processing field. Using a field more recent than the second oldest field in general allows faster reaction to changes from normal to converted mode (and converted to normal mode). However, the actual detection of normal or converted mode may be less accurate. In a specific embodiment of the present invention, field buffer 710 includes 4 (i.e., M=4) field buffers and the processing field is field i−2 (i.e., PF=2).

[0046] Mode detector 720 includes a mode detection parameter calculation unit 721, a mode detection parameter (MDP) FIFO 722, and a mode analysis unit 726. Mode detection parameter calculation unit 721 calculates a mode detection parameter MDP(i) (as described above) when each current field i is written into buffer 710. Mode detection parameter MDP(i) is written into MDP FIFO 722. The size in data words of MDP FIFO 722 is equal to a MDP FIFO size MFS. Specifically, MDP FIFO 722 includes data words 722_1 to 722_MFS. In general MDP FIFO size MFS should be greater than or equal to the distance between the processing field and the current field minus one (i.e., MFS≧PF−1).

[0047] MDP FIFO 722 is operated as a FIFO memory. As new data words are “pushed” into data word 722_1, data in data word 722_MFS is “popped” off. Specifically, when mode detection parameter calculation unit 721 needs to write a mode detection parameter into data word 722_1, The contents of data word 722_1 is copied into data word 722_2; the contents of data word 722_2 is copied into data word 722_3; the contents of data word 722_3 is copied into data word 722_4; and in general the contents of data word 722_X is copied into data word 722_X+1. Except that the contents of data word 722_MFS is not retained. In this manner, MDP FIFO 722 stores the MFS most recent mode detection parameters calculated by mode detection parameter calculation unit 721. FIFO memories are well known in the art and are not described in detail herein.

[0048] In mode detector 720, data words 722_X contains mode detection parameter MDP(i−X) which corresponds to field (i−X), in which field i is the field currently being input to the system, and mode detection parameter MDP(i−1) of field i−1 is saved in 722_1.

[0049] Mode analysis unit 726 examines the contents of MDP FIFO 722 to determine whether field merging and conversion unit should perform converted mode deinterlacing for the processing field (i.e. field i−PF in FIG. 7) by merging the processing field with either the field that precedes the processing field or the field that follows the processing field or normal mode deinterlacing for the processing field. In most embodiments of the present invention mode analysis unit 726 is configured to use the first P data words of MDP FIFO 722. In general, if the processing field is field i−(M−K) (i.e., PF=M−K), with K in the range of 2 to M−2, inclusive (i.e., 2≦K≦M−2), then MDP FIFO size MFS must be larger than or equal to M−K−1, and P is in the range of M−K−1 to MDP FIFO size MFS, inclusive (i.e., M−K−l≦P≦MFS).

[0050] In one embodiment of the present invention, mode analysis unit 726 first determines which of three possible conditions are indicated by the mode detection parameters and what actions to take based on the condition. The three conditions are as follows: 1) an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a valley, 2) an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a peak, and 3) no alternating peak-valley pattern. As explained above, mode detection parameter MDP(i−PF) measures the amount of a “saw tooth” artifact that exists in a frame formed by merging field i−PF with field i−(PF+1). Properly merged fields would result in small “saw tooth” artifacts. Thus, if mode detection parameter MDP(i−PF) is a peak, a frame formed by merging field i−PF with field i−(PF+1) is likely to be mismerged. Conversely, if mode detection parameter MDP(i−PF) is a valley, a frame formed by merging field i−PF with field i−(PF+1) is likely to be properly merged. Therefore, when mode analysis unit 726 detects an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a valley, mode analysis unit 726 causes field merging and conversion unit 730 to merge field i−PF (i.e., the processing field) with field i−(PF+1), (i.e., the field preceding the processing field). When mode analysis unit 726 detects an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a peak, mode analysis unit 726 causes field merging and conversion unit 730 to merge field i−PF (i.e. the processing field) with field i−(PF−1), (i.e. the field following the processing field). When mode analysis unit 726 does not detect an alternating peak valley pattern, mode analysis unit 726 causes field merging and conversion unit 730 to perform normal mode deinterlacing on field i−PF (i.e., the processing field).

[0051] To determine if the P most recent mode detection parameters (i.e., MDP(i−1), MDP(i−2), . . . MDP(i−P)) exhibit an alternating peak valley pattern, mode analysis unit 726 finds a minimum peak value MPV, which is the minimum mode detection parameter at the expected peaks of the P most recent mode detection parameters, and a maximum valley value MVV, which is the maximum mode detection parameter at the expected valleys of the P most recent mode detection parameters. If minimum peak value MPV multiplied by a valley to peak threshold T_VP is greater than maximum valley value MVV (i.e. MPV*T_VP>MVV) then the mode detection parameters satisfy the alternating peak-valley pattern.

[0052] To detect condition 1) an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a valley, mode detection parameter MDP(i−PF) is expected to be a valley. Thus, if an alternating peak valley pattern exists, the other expected valleys are mode detection parameters MDP(i−(PF−2*x)), MDP(i−(PF−2*(x−1))), . . . MDP(i−(PF−2)), MDP(i−PF), MDP(i−(PF+2)), . . . MDP(i−(PF+2*(y−1))), MDP(i−(PF+2*y)), where (PF−2*x) is greater than or equal to 1 and (PF+2*y) is less than or equal to P. Thus, for example if P is equal to 5 and PF is equal to 2, the expected valleys are mode detection parameters MDP(i−2) and MDP(i−4). Similarly if P is equal to 5 and PF is equal to 3, the expected valleys are mode detection parameters MDP(i−1), MDP(i−3), and MDP(i−5). When mode detection parameter MDP(i−PF) is expected to be a valley, mode detection parameter MDP(i−(PF−1)) is expected to be a peak. Therefore, the other expected peaks are mode detection parameters MDP(i−(PF−1−2*m)), MDP(i−(PF−1−2*(m−1))), . . . MDP(i−(PF−1−2)), MDP(i−(PF−1)), MDP(i−(PF−1+2)), . . . MDP(i−(PF−1+2*(n−1))), MDP(i−(PF−1+2*n)), where (PF−1−2*m) is greater than or equal to 1 and (PF−1+2*n) is less than or equal to P. Thus, for example if P is equal to 5 and PF is equal to 2, the expected peaks are mode detection parameters MDP(i−1), MDP(i−3), and MDP(i−5). Similarly if P is equal to 5 and PF is equal to 3, the expected peaks are mode detection parameters MDP(i−2) and MDP(i−4).

[0053] To detect condition 2) an alternating peak valley pattern with mode detection parameter MDP(i−PF) being a peak, mode detection parameter MDP(i−PF) is expected to be a peak. Thus, if an alternating peak valley pattern exists, the other expected peaks are mode detection parameters MDP(i−(PF−2*x)), MDP(i−(PF−2*(x−1))), . . . MDP(i−(PF−2)), MDP(i−PF), MDP(i−(PF+2)), . . . MDP(i−(PF+2*(y−1))), MDP(i−(PF+2*y)), where (PF−2*x) is greater than or equal to 1 and (PF+2*y) is less than or equal to P. Thus, for example if P is equal to 5 and PF is equal to 2, the expected peaks are mode detection parameters MDP(i−2) and MDP(i−4). Similarly if P is equal to 5 and PF is equal to 3, the expected peaks are mode detection parameters MDP(i−1), MDP(i−3), and MDP(i−5). When mode detection parameter MDP(i−PF) is expected to be a peak, mode detection parameter MDP(i−(PF−1)) is expected to be a valley. Therefore, the other expected valleys are mode detection parameters MDP(i−(PF−1−2*m)), MDP(i−(PF−1−2*(m−1))), . . . MDP(i−(PF−1−2)), MDP(i−(PF−1)), MDP(i−(PF−1+2)), . . . MDP(i−(PF−1+2*(n−1))), MDP(i−(PF−1+2*n)), where (PF−1−2*m) is greater than or equal to 1 and (PF−1+2*n) is less than or equal to P. Thus, for example if P is equal to 5 and PF is equal to 2, the expected valleys are mode detection parameters MDP(i−1), MDP(i−3), and MDP(i−5). Similarly if P is equal to 5 and PF is equal to 3, the expected valleys are mode detection parameters MDP(i−2) and MDP(i−4).

[0054] FIG. 8 is a block diagram of an embodiment of mode analysis unit 726 that operates mode detector 720 using a bi-modal approach. Specifically, the embodiment of FIG. 8 has a normal operating mode and a converted operating mode. In general, normal operating mode is used when the input interlaced video stream is in normal mode, and converted operating mode is used when the input interlaced video stream is in converted mode. While in normal operating mode, mode analysis unit 726 analyzes the mode detection parameters to determine when to switch to the converted operating mode. Similarly, while in converted operating mode, mode analysis unit 726 analyzes the mode detection parameters to determine when to switch to the normal operating mode. For clarity, the embodiment of FIG. 8 is described with the processing field parameter PF being an even number. However, use of odd processing field parameters is also summarized below.

[0055] The embodiment of FIG. 8 includes a processing field expected peak valley (P/V) characteristic register 810, a mode analysis controller 820, a peak valley (P/V) pattern checker 830, a converted operating mode transition threshold register 840, a operating mode switch counter 850, and a normal operating mode transition threshold register 860. Expected peak valley characteristic register 810 provides a processing field peak expected signal PFPE, which indicates whether the mode detection parameter corresponding with the processing field is expected to be a peak or a valley. Specifically, processing field peak expected signal PFPE is set to a TRUE value (e.g. Logic high) to indicate that mode detection parameter MDP(i−PF) (i.e. the mode detection parameter corresponding to the processing field) is expected to be a peak. Conversely, processing field peak expected signal PFPE is set to a FALSE value (e.g. logic low) to indicate that mode detection parameter MDP(i−PF) (i.e., the mode detection parameter corresponding to the processing field) is expected to be a valley. Processing field peak expected signal PFPE can be set to an initial value by a user through a control port 811. The initial value of processing field peak expected signal PFPE only affects the initial few frames of the output progressive video stream O_PVS. In one embodiment of the present invention the initial value of processing field peak expected signal PFPE is set to the TRUE value. Processing field peak expected signal PFPE is provided to mode analysis controller 820, which can also adjust the value of processing field peak expected signal PFPE through a control port 812.

[0056] Peak valley pattern checker 830 is configured to analyze mode detection parameters MDP(i−1), MDP(i−2), . . . MDP(i−P) to determine whether the alternating peak valley pattern (described above) is satisfied. In the embodiment of FIG. 8, peak valley pattern checker 830 includes a peak detector 834, a valley detector 836, and a still image detector 838. Peak detector 834 determines whether the mode detection parameters satisfy the alternating peak valley pattern beginning with a peak (i.e. mode detection parameter MDP(i−1) is a peak). Peak detector 834 generates a Boolean peak detected signal P_D, which is provided to mode analysis controller 820. In one embodiment of the present invention peak detected signal P_D is set equal to a TRUE value (e.g., logic high) when minimum peak value MPV multiplied by valley to peak threshold T_VP is greater than maximum valley value MVV (i.e. MPV*T_VP>MVV). Otherwise, peak detected signal P_D is set equal to a FALSE value (e.g., logic low). In peak detector 834, when P is an even number, maximum valley value is equal to the maximum value from among mode detection parameters MDP(i−2), MDP(i−4), . . . MDP(i−P) and minimum peak value MPV is equal to the minimum value from among mode detection parameters MDP(i−1), MDP(i−3), . . . MDP(i−(P−1)). When P is an odd number, maximum valley value MVV is equal to the maximum value from among mode detection parameters MDP(i−2), MDP(i−4), . . . MDP(i−(P−1)) and minimum peak value MPV is equal to the maximum value from among mode detection parameters MDP(i−1), MDP(i−3), . . . MDP(i−P).

[0057] Valley detector 836 determines whether the mode detection parameters satisfy the alternating peak valley pattern beginning with a valley (i.e., mode detection parameter MDP(i−1) is a valley). Valley detector 836 generates a Boolean valley detected signal V_D, which is provided to mode analysis controller 820. In one embodiment of the present invention valley detected signal V_D is set equal a TRUE value (e.g., logic high) when minimum peak value MPV multiplied by valley to peak threshold T_VP is greater than maximum valley value MVV (i.e. MPV*T_VP>MVV). Otherwise, valley detected signal V_D is set equal to a FALSE value (e.g., logic low). In valley detector 836, when P is an even number, maximum valley value MVV is equal to the maximum value from among mode detection parameters MDP(i−1), MDP(i−3), MDP(i−(P−1)) and minimum peak value MPV is equal to the minimum value from among mode detection parameters MDP(i−2), MDP(i−4), MDP(i−P). When P is an odd number, maximum valley value MVV is equal to the maximum value from among mode detection parameters MDP(i−1), MDP(i−3), . . . MDP(i−P) and minimum peak value MPV is equal to the minimum value from among mode detection parameters MDP(i−2), MDP(i−4), . . . MDP(i−(P−1)).

[0058] Still image detector 838 is used during converted operation mode to determine whether the input interlaced video stream contains a series of still fields, i.e. fields in which the images have little or no motion. When mode analysis controller 820 is operating in converted operating mode, the series of still fields should not cause a switch to normal operating mode. However, as explained above, the “saw tooth” patterns used to calculate the mode detection parameters only make use of non-still pixels. Thus, for still images, the calculated mode detection parameters are very small and may equal zero. Accordingly, peak detector 834 and valley detector 836 are unlikely to find the alternating peak valley pattern during the series of still fields. Therefore, still image detector 838 provides a Boolean still image detected signal to mode analysis controller 820 so that mode analysis controller 820 does not erroneously switch from converted operating mode to normal operating mode due to the series of still file. When a series of still fields is detected still image detector 838 drives still image detected signal SI_D to a TRUE value (e.g. logic high); otherwise, still image detector 838 drives still image detected signal SI_D to a FALSE value (e.g., logic low). In one embodiment of the present invention, a series of still fields is detected when all the mode detection parameters (i.e., MDP(i−1), MDP(i−2), . . . MDP(i−P)) are equal to zero. In another embodiment of the present invention, a series of still fields is detected when the X most recent mode detection parameters (i.e., MDP(i−1), MDP(i−2), . . . MDP(i−X)) are equal to zero, where X is equal to a user definable number of still field threshold T_NSF. In still another embodiment of the present invention, a series of still fields is detected when the X most recent mode detection parameters (i.e., MDP(i−1), MDP(i−2), . . . MDP(i−X)) is less than a user definable still field parameter threshold T_SFP, where X is equal to number of still fields threshold T_NSF.

[0059] Converted operating mode transition threshold register 840 stores a converted operating mode transition threshold T_CMT, which is user configurable. Converted operating mode transition threshold T_CMT dictates how many consecutive fields must match the alternating peak valley pattern for mode analysis controller 820 to switch from the normal operating mode to the converted operating mode. Normal operating mode transition threshold register 860 stores a normal operating mode transition threshold T_NMT, which is user configurable. Normal operating mode transition threshold T_NMT dictates how many consecutive fields must fail to match the alternating peak valley pattern for mode analysis controller 820 to switch from the converted operating to the normal operating mode. Mode analysis controller 820 uses mode switch counter 850 to track the number of consecutive matches or number of consecutive mismatches of the mode detection parameters with an alternating peak valley pattern. Mode analysis controller 820 can increment mode switch counter 850 using an increment signal INC and reset mode switch counter 850 using a reset signal RESET. Mode switch counter 850 provides a mode switch count MSC to mode analysis controller 820.

[0060] Mode analysis controller 820 operates as a state machine in either normal operating mode or the converted operating mode. Operation of Mode analysis controller 820 is described by a state diagram 900 of FIG. 9. State diagram 900 includes a normal state 910, which represents the normal operating mode, and a converted state 920, which represents the converted operating mode. Mode analysis controller 820 uses a plurality of status signals, variables, thresholds, and parameters, which are not shown in FIG. 9. As illustrated in FIG. 8, mode analysis controller 820 uses peak detected signal P_D, valley detected signal P_V, still image detected signal SI_D, normal operating mode transition threshold T_NMT, converted operating mode transition threshold T_CMT, mode switch count MSC, and processing field peak expected signal PFPE. Mode analysis controller 820 also uses a state variable STATE (not shown), which indicates under which state mode analysis controller 820 is operating. Specifically state variable STATE is equal to 0 when mode analysis controller 820 is operating in normal state 910. Conversely, state variable STATE is equal to 1 when mode analysis controller 820 is operating in converted state 920.

[0061] Upon power/on reset, the various user thresholds are defined, processing field peak expected signal PFPE is set to an initial value, and mode switch counter 850 is initialized to zero. Mode analysis controller 820 begins in normal state 910. From normal state 910, mode analysis controller 820 can take one of 8 transitions path T_N_C_1, T_N_C_2, T_N_N_1, T_—T_N_N_4, T_N_N_5, or T_N_N_6. For clarity the referen for the transitions paths are of the form T_X_Y_Z, where X indicates the starting state (N for normal state 910 and C for converted state 920), Y indicates the ending state, and Z enumerates the different transitions that can be taken from the same starting state to the same ending states. After each new mode detection parameter MDP(i−1) becomes available, mode analysis controller 820 follows a transition path and causes field merging and conversion unit 730 to create an output frame for output progressive video stream O_PVS(FIG. 7).

[0062] Mode analysis controller 820 takes transition path T_N_N_1 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the FALSE value, peak detected signal P_D is equal to the TRUE value, and mode switch count MSC is less than converted operating mode transition threshold T_CMT minus 1 (i.e., MSC<T_CMT−1). When mode analysis controller 820 takes transition path T_N_N_—1, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and changes the value of processing field peak expected signal PFPE to equal the TRUE value.

[0063] Mode analysis controller 820 takes transition path T_N_N_2 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the FALSE value, peak detected signal P_D is equal to the FALSE value, and valley detected signal V_D is equal to the TRUE value. When mode analysis controller 820 takes transition path T_N_N_2, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and keeps the value of processing field peak expected signal PFPE at the FALSE value.

[0064] Mode analysis controller 820 takes transition path T_N_N_3 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the FALSE value, peak detected signal P_D is equal to the FALSE value, and valley detected signal V_D is equal to the FALSE value. When mode analysis controller 820 takes transition path T_N_N_3, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the TRUE value.

[0065] Mode analysis controller 820 takes transition path T_N_N_4 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the TRUE value, valley detected signal V_D is equal to the TRUE value, and mode switch count MSC is less than converted operating mode transition threshold T_CMT minus 1 (i.e., MSC<T_CMT−1). When mode analysis controller 820 takes transition path T_N_N_4, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and changes the value of processing field peak expected signal PFPE to equal the FALSE value.

[0066] Mode analysis controller 820 takes transition path T_N_N_5 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the TRUE value, valley detected signal V_D is equal to the FALSE value, and peak detected signal P_D is equal to the TRUE value. When mode analysis controller 820 takes transition path T_N_N_5, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and keeps the value of processing field peak expected signal PFPE at the TRUE value.

[0067] Mode analysis controller 820 takes transition path T_N_N_6 from normal state 910 back to normal state 910 when processing field peak expected signal PFPE is equal to the TRUE value, valley detected signal V_D is equal to the FALSE value, and peak detected signal P_D is equal to the FALSE value. When mode analysis controller 820 takes transition path T_N_N_6, mode analysis controller 820 causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and changes value of processing field peak expected signal PFPE to equal the FALSE value.

[0068] Mode analysis controller 820 takes transition path T_N_C_1 from normal state 910 to converted state 920 when processing field peak expected signal PFPE is equal to the FALSE value, peak detected signal P_D is equal to the TRUE value, and mode switch count MSC is equal to converted operating mode transition threshold T_CMT minus 1 (i.e., MSC=T_CMT−1). When mode analysis controller 820 takes transition path T_N_C_1, mode analysis controller 820 causes field merging and conversion unit 730 to use converted mode deinterlacing to merge field i−PF with field i−(PF+1), resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the TRUE value.

[0069] Mode analysis controller 820 takes transition path T_N_C_2 from normal state 910 to converted state 920 when processing field peak expected signal PFPE is equal to the TRUE value, valley detected signal V_D is equal to the TRUE value, and mode switch count MSC is equal to converted operating mode transition threshold T_CMT minus 1 (i.e., MSC=T_CMT−1). When mode analysis controller 820 takes transition path T_N_C_2, mode analysis controller 820 causes field merging and conversion unit 730 to use converted mode deinterlacing to merge field i−PF with field i−(PF−1), resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the FALSE value.

[0070] Mode analysis controller 820 takes transition path T_C_C_1 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the FALSE value and either peak detected signal P_D or still image detected signal SI_D or both is equal to the TRUE value. When mode analysis controller takes transition path T_C_C_1, mode analysis controller causes field merging and conversion unit 730 to use converted mode deinterlacing to merge field i−PF and field i−(PF+1), resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the TRUE value.

[0071] Mode analysis controller 820 takes transition path T_C_C_2 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the FALSE value, valley detected signal V_D is equal to the TRUE value, mode switch count MSC is less than normal operating mode transition threshold T_NMT minus 1 (i.e., MSC<T_NMT−1), and both peak detected signal P_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_C_2, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and keeps the value of processing field peak expected signal PFPE at the FALSE value. Normal mode deinterlacing is used with transition path T_C_C_2 (as well as with transition paths T_C_C_3, T_C_C_5, and T_C_C_6), because the expected alternating peak valley pattern was not detected. A common cause of the loss of the expected alternating peak valley pattern is a bad edit in the formation of the converted mode interlaced video stream. For these bad edits, normal mode deinterlacing generally provides higher picture quality than field merging of possibly mismatched fields.

[0072] Mode analysis controller 820 takes transition path T_C_C_3 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the FALSE value, valley detected signal V_D is equal to the FALSE value, mode switch count MSC is less than normal operating mode transition threshold T_NMT minus 1 (i.e., MSC<T_NMT−1), and both peak detected signal P_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_C_3, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and changes the value of processing field peak expected signal PFPE to equal the TRUE value.

[0073] Mode analysis controller 820 takes transition path T_C_C_4 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the TRUE value and either valley detected signal V_D or still image detected signal SI_D or both is equal to the TRUE value. When mode analysis controller takes transition path T_C_C_4, mode analysis controller causes field merging and conversion unit 730 to use converted mode deinterlacing to merge field i−PF and field i−(PF−1), resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the FALSE value.

[0074] Mode analysis controller 820 takes transition path T_C_C_5 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the TRUE value, peak detected signal P_D is equal to the TRUE value, mode switch count MSC is less than normal operating mode transition threshold T_NMT minus 1 (i.e., MSC<T_NMT−1), and both valley detected signal V_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_C_5, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and keeps the value of processing field peak expected signal PFPE at the TRUE value.

[0075] Mode analysis controller 820 takes transition path T_C_C_6 from converted state 920 back to converted state 920 when processing field peak expected signal PFPE is equal to the TRUE value, peak detected signal P_D is equal to the FALSE value, mode switch count MSC is less than normal operating mode transition threshold T_NMT minus 1 (i.e., MSC<T_NMT−1), and both valley detected signal V_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_C_6, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, causes mode switch count MSC to increment by one, and changes the value of processing field peak expected signal PFPE to equal the FALSE value.

[0076] Mode analysis controller 820 takes transition path T_C_N_1 from converted state 920 to normal state 910 when processing field peak expected signal PFPE is equal to the FALSE value, valley detected signal V_D is equal to the TRUE value, mode switch count MSC is equal to normal operating mode transition threshold T_NMT minus 1 (i.e., MSC=T_NMT-1), and both peak detected signal P_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_N_—1, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and keeps the value of processing field peak expected signal PFPE at the FALSE value.

[0077] Mode analysis controller 820 takes transition path T_C_N_2 from converted state 920 to normal state 910 when processing field peak expected signal PFPE is equal to the FALSE value, valley detected signal V_D is equal to the FALSE value, mode switch count MSC is equal to normal operating mode transition threshold T_NMT minus 1 (i.e., MSC=T_NMT−1), and both peak detected signal P_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_N_2, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and changes value of processing field peak expected signal PFPE to equal the TRUE value.

[0078] Mode analysis controller 820 takes transition path T_C_N_3 from converted state 920 to normal state 910 when processing field peak expected signal PFPE is equal to the TRUE value, peak detected signal P_D is equal to the TRUE value, mode switch count MSC is equal to normal operating mode transition threshold T_NMT minus 1 (i.e., MSC=T_NMT−1), and both valley detected signal V_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_N_3, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and keeps the value of processing field peak expected signal PFPE at the TRUE value.

[0079] Mode analysis controller 820 takes transition path T_C_N_4 from converted state 920 to normal state 910 when processing field peak expected signal PFPE is equal to the TRUE value, peak detected signal P_D is equal to the FALSE value, mode switch count MSC is equal to normal operating mode transition threshold T_NMT minus 1 (i.e., MSC=T_NMT−1), and both valley detected signal V_D and still image detected signal SI_D are equal to the FALSE value. When mode analysis controller takes transition path T_C_N_4, mode analysis controller causes field merging and conversion unit 730 to use normal mode deinterlacing on field i−PF, resets mode switch count MSC to zero, and changes the value of processing field peak expected signal PFPE to equal the FALSE value.

[0080] The transition conditions and actions for mode analysis controller 820 are summarized in Tables 1(a), 1(b), 2(a), 2(b), 3(a), and 3(b). Specifically, Table 1(a) lists the condition for each transition path from normal stage 910, Table 1(b) lists the action for each transition path in Table 1(a), Table 2(a) lists the condition for each transition path from converted stage 920 when processing field peak expected signal PFPE is equal to the FALSE value, Table 2(b) lists the actions for each transition path in Table 2(a), Table 3(a) lists the condition for each transition path from converted stage 920 when processing field peak expected signal PFPE is equal to the TRUE value, Table 3(b) lists the actions for each transition path in Table 3(a). In the Tables, T is used for the TRUE value, F is used for the FALSE value, and X is used as a don't-care condition.

[0081]

TABLE 1(a)
PFPE	P_D	V_D	MSC	Transition Path
F	T	X	<(T_CMT − 1)	T_N_N_1
F	T	X	=(T_CMT − 1)	T_N_C_1
F	F	T	X	T_N_N_2
F	F	F	X	T_N_N_3
T	X	T	<(T_CMT − 1)	T_N_N_4
T	X	T	=(T_CMT − 1)	T_N_C_2
T	T	F	X	T_N_N_5
T	F	F	X	T_N_N_6

[0082]

	TABLE 1(b)
	Transition Path	Actions Taken
	T_N_N_1	MSC = MSC + 1; PFPE =
		T; NORMAL MODE DEINTERLACING
	T_N_C_1	MSC = 0; PFPE=T;
		MERGE FIELD i − PF and FIELD
		i − (PF + 1)
	T_N_N_2	MSC = 0; NORMAL MODE
		DEINTERLACING
	T_N_N_3	MSC = 0; PFPE=T;
		NORMAL MODE DEINTERLACING
	T_N_N_4	MSC = MSC + 1; PFPE =
		F; NORMAL MODE DEINTERLACING
	T_N_C_2	MSC = 0; PFPE = F;
		MERGE FIELD i − PF and FIELD
		i − (PF − 1)
	T_N_N_5	MSC = 0; NORMAL MODE
		DEINTERLACING
	T_N_N_6	MSC = 0; PFPE = F;
		NORMAL MODE DEINTERLACING

[0083]

TABLE 2(a)
(PFPE = F)
(P_D or SI_D)	V_D	MSC	Transition Path
T	X	X	T_C_C_1
F	T	<(T_NMT − 1)	T_C_C_2
F	T	=(T_NMT − 1)	T_C_N_1
F	F	<(T_NMT − 1)	T_C_C_3
F	F	=(T_NMT − 1)	T_C_N_2

[0084]

TABLE 2(b)
(PFPE = F)
	Transition Path	Actions Taken
	T_C_C_1	MSC = 0; PFPE = T;
		MERGE FIELD i − PF and
		FIELD i − (PF + 1)
	T_C_C_2	MSC = MSC + 1; NORMAL
		MODE DEINTERLACING
	T_C_N_1	MSC = 0; NORMAL MODE
		DEINTERLACING
	T_C_C_3	MSC = MSC + 1; PFPE =
		T; NORMAL MODE DEINTERLACING
	T_C_N_2	MSC = 0; PFPE = T;
		NORMAL MODE DEINTERLACING

[0085]

TABLE 3(a)
(PFPE = T)
(V_D or SI_D)	P_D	MSC	Transition Path
T	X	X	T_C_C_4
F	T	<(T_NMT − 1)	T_C_C_5
F	T	=(T_NMT − 1)	T_C_N_3
F	F	<(T_NMT − 1)	T_C_C_6
F	F	=(T_NMT − 1)	T_C_N_4

[0086]

TABLE 3(b)
(PFPE = T)
	Transition Path	Actions Taken
	T_C_C_4	MSC = 0; PFPE = F;
		MERGE FIELD i − PF and
		FIELD i − (PF − 1)
	T_C_C_5	MSC = MSC + 1; NORMAL
		MODE DEINTERLACING
	T_C_N_3	MSC = 0; NORMAL MODE
		DEINTERLACING
	T_C_C_6	MSC = MSC + 1; PFPE =
		F; NORMAL MODE DEINTERLACING
	T_C_N_4	MSC = 0; PFPE = F;
		NORMAL MODE DEINTERLACING

[0087] As stated above, the embodiment of FIGS. 8 and 9 assumes processing field parameter PF is equal to an even number. For embodiments of the present invention in which processing field parameter PF is an odd number, the embodiment of FIGS. 8 and 9 should be modified by inverting the value of processing field peak expected signal PFPE.

[0088] APPENDIX I provides another embodiment of a deinterlacing system in accordance with the present invention implemented in pseudocode. One skilled in the art can easily convert the pseudocode to a hardware definition language such as VHDL or Verilog to create a deinterlacing system in accordance with the present invention. In the embodiment of Appendix I MDP FIFO size MFS is equal to 5.

[0089] In the various embodiments of the present invention, novel structures have been described for deinterlacing systems. By using mode detection parameters a novel method for detecting converted mode video streams is achieved. The various embodiments of the structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, in view of this disclosure those skilled in the art can define other peak valley patterns, converted mode deinterlacing techniques, normal mode deinterlacing techniques, buffers, mode detectors, mode detection parameter calculation units, mode analysis units, peak valley pattern checkers, peak detectors, valley detectors, still image detectors, mode analysis controllers, field merging and conversion units, threshold levels, and so forth, and use these alternative features to create a method, circuit, or system according to the principles of this invention. Thus, the invention is limited only by the following claims.

[0090]

Initialization:
	PFPE	= TRUE
	MSC	= 0
	C_MODE = TRUE “converted mode”
IF PFPE=TRUE
	{
	IF C_MODE=TRUE
	{
	IF MIN(MDP(i−2),MDP(i−4))*T_VP > MAX(MDP(i−1),MDP(i−3),MDP(i−5)
	OR MAX(MDP(i−1),MDP(i−2),MDP(i−3),MDP(i−4),MDP(i−5))<T_SFP
	{
	PFPE=FALSE
	MSC=0
	MARK FIELD i−2 TO MERGE WITH FIELD i−1
	GO TO NEXT FIELD
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	IF MIN(MDP(i−1),MDP(i−3),MDP(i−5))*T_VP
	>MAX(MDP(i−2),MDP(i−4))
	{
	PFPE=TRUE
	}
	ELSE
	{
	PFPE=FALSE
	}
	MSC = MSC+1
	IF MSC=T_NMT
	{
	MSC=0
	C_MODE=FALSE
	GO TO NEXT FIELD
	}
	}
	ELSE
	{
	IF MIN(MDP(i−2),MDP(i−4))*T_VP
	> MAX(MDP(i−1),MDP(i−3),MDP(i−5))
	{
	PFPE=FALSE
	MSC = MSC+1
	IF MSC=T_CMT
	{
	MSC=0
	C_MODE=TRUE
	MARK FIELD i−2 TO MERGE WITH FIELD i−1
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	}
	GO TO NEXT FIELD
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	MSC=0
	IF MIN(MDP(i−1),MDP(i−3),MDP(i−5))*T_VP
	>MAX(MDP(i−2),MDP(i−4))
	{
	PFPE=TRUE
	}
	ELSE
	{
	PFPE=FALSE
	}
	GO TO NEXT FIELD
	}
	}
	}
ELSE
	{
	IF C_MODE = TRUE
	{
	IF MIN(MDP(i−1),MDP(i−3),MDP(i−5))*T_VP>MAX(MDP(i−2),MDP(i−4))
	OR MAX(MDP(i−1),MDP(i−2),MDP(i−3),MDP(i−4),MDP(i−5))<T_SFP
	{
	PFPE=TRUE
	MSC=0
	MARK FIELD i−2 TO MERGE WITH FIELD i−3
	GO TO NEXT FIELD
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	IF MIN(MDP(i−2),MDP(i−4))*T_VP
	> MAX(MDP(i−1),MDP(i−3),MDP(i−5))
	{
	PFPE=FALSE
	}
	ELSE
	{
	PFPE=TRUE
	}
	MSC = MSC+1
	IF MSC=T_NMT
	{
	MSC=0
	C_MODE=FALSE
	}
	GO TO NEXT FIELD
	}
	ELSE
	{
	IF MIN(MDP(i−1),MDP(i−3),MDP(i−5))*T_VP>MAX(MDP(i−2),MDP(i−4))
	{
	PFPE=TRUE
	MSC = MSC +1
	IF MSC =T_CMT
	{
	MSC =0
	C_MODE=TRUE
	MARK FIELD i−2 TO MERGE WITH FIELD i−3
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	}
	GO TO NEXT FIELD
	}
	ELSE
	{
	MARK FIELD i−2 TO DO NORMAL MODE DEINTERLACING
	MSC =0
	IF MIN(MDP(i−2),MDP(i−4))*T_VP
	> MAX(MDP(i−1),MDP(i−3),MDP(i−5))
	{
	PFPE=FALSE
	}
	ELSE
	{
	PFPE=TRUE
	}
	GO TO NEXT FIELD
	}
	}