Method for making a semiconductor device having a high-k gate dielectric

[0001] The present invention relates to methods for making semiconductor devices, in particular, those that include high-k gate dielectric layers.

[0002] MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. When forming such a dielectric on a hydrophobic surface, it may be necessary to form a buffer layer (e.g., a thin layer of silicon dioxide or silicon oxynitride) on that surface prior to forming the dielectric on the buffer layer. The presence of a buffer layer between the substrate and the high-k dielectric may contribute to the overall electrical thickness of the gate/gate dielectric stack. As device gate lengths shrink (e.g., to lengths that are significantly less than 45 nm), it may be desirable to decrease that electrical thickness—which may be done by eliminating such a buffer layer.

[0003] Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric. There is a need for a process for forming such a device that does not include forming the high-k gate dielectric on a buffer layer that is formed on an underlying substrate. The method of the present invention provides such a process.

[0006] A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.

[0007] FIGS. 1a-1e represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention. FIG. 1a represents substrate 100, which includes hydrophobic surface 101. Substrate 100 may comprise any material that may serve as a foundation upon which a semiconductor device may be built. Substrate 100 may, for example, comprise silicon and/or germanium.

[0008] When substrate 100 comprises a silicon wafer, hydrophobic surface 101 may be formed on silicon containing substrate 100 by exposing silicon containing substrate 100 to a reducing agent, e.g., a reducing agent that comprises hydrogen. In a preferred embodiment, silicon containing substrate 100 is exposed to a 1% hydrofluoric acid solution for about 60 seconds to generate hydrophobic surface 101. It is believed that exposing silicon containing substrate 100 to such a solution will etch away any native oxide and subsequently cause hydrogen atoms to bond to its surface (as FIG. 1a indicates), yielding a surface that is hydrophobic.

[0009] After forming hydrophobic surface 101 on silicon containing substrate 100, hydrophobic surface 101 is converted into a hydrophilic surface. In the illustrated embodiment, hydrophobic surface 101 is first converted into intermediate surface 102 (as FIG. 1b illustrates), which is then converted into hydrophilic surface 103 (as FIG. 1c illustrates). Hydrophobic surface 101 may, for example, be converted into intermediate surface 102 by exposing hydrophobic surface 101 to a halogen containing gas or a halide containing solution, e.g., chlorine or bromine gas, hydrobromic or hydrochloric acid, or a plasma derived at least in part from bromine or chlorine.

[0010] When hydrophobic surface 101 is exposed to chlorine, that surface may be exposed to a 2% solution of hydrochloric acid in deionized water. Alternatively, hydrophobic surface 101 may be treated with chlorine gas while being exposed to ultraviolet light. Appropriate conditions for converting hydrophobic surface 101 into intermediate surface 102 using these materials will be apparent to those skilled in the art. It is believed that exposing hydrophobic surface 101 to such a chlorine based solution or gas will cause chlorine atoms to replace hydrogen atoms that are located on the surface of substrate 100, yielding an intermediate surface that may react with steam, e.g., the chlorine covered surface that FIG. 1b represents.

[0011] In this embodiment, after forming intermediate surface 102, that surface is converted into hydrophilic surface 103 by exposing it to steam. In a preferred embodiment, the structure that FIG. 1c illustrates may be generated by exposing intermediate surface 102 to gas phase water at about 350° C. It is believed that exposing intermediate surface 102 to steam at that temperature will cause hydroxyl groups to replace chlorine atoms that are located on the surface of substrate 100, yielding the monohydroxylated surface shown in FIG. 1c.

[0012] It is further believed that the presence of chlorine atoms on intermediate surface 102 inhibits consumption (e.g., oxidation) of underlying substrate 100, which may otherwise occur when a surface like hydrophobic surface 101 is converted directly to hydrophilic surface 103 without forming intermediate surface 102, e.g., by treating hydrophobic surface 101 with an aqueous solution that contains hydrogen peroxide. Furthermore, hydrophobic surface 101 will not sufficiently convert to the desired hydrophilic surface 103 if merely exposed to steam. In a typical process, exposing hydrophobic surface 101 to a hydrogen peroxide solution may generate a buffer layer that is between about 3 and about 6 angstroms thick. Although a few examples of processes for converting hydrophobic surface 101 into hydrophilic surface 103 are described here, other processes for performing that conversion may be used instead, as will be apparent to those skilled in the art.

[0013] After generating bufferless surface 103, high-k gate dielectric layer 110 may be formed on that hydrophilic surface, generating the FIG. 1d structure. High-k gate dielectric layer 110 may comprise, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, and aluminum oxide. Although a few examples of materials that may be used to form dielectric layer 110 are described here, that layer may be made from other materials that serve to reduce gate leakage.

[0014] High-k gate dielectric layer 110 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and dielectric layer 110. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer 110 should be less than about 60 angstroms thick, and more preferably between about 5 angstroms and about 40 angstroms thick.

[0015] After high-k gate dielectric layer 110 is deposited, it may be desirable to remove impurities from high-k gate dielectric layer 110 and to increase that layer's oxygen content. After removing impurities and increasing the oxygen content, metal gate electrodes 115 and 120 may be formed on the resulting high-k gate dielectric layer 110, to generate the structure of FIG. 1e. Various techniques for generating that structure will be apparent to those skilled in the art.

[0016] Metal gate electrodes 115 and 120 may comprise any conductive material from which metal gate electrodes may be derived. Metal gate electrode 115 may comprise an NMOS metal gate electrode, while metal gate electrode 120 comprises a PMOS metal gate electrode. Alternatively, metal gate electrode 115 may comprise a PMOS metal gate electrode, while metal gate electrode 120 comprises an NMOS metal gate electrode. Materials that may be used to form n-type metal gate electrodes include: hafnium, zirconium, titanium, tantalum, aluminum, their alloys (e.g., metal carbides that include these elements, i.e., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and aluminides (e.g., an aluminide that comprises hafnium, zirconium, titanium, tantalum, or tungsten). Materials for forming p-type metal gate electrodes include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.

[0017] Metal NMOS gate electrodes preferably have a workfunction that is between about 3.9 eV and about 4.2 eV. Metal PMOS gate electrodes preferably have a workfunction that is between about 4.9 eV and about 5.2 eV. Although FIG. 1e represents structures in which the metal gate electrodes consist essentially of a homogeneous metal layer, in alternative embodiments, the n-type or p-type metal layers may generate only the lower part of the metal gate electrodes, with the remainder of the metal gate electrodes comprising another metal or metals, e.g., a metal that may be easily polished like tungsten, aluminum, titanium, or titanium nitride. Although a few examples of materials for forming metal gate electrodes 115 and 120 are identified here, those metal gate electrodes may be made from many other materials, as will be apparent to those skilled in the art. Moreover, although gate electrodes 115 and 120 preferably are metal gate electrodes, they may alternatively comprise polysilicon or a silicide.

[0018] The method of the present invention may enable a high-k gate dielectric layer to be formed directly on a hydrophilic surface of a substrate (e.g., a silicon containing substrate) without a buffer layer being present between the high-k gate dielectric layer and the hydrophilic surface. By enabling such a high-k gate dielectric layer to be formed on such a bufferless surface, it may be possible to substantially reduce the electrical thickness of a gate/gate dielectric stack that includes such a dielectric layer, which may facilitate high volume manufacture of devices with gate lengths of about 30 nm or less.

[0019] Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, all such modifications, substitutions and additions fall within the spirit and scope of the invention as defined by the appended claims.