US 7,383,522 B2Grant
Crosstalk-aware timing analysis
Issue Date:2008-06-03
•40 Claims
•3 Drawing Sheets
Abstract
In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Rajeev Murgai
- Yinghua Li
- Takashi Miyoshi
Application Information
Application Number:US 11/178,111
Filing Date:2005-07-08
Priority Date:2004-10-08
Art Unit:2825
Classifications
IPC:
G06F17/50G06F9/45
Patent Drawings (3 sheets)
Description
Related Application
[0001] This application claims the benefit, under 35 U.S.C. § 119(e), of U.S. Provisional Application No. 60/617,283, filed Oct. 8, 2004.
Technical Field of the Invention
[0002] This invention relates generally to circuit design and more particularly to crosstalk-aware timing analysis.
Background
[0003] In deep sub-micron circuit designs, as wires have become taller and narrower while distances separating them from each other has decreased, coupling capacitance between adjacent interconnects has become a significant problem.
Summary
[0004] According to the present invention, disadvantages and problems associated with circuit design may be reduced or eliminated.
[0005] In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying one or more critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method also includes identifying one or more potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect. The method also includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, computing a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.
[0006] Particular embodiments of the present invention may provide one or more technical advantages. As an example, particular embodiments include an analysis tool for measuring the impact of crosstalk on delays of critical paths in a design. In particular embodiments, the crosstalk-aware delay information is useable by designers to modify the design to reduce or even prevent crosstalk. Compared with other approaches, particular embodiments of the present invention provide high delay-computation accuracy. Particular embodiments avoid use of approximate models for cells and nets and interconnect reductions. Particular embodiments employ a path-based approach, use detailed and accurate distributed RC parasitics for critical nets and their aggressors, use BSIM3-accurate gate models, and invoke accurate analysis tools, such as, for example, HSPICE, for delay computation using only the minimum complete set of input patterns.
[0007] Particular embodiments may provide all, some, or none of the technical advantages described above. Particular embodiments may provide one or more other technical advantages, one or more of which may be apparent, from the figures, descriptions, and claims herein, to a person having ordinary skill in the art
Brief Description of the Drawings
[0008] To provide a more complete understanding of the present invention and the features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:
[0009] FIG. 1 illustrates example crosstalk;
[0010] FIG. 2 illustrates an example crosstalk-aware timing analysis;
[0011] FIG. 3 illustrates an example path; and
[0012] FIG. 4 illustrates an example method for crosstalk-aware timing analysis.
Description of Example Embodiments
[0013] FIG. 1 illustrates example crosstalk. In deep sub-micron circuit designs, as wires have become taller and narrower while distances separating them from each other has decreased, coupling capacitance between adjacent interconnects has become a significant problem. As a result, crosstalk noise between physically adjacent nets (or interconnects) has become a significant problem. An affected net is a victim, v. A neighboring switching net causing noise affecting the victim v is an aggressor, a. Reference to an aggressor a encompasses one or more such nets, where appropriate. As FIG. 1 illustrates, when the aggressor a switches in a direction opposite the victim v, crosstalk may increase an arrival time at the victim v. When the aggressor a switches in the same direction as the victim v, crosstalk may decrease an arrival time at the victim v. Distributed coupling capacitance between v and a is shown as Cci. Crosstalk may also result in logic hazards and circuit malfunction. For instance, if the delay change is large enough to render a critical path slower than the clock cycle (and thus cause a timing violation) or the large spike generated on the victim v due to capacitive coupling with an aggressor a is close enough to the clock edge to latch a wrong value at the target flip-flop, the circuit may malfunction. Accurate computation of the delay change due to crosstalk becomes important in the circuit design process. Particular embodiments of the present invention address this problem in the context of chip-level design and compute accurate path delays in the presence of crosstalk coupling.
[0014] Particular embodiments of the present invention provide an accurate analysis methodology and a tool for measuring the effects of crosstalk on path and circuit delay. In particular embodiments of the present invention, the tool is a hardware, software, or embedded logic component or a combination of two or more such components. In such embodiments, one or more computer systems provide user access to the tool. Particular embodiments of the present invention are path-based and do not suffer from the pessimism inherent in net-based analysis in previous approaches. For each path p under analysis, for a given victim net, the true aggressors and their switching times are computed based on the switching time of the victim net with respect to p. For a given path p, the delays through gates and nets in the path in the presence of crosstalk are computed very accurately using HSPICE. Particular embodiments of the present invention model nets as distributed RC networks. Macromodel reduction techniques need not be applied. Because crosstalk has a significant impact on gate delays, as well as net delays, accurate gate-delay model are important. Particular embodiments of the present invention use BSIM3 gate models, in contrast to the simple resistive models used in previous approaches. To compute gate delays, static timing analysis (STA) tools typically replace the interconnect parasitics at the output net by a single effective capacitance Ceff. Computation of Ceff is approximate and an attempt to fit the output-load based cell delay model used in STA tools. In contrast, particular embodiments of the present invention use HSPICE and the complete RC network at the output net to compute the pin-to-pin delay through the gate, which provides substantial accuracy. For cell delay recomputation, particular embodiments of the present invention provide a method that generates a minimum number of patterns that should be simulated to derive a worst case pin-to-pin delay through a cell on a critical path for a given input-output pin pair and transition directions. Particular embodiments of the present invention generate SPICE-accurate delay reports for the critical paths for two scenarios: one in the presence of switching aggressors and coupling capacitances, and another in their absence. This allows designers to more readily see the impact of crosstalk.
[0015] Generally speaking, particular embodiments of the invention assume that a mapped, placed, and routed design is available, then recompute the delay of a set of critical paths in the presence of neighboring aggressor nets. Such embodiments first identify potential aggressor nets for each net v of a critical path p, then extract parasitics for v in the presence of the aggressors. The parasitics include distributed coupling capacitances, self capacitances, and resistances. Such embodiments then recompute p's delay by traversing p from the start point, recomputing the delay and slew through each cell on p and the associated output net v in the presence of the coupling capacitances and aggressor transitions.
[0016] Particular embodiments of the present invention involve the following input and output. Particular embodiments read a mapped and post-routed design, including a gate-level hierarchical netlist and placement and routing data. A designer may also provide an optional list P of paths that the designer wants to analyze for delay in the presence of capacitive coupling. If the designer provides such a list, the list should have actual arrival times and transition times for all points (or pads or pins) on each path of P. If the designer does not provide the path list P (which in particular embodiments is the default mode), particular embodiments will automatically generate an intermediate timing report Rpt that contains the list P of critical and near-critical paths in the design. Particular embodiments also require a cell library and SPICE model files.
[0017] Particular embodiments of the present invention may invoke computer-assisted design (CAD) vendor tools for the following tasks: PrimeTime for STA, StarXtract for parasitic extraction, and HSPICE for circuit analysis and delay computation. These tools come from SYNOPSYS. Although particular tools are described for particular tasks, the present invention contemplates any suitable tools for any suitable tasks. The output of particular embodiments of the present invention are two timing reports, Rct and Rsp. The timing report Rct contains timing information for each path p in P in the presence of crosstalk. Particular embodiments report actual arrival times and slews at all points and delays through cells and nets on p. The second report Rsp contains the same timing information, but in the absence of crosstalk from switching aggressors. A difference between Rsp and the timing report Rpt generated by PrimeTime is that Rsp is generated using HSPICE. Since PrimeTime is usually pessimistic in comparison with HSPICE, e.g., PrimeTime reports higher delay numbers than HSPICE does, comparing Rct with Rsp is preferable: both are generated using HSPICE and are more accurate than PrimeTime.
[0018] FIG. 2 illustrates an example crosstalk-aware timing analysis. In particular embodiments of the present invention, critical path generation 10 generates a set of critical paths P, if not already provided. All nets on P along with their directions, i.e., rise or fall, and arrival times constitute the set V of victim nets. For at least some designs, critical path generation 10 uses a PrimeTime script to generate this set. This script also reads in the net parasitics to model the interconnect. Let tPT be the path delay computed by PrimeTime. Any suitable static timing analysis may be used in place of PrimeTime. In particular embodiments of the present invention, aggressor net generation 12 computes, for each net n in V, the set of potential aggressor nets, A(n). These are the nets that are physically close to n. Given n, aggressor net generation 12 computes A(n) as follows. First, from the layout, all the net segments NS(n) of n and their end point coordinates are determined. Next, those segments in the entire design that are within some user-defined maximum distance (in terms of grids) from some segment in NS(n) are extracted. The owning nets of these segments determine the set of possible aggressor nets A(n) for n. In particular embodiments of the present invention, a user specifies the minimum length for which a net segment must run in parallel with a segment in NS(n) to qualify as an aggressor. Let n∪A(n)=S(n), also called the victim-aggressor set.
[0019] In particular embodiments of the present invention, parasitics extraction 14 generates, for each nεV, the parasitics for the victim-aggressor set S(n). The parasitics form an RC network, which includes distributed net resistances, capacitances to ground, and coupling capacitances between the nets in S(n). FIG. 1 illustrates an example of such a network the victim v and a single aggressor a. In particular embodiments of the present invention, timing window generation 16 computes a timing window for each net m in ∪nεVS(n). To reduce pessimism and false timing violations, the timing window preferably lists delays of all subpaths that pass through m, i.e., delays from their respective start points up to m, explicitly. However, a tool that generates such information is unavailable. In particular embodiments of the present invention, timing window generation 16 instead uses PrimeTime, which only computes the shortest and the longest paths. As a result, the timing window consists of min/max and rise/fall arrival times and transition times. These timing windows are used to generate aggressor nets' waveforms, which are used in subsequent SPICE simulations. In particular embodiments of the present invention, path delay recomputation 18 recomputes the delay of each critical path pεP, taking into account coupling and aggressor information. FIG. 3 illustrates an example path p. Path p is an alternation of cells and nets, along with the transition direction (rise or fall) at each point. Path delay recomputation 18 traverses path p from the start point and recomputes delay of each cell ci from the input pin I(ci) to the output pin O(ci) and delay of net ni rooted at O(ci). Path delay recomputation 18 then updates the arrival time and transition time at the sink I(ci+1) of ni, which are later used to compute the delay of the stage i+1. This process continues until the new arrival time at the end-point of p is known.
[0020] The delays of the cell ci and net ni are computed in the presence of the entire parasitic RC network (including coupling capacitances in the nets S(ni)) and transitions on the aggressor nets A(ni). To compute the maximum impact of the aggressor αεA(ni) on the victim delay, α should make a transition in a direction opposite to that of the victim ni, if the timing window of a contains the actual arrival time of ni; on the path p. The arrival time of α is identical to that of ni, and its transition time or slew is the minimum slew in the appropriate direction. This timing information is obtained from STA. Note that, in general, the minimum slew on the aggressor will result in the maximum delay increase. When the aggressor α's timing window does not contain the arrival time of ni, α is kept static at VDD (if ni is falling) or GND (if ni is rising). The arrival time, transition time, and direction (rising, falling, or constant VDD/GND) together constitute the aggressor waveform.
[0021] The parasitics extracted for ni and A(ni) nets are combined with the aggressor waveforms into a SPICE deck. The only missing information in the deck is the values on the side inputs of the cell ci. The side inputs of ci are all inputs of ci except I(ci). Note that the waveform on I(ci) is already known: it is based on the new arrival time and the transition time computed from the previous stage i−1. To measure the worst delay through ci, all possible values should be specified at the side inputs of ci. In particular embodiments of the present invention, the delay is measured with HSPICE for each case, and the maximum of all these delay values yields the worst pin-to-pin delay through ci. This is the naïve approach for delay computation. Utilizing the information about sensitivity and input/output transitions at ci speeds up the delay characterization process significantly. For instance, if ci is a three-input AND gate, with critical input I(ci)=x1 rising and the output O(ci) also rising as a result, the naive approach requires four SPICE simulations, corresponding to the four vectors 00, 01, 10, and 11 at x2 and x3. However, the input transition at x1 can propagate to the output only if the side inputs x2 and x3 are both 1. So, only one input vector needs to be applied and simulated. This is the preferred approach. In general, assume that the output O(ci) of the cell ci implements logic function f(x1, x2, . . . , xm), where I(ci)=x1 is on the critical path. Without loss of generality, assume x1 makes a rising transition and f makes a falling transition. Particular embodiments of the present invention compute the minimum set of patterns that should be simulated to compute the worst case delay from x1 to the output f of the cell ci for the given pair of transitions on x1 and f. Before x1 rises, x1=0 and f=1. This corresponds to the condition g(x2,x3, . . . xm)=fx′1 , where fx′1 is the cofactor off with respect to x1=0 and represents exactly those input combinations at x2 through xm for which f=1 when x1 is set to 0. After x1 rises, f falls. The other inputs off do not change. The fluid state is x1=1 and f=0. This corresponds to the condition h(x2,x3, . . . ,xm)=f′x1 , where f′x1 represents exactly those input combinations for which and f=0 when x1 is set to 1. Since the only input that has changed is x1, the function gh(x2,x3, . . . xm)=fx′1 f′x1 represents exactly all the combinations at x2 through xm that are possible both before and after x1 and f make transitions in the specified directions. fx′1 f′x1 also represents the set of combinations for the case when x1 falls and f rises. When both x1 and f rise (or fall), the desired function is fx1 f′x′1 .
[0022] As an example and not by way of limitation, consider the above three-input AND gate example, where x1 rises and f rises as a result. f(x1,x2,x3)=x1x2x3. f′(x1, x2, x3)=x′1+x′2+x′3 From the desired function fx1 f′x′1 , the function fx1 f′x′1 =(x2x3)(1)=x2x3 yields all the x2 and x3 combinations under which rising x1 can result in rising f. This implies x2=x3=1.
[0023] In particular embodiments of the present invention, a library pattern generator 20 applies the above analysis to each input-output pin pair (and their transition directions) of all library cells, computes the above functions, and generates the minimum set of patterns that need to be simulated. Library pattern generator 20 may, but need not, be a Sequential Interactive Synthesis (SIS)-based library preprocessor. Particular embodiments of the present invention incorporate these patterns and compute the worst delay through ci from the input pin I(ci) to the output pin O(ci). Such embodiments compute arrival time at O(ci) from the arrival time at I(ci) and the cell delay. Corresponding to this worst case, such embodiments also use HSPICE to measure the new net delay from O(ci) to I(ci+1) (which in turn determines the new arrival time at I(ci+1)) and the transition time at I(ci+1). This completes the delay recomputation through the cell ci and net ni. Repeating this for all the stages of p computes p's new delay, tCT, which may be referred to as the crosstalk-aware delay.
[0024] Since PrimeTime and HSPICE can yield different delay values, for an accurate computation of delay change due to crosstalk, particular embodiments of the present invention recompute the path delay of p by repeating the above delay computation process, but without using any aggressor switchings. In other words, all aggressors are assumed to be either at VDD or GND, which effectively replaces the coupling capacitances in S(ni) with capacitances to ground. The path delay thus obtained is called the SPICE delay (tSP).
[0025] As an example and not by way of limitation, particular embodiments of the present invention may be applied to two industrial designs: D1 and D2. Both use 0.11-μ technology and have a VDD of 1.2V. Table 1 shows the numbers of cells and nets in these two designs. The designs are analyzed after they have been successfully placed and detail-routed. The layout parasitics are also extracted and used in the STA tool PrimeTime Version 2002.03-SP1.
[0026]
| TABLE 1 | ||
|---|---|---|
| Benchmark Statistics | ||
| Design | # Cells | # Nets |
| D1 | 165K | 167K |
| D2 | 454K | 460K |
| 1K = 1000 | ||
| Both benchmarks correspond to 0.11μ, technology. | ||
[0027] First, the results on D1 are reported. Initially, PrimeTime reports 65 critical or near-critical paths in D1. Out of these, only 36 are unique: 29 are found to be duplicates and removed. This utility reduced run-time by a factor of almost two, since the run-time is roughly linear in the number of paths analyzed. The total number of critical or victim nets on these 36 paths is 130. The total number of aggressor nets is 309. On average, there are about 2.4 aggressor nets per victim net. It turns out that 68 victim nets have no neighboring aggressor nets. Particular embodiments of the present invention are applied to each of the 36 paths to compute tSP (HSPICE delay without crosstalk) and tCT (HSPICE delay in the presence of crosstalk). It turns out that only 11 of these paths have a delay change of more than 10 picoseconds, i.e., Δt=tCT−tSP-≧10 picoseconds. Table 2 provides delay information for each of the 11 paths. Paths 7 and 10 have maximum Δt: more than 350 picoseconds. This prompts further investigation, which discovers that, on path 7, there is a net nil that has four aggressors. ni1 had an overlap length of 950μ with two of them and 180-255μ with the other two. On path 10, there are two nets with significant overlaps: 400-650μ. These paths, their tSP and tCT delays, and the overlap lengths with aggressors are reported to the designers, who verify that coupling causes these paths to become longer and moves the relevant victim and aggressor nets away from each other to reduce the delay increase.
[0028]
| TABLE 2 | ||||||
|---|---|---|---|---|---|---|
| Critical path delays by PrimeTime, HSPICE, | ||||||
| and crosstalk-aware analysis for D1 | ||||||
| Path | tPT | tSP | tCT | Δt = tCT − tSP | Δg | Δg Δt ( % ) |
| 1 | 3754.5 | 3641.83 | 3682.85 | 41.02 | 34.29 | 83.6 |
| 2 | 3769.3 | 3663.32 | 3703.21 | 39.89 | 33.22 | 83.3 |
| 3 | 3769.1 | 3663.13 | 3703.02 | 39.89 | 33.22 | 83.3 |
| 4 | 3768.73 | 3668.61 | 3707.47 | 38.86 | 32.19 | 82.8 |
| 5 | 3767.42 | 3661.60 | 3701.49 | 39.89 | 33.22 | 83.3 |
| 6 | 1672.37 | 1641.73 | 1657.86 | 16.13 | 9.54 | 59.2 |
| 7 | 4057.18 | 4027.49 | 4379.20 | 351.71 | 350.35 | 99.6 |
| 8 | 1653.58 | 1626.83 | 1637.37 | 10.54 | 10.54 | 100.0 |
| 9 | 1404.57 | 1335.93 | 1354.03 | 18.10 | 14.97 | 82.7 |
| 10 | 4089.96 | 4015.67 | 4384.56 | 368.89 | 347.88 | 94.3 |
| 11 | 1348.9 | 1294.35 | 1332.07 | 37.72 | 37.72 | 100.0 |
| All delays are in pHs. | ||||||
[0029] For the second design, D2, PrimeTime reports sixty unique critical paths. In all, there are 450 victim nets on these paths. They have a total of 247 aggressor nets. It turns out that 336 critical nets do not have any aggressors. Particular embodiments of the present invention find four paths having delay increases of more than 10 picoseconds. These paths are listed in Table 3. The main reason why D2 experiences less impact from crosstalk than does D1 is that the average number of aggressors per victim net was 0.55 in D2 and 2.4 in D1. This is because D2 had already been optimized by the designers for crosstalk prevention. This version of the design is obtained after increasing the spacing between the net segments that have significant coupling. Any overlap of smaller than 20μ between two net segments tends not to result in significant coupling capacitance.
[0030]
| TABLE 3 | ||||
|---|---|---|---|---|
| Critical path delays by PrimeTime, HSPICE, | ||||
| and crosstalk-aware analysis for D2 | ||||
| Path | tPT | tSP | tCT | Δt = tCT − tSP |
| 1 | 1878.27 | 1821.26 | 1833.89 | 12.63 |
| 2 | 1791.09 | 1758.72 | 1776.79 | 18.07 |
| 3 | 1947.89 | 1893.51 | 1911.73 | 18.22 |
| 4 | 1834.71 | 1798.49 | 1816.67 | 18.18 |
| All delays are in ps. | ||||
[0031] As an example and not by way of limitation, consider an experiment on the impact of crosstalk on gate delays and the relative contribution of gate delay changes to the path delay degradation Δt. For the chip D1, for each path reported in Table 2, the sum of the gate delay changes due to crosstalk is computed. This is listed under the column Δg in Table 2. The percentage fraction is shown in the column
[0032]
For instance, for Path 1, the crosstalk resulted in a delay increase of 41.02 picoseconds, out of which 34.29 picoseconds were contributed by the gate delay increase. Only a 6.73 picosecond increase was due to interconnect. For almost all paths, the contribution of gate delay change to Δt is over 83%, which points to a significant impact of crosstalk on gate delays. Therefore, it is important to accurately model and compute not only interconnect delays, but also gate delays.
For instance, for Path 1, the crosstalk resulted in a delay increase of 41.02 picoseconds, out of which 34.29 picoseconds were contributed by the gate delay increase. Only a 6.73 picosecond increase was due to interconnect. For almost all paths, the contribution of gate delay change to Δt is over 83%, which points to a significant impact of crosstalk on gate delays. Therefore, it is important to accurately model and compute not only interconnect delays, but also gate delays.
[0033] Regarding the accuracy of particular embodiments of the present invention, note from Table 2 that the PrimeTime delay tPT for a path p is different from tSP on average by 72.5 picoseconds. For all these paths, the PrimeTime delay values are greater. This significant difference, is possibly due to three factors: (1) PrimeTime reducing the interconnect at an output pin to a single Ceff to compute the cell delay; (2) PrimeTime using a look-up-table based scheme to compute the cell delay; and (3) PrimeTime not computing the delay through interconnect as accurately as HSPICE. There are several cases where the interconnect delays computed by PrimeTime differ by more than 10% from those computed by HSPICE. Usually the PrimeTime-computed interconnect delays are smaller, which justifies the use of HSPICE in particular embodiments of the present invention.
[0034] The following data highlights the inaccuracy of net-based analysis next to path-based analysis for crosstalk. In net-based analysis, the maximum arrival time of a net is used to derive aggressors' waveforms. In design D1, there is a critical net n with a maximum arrival time of tm=4694 picoseconds. The net-based analysis results in aggressors switching at tm. In this case, only one aggressor's timing window contains tm. However, n is on two critical paths, and on one of these paths-Path 7 in Table 2—the arrival time of n was t=3520 picoseconds. Path 7 is not analyzed correctly using net-based analysis, since the aggressor switching time is forced to tm, which is substantially different from the correct value t. The net-based analysis computed that the delay of Path 7 changed by less than 15 picoseconds over tsp. However, in the path-based analysis of particular embodiments of the present invention, the switching times of aggressors are set at t instead of tm. The net n has two aggressors with timing windows containing t. By setting the switching times of these two aggressors to t and carrying out the analysis, the delay of path 7 increases by more than 350 picoseconds over tSP, as shown in Table 2. Path 10 provides a similar case. This example illustrates the inaccuracy inherent in the net-based crosstalk delay analysis (in terms of the aggressors that should switch and their switching times to model the worst-case scenario and its inability to distinguish different signal arrival times at a single net) and strengthens the case for a path-based analysis.
[0035] As an example and not by way of limitation, consider a comparison between the naive and smart approaches for cell delay characterization in the presence of crosstalk. As described above, the naive approach applies all possible input transitions to the side inputs of a cell, whereas the smart approach only applies the minimum set of vectors needed. On D1, using the smart technique, the total number of HSPICE simulations for 36 paths was reduced from 484 for the naive method to 327: a reduction of 32%. The total runtime for characterization went down from 173 minutes to 109 minutes, a speed-up of 1.59. This underscores the effectiveness of the smart approach for delay computation.
[0036] Particular embodiments of the present invention include an analysis tool for measuring the impact of crosstalk on delays of critical paths in a design. The crosstalk-aware delay information is useable by designers to modify the design to reduce or even prevent crosstalk. Compared with other approaches, particular embodiments of the present invention provide high delay-computation accuracy. Particular embodiments avoid use of approximate models for cells and nets and interconnect reductions. Particular embodiments employ a path-based approach, use detailed and accurate distributed RC parasitics for critical nets and their aggressors, use BSIM3-accurate gate models, and invoke HSPICE for delay computation using only the minimum complete set of input patterns.
[0037] As described above, application of particular embodiments of the present invention to two real designs indicated that the crosstalk impact was much greater on one design D1, since a significant number of critical net segments in the other design D2 had no neighboring nets, owing to previous crosstalk optimization. As further described above, crosstalk tends to severely impact gate delays, which underscores the significance of modeling gate delays accurately.
[0038] As described above, previous net-based crosstalk estimation work is typically pessimistic and does not meet stringent accuracy requirements. On the other hand, an exhaustive path-based approach, though accurate, is impractical due to exponential numbers of paths in the design. A hybrid two-step methodology is a viable way to solve this problem. The first step prunes the number of paths that will be passed to the second step. In the first step, either a pessimistic net-based crosstalk analysis may be used to report a superset of actual paths that may violate timing requirements, or, as in other embodiments of the present invention, simply the most critical or near-critical paths may be chosen. The second step then accurately analyzes for crosstalk effects each of the paths selected in the first step and determines the true violations, as described above.
[0039] Particular embodiments of the present invention make substantial use of the extraction tool StarXtract (which is invoked once for each victim net) and HSPICE for cell delay characterization. Although smart pattern generation speeds up delay characterization, delay computation and extraction tend to create bottlenecks in the flow. Particular embodiments of the present invention are useful for analyzing up to approximately 150 paths. Beyond that, run-time may become large, depending on the total number of nets on the selected paths. Particular embodiments of the present invention may make use of faster extraction and circuit simulation techniques. Another solution is parallel computing. Parallelization may be carried out at various levels. Different paths may be analyzed in parallel. In addition or as an alternative, extraction for each victim net and its associated aggressors may be done in parallel. Also, during delay recomputation, multiple HSPICE invocations for a single stage may be done in parallel.
[0040] Particular embodiments of the present invention assume that, to capture the maximum impact on the victim delay, if the timing window of the aggressor contains the victim arrival time, the aggressor arrival time may be made to coincide with the victim arrival time. However, this may at times be impossible, since the timing window computed by PrimeTime contains information only about the minimum and maximum arrival times at a gate. Storing more detailed timing information may help alleviate this problem.
[0041] In particular embodiments of the present invention, for HSPICE simulation, the aggressor arrival time is derived from that of the victim net (for the path under consideration) as reported by PrimeTime. This is because the true victim arrival time in the presence of aggressors is typically not known beforehand. Table 2 shows discrepancies between PrimeTime and HSPICE numbers. The following may fix this problem. If the victim arrival time as reported by PrimeTime is different from that computed by HSPICE in the presence of coupling, say by more than 5 picoseconds, the new arrival time may be used to generate the aggressor waveform, and the delay characterization may be repeated. This fix may be expensive if the convergence is slow, in which case a limit on the maximum number of iterations may be useful.
[0042] Particular embodiments of the present invention do not check if there exists a pair of input vectors that will cause aggressors to make transitions in a direction opposite to that of the victim at a certain time. Such embodiments assume that such a pair exists. Such a check can be done using automatic test pattern generation (ATPG) or satisfiability checking (SAT), but the signal arrival times, transition times and gate delays should be incorporated. Particular embodiments of the present invention ignore any change in the timing window of an aggressor due to coupling at its transitive fan in nets.
[0043] FIG. 4 illustrates an example method for crosstalk-aware timing analysis. The method begins at step 100, where a crosstalk-analysis tool accesses a design of a circuit. At step 102, the crosstalk-analysis tool identifies one or more critical paths in the design. At step 104, the crosstalk-analysis tool identifies one or more potential aggressor interconnects associated with each victim interconnect. At step 106, the crosstalk-analysis tool extracts, for each victim interconnect, one or more parasitics associated with the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect. At step 108, the crosstalk-analysis tool computes timing windows of the potential aggressor interconnects. At step 110, the cross-talk-analysis tool computes first timing of each cell and each victim interconnect on each critical path. At step 112, the cross-talk analysis tool generates timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on a first one of the critical paths, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the first critical path associated with the potential aggressor interconnects. At step 114, the cross-talk analysis tool traverses the first critical path from a start point on the first critical path to an end point on the first critical path. At step 116, using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the first critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the first critical path, the cross-talk analysis tool computes a second timing of each cell and each victim interconnect on the first critical path according to the traversal of the first critical path.
[0044] At step 118, the cross-talk analysis tool communicates the second timing of each cell and each victim interconnect on the first critical path for analysis. At step 120, if the cross-talk analysis tool has analyzed all critical paths identified at step 102, the method ends. At step 120, if the cross-talk analysis tool has not analyzed all critical paths identified at step 102, the method proceeds to step 122. At step 122, the cross-talk analysis tool generates timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on a next one of the critical paths, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the next critical path associated with the potential aggressor interconnects. At step 124, the cross-talk analysis tool traverses the next critical path from a start point on the next critical path to an end point on the next critical path. At step 126, using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the next critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the next critical path, the cross-talk analysis tool computes a second timing of each cell and each victim interconnect on the next critical path according to the traversal of the next critical path. At step 128, the cross-talk analysis tool communicates the second timing of each cell and each victim interconnect on the next critical path for analysis, and the method returns to step 120.
[0045] Although particular steps of the method illustrated in FIG. 4 have been illustrated and described as occurring in a particular order, the present invention contemplates any suitable steps of the method illustrated in FIG. 4 occurring in any suitable order. As an example and not by way of limitation, two or more suitable steps of the method illustrated in FIG. 4 may occur in parallel instead of serially.
[0046] Particular embodiments have been used to describe the present invention, and a person having skill in the art may comprehend one or more changes, substitutions, variations, alterations, or modifications to the particular embodiments used to describe the present invention. The present invention encompasses all such changes, substitutions, variations, alterations, and modifications within the scope of the appended claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A system for crosstalk-aware timing analysis, the system comprising:
a crosstalk analysis module operable to:
access a design of a circuit;
identify one or more critical paths in the design, each critical path comprising one or more victim interconnects and one or more cells;
identify one or more potential aggressor interconnects associated with each victim interconnect;
for each victim interconnect, extract one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect;
compute timing windows of the potential aggressor interconnects;
compute a first timing of each cell and each victim interconnect on each critical path; and
for each critical path:
generate one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects;
traverse the critical path from a start point on the critical path to an end point on the critical path; and
using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, compute a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.
2. The system of claim 1, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both take crosstalk into account.
3. The system of claim 1, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both do not take crosstalk into account.
4. The system of claim 1, wherein each timing window of each of the potential aggressor interconnects comprises minimum and maximum rise and fall arrival times and transition times.
5. The system of claim 1, wherein the first and second timings of each cell and each victim interconnect on the critical path comprise one or more of rise and fall arrival and transition times.
6. The system of claim 5, wherein the crosstalk analysis module is further operable to compute a rise or a fall arrival time of a cell or a victim interconnect on the critical path according to a sum of all delays through all cells and all victim interconnects on the critical path between the start point on the critical path and the cell or the victim interconnect on the critical path of which the crosstalk analysis module is computing the rise or the fall arrival time.
7. The system of claim 1, wherein the crosstalk analysis module is further operable to process each of two or more of the critical paths in parallel to generate the timing waveforms of the potential aggressor interconnects, traverse the critical path, and compute a second timing of each cell and each victim interconnect on the critical path.
8. The system of claim 1, wherein the crosstalk analysis module is further operable to extract parasitics of two or more victim interconnects in parallel.
9. The system of claim 1, wherein the crosstalk analysis module is further operable, to compute a second timing of a cell on a critical path, to run a plurality of simulations of the cell in parallel.
10. The system of claim 1, wherein the crosstalk analysis module is further operable to identify the critical paths in the design without taking crosstalk into account, without accurately modeling the design, or both.
11. The system of claim 1, wherein the crosstalk analysis module is further operable to identify the potential aggressor interconnects according to distances separating interconnects in the design from each other.
12. The system of claim 1, wherein the start point is an input pin on the critical path and the end point is an output pin on the critical path.
13. The system of claim 1, wherein one or more parasitics each comprise one or more of one or more distributed coupling capacitances, one or more self capacitances, and one or more resistances.
14. A method for crosstalk-aware timing analysis, the method comprising:
accessing a design of a circuit;
identifying one or more critical paths in the design, each critical path comprising one or more victim interconnects and one or more cells;
identifying one or more potential aggressor interconnects associated with each victim interconnect;
for each victim interconnect, extracting one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect;
computing timing windows of the potential aggressor interconnects;
computing a first timing of each cell and each victim interconnect on each critical path; and
for each critical path:
generating one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects;
traversing the critical path from a start point on the critical path to an end point on the critical path; and
using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, computing a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.
15. The method of claim 14, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both take crosstalk into account.
16. The method of claim 14, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both do not take crosstalk into account.
17. The method of claim 14, wherein each timing window of each of the potential aggressor interconnects comprises minimum and maximum rise and fall arrival times and transition times.
18. The method of claim 14, wherein the first and second timings of each cell and each victim interconnect on the critical path comprise one or more of rise and fall arrival and transition times.
19. The method of claim 18, further comprising computing a rise or a fall arrival time of a cell or a victim interconnect on the critical path according to a sum of all delays through all cells and all victim interconnects on the critical path between the start point on the critical path and the cell or the victim interconnect on the critical path of which the crosstalk analysis module is computing the rise or the fall arrival time.
20. The method of claim 14, further comprising processing each of two or more of the critical paths in parallel to generate the timing waveforms of the potential aggressor interconnects, traverse the critical path, and compute a second timing of each cell and each victim interconnect on the critical path.
21. The method of claim 14, further comprising extracting parasitics of two or more victim interconnects in parallel.
22. The method of claim 14, further comprising, to compute a second timing of a cell on a critical path, running a plurality of simulations of the cell in parallel.
23. The method of claim 14, further comprising identifying the critical paths in the design without taking crosstalk into account, without accurately modeling the design, or both.
24. The method of claim 14, further comprising identifying the potential aggressor interconnects according to distances separating interconnects in the design from each other.
25. The method of claim 14, wherein the start point is an input pin on the critical path and the end point is an output pin on the critical path.
26. The method of claim 14, wherein one or more parasitics each comprise one or more of one or more distributed coupling capacitances, one or more self capacitances, and one or more resistances.
27. Logic for crosstalk-aware timing analysis, the logic encoded in one or more media for execution and when executed by a computer is operable to:
access a design of a circuit;
identify one or more critical paths in the design, each critical path comprising one or more victim interconnects and one or more cells;
identify one or more potential aggressor interconnects associated with each victim interconnect;
for each victim interconnect, extract one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect;
compute timing windows of the potential aggressor interconnects;
compute a first timing of each cell and each victim interconnect on each critical path; and
for each critical path:
generate one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects;
traverse the critical path from a start point on the critical path to an end point on the critical path; and
using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, compute a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.
28. The logic of claim 27, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both take crosstalk into account.
29. The logic of claim 27, wherein computation of the timing windows of the potential aggressor interconnects, computation of the first timing of each cell and each victim interconnect on the critical path, or both do not take crosstalk into account.
30. The logic of claim 27, wherein each timing window of each of the potential aggressor interconnects comprises minimum and maximum rise and fall arrival times and transition times.
31. The logic of claim 27, wherein the first and second timings of each cell and each victim interconnect on the critical path comprise one or more of rise and fall arrival and transition times.
32. The logic of claim 31, further operable to compute a rise or a fall arrival time of a cell or a victim interconnect on the critical path according to a sum of all delays through all cells and all victim interconnects on the critical path between the start point on the critical path and the cell or the victim interconnect on the critical path of which the crosstalk analysis module is computing the rise or the fall arrival time.
33. The logic of claim 27, further operable to process each of two or more of the critical paths in parallel to generate the timing waveforms of the potential aggressor interconnects, traverse the critical path, and compute a second timing of each cell and each victim interconnect on the critical path.
34. The logic of claim 27, further operable to extract parasitics of two or more victim interconnects in parallel.
35. The logic of claim 27, further operable, to compute a second timing of a cell on a critical path, to run a plurality of simulations of the cell in parallel.
36. The logic of claim 27, further operable to identify the critical paths in the design without taking crosstalk into account, without accurately modeling the design, or both.
37. The logic of claim 27, further operable to identify the potential aggressor interconnects according to distances separating interconnects in the design from each other.
38. The logic of claim 27, wherein the start point is an input pin on the critical path and the end point is an output pin on the critical path.
39. The logic of claim 27, wherein one or more parasitics each comprise one or more of one or more distributed coupling capacitances, one or more self capacitances, and one or more resistances.
40. A system for crosstalk-aware timing analysis, the system comprising:
means for accessing a design of a circuit;
means for identifying one or more critical paths in the design, each critical path comprising one or more victim interconnects and one or more cells;
means for identifying one or more potential aggressor interconnects associated with each victim interconnect;
means for, for each victim interconnect, extracting one or more parasitics of the victim interconnect and the one or more potential aggressor interconnects associated with the victim interconnect;
means for computing timing windows of the potential aggressor interconnects;
means for computing a first timing of each cell and each victim interconnect on each critical path; and
means for, for each critical path:
generating one or more timing waveforms of the potential aggressor interconnects according to the first timing of each cell and each victim interconnect on the critical path, the timing windows of the potential aggressor interconnects, and the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects;
traversing the critical path from a start point on the critical path to an end point on the critical path; and
using the timing waveforms of the potential aggressor interconnects, the parasitics of the victim interconnects on the critical path associated with the potential aggressor interconnects, and any second timing of any immediately preceding cell on the critical path, computing a second timing of each cell and each victim interconnect on the critical path according to the traversal of the critical path.
Patent Citations (3)
Non-Patent Literature (19)
- Arvind, “Path Based Approach for Crosstalk Delay Analysis,” Int. Conf. on VLSI Design, pp. 727-730, Jan. 2004, 5 pages.Applicant
- Arvind, “Integrated Crosstalk and Oxide Integrity Analysis in DSM Designs,” Int. Conf. on VLSI Design, pp. 518-523, Jan. 2001, 7 pages.Applicant
- Bakoglu, “Circuits, Interconnections and Packaging,” Addison Wesley.Applicant
- Chen et al., “Analytic Models for Crosstalk Delay and Pulse Analysis Under NonIdeal Inputs,” In ITC, 1997, 12 pages.Applicant
- Chen et al., “Test Generation for Cross-Talk Induced Faluts: Framework and Computational Results,” Asian Test Symposium, 2000, 6 pages.Applicant
- Cong et al., “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization,” ASP-DAC, pp. 373-378, 2001, 6 pages.Applicant
- Devgan, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” ICCAD, Nov. 1997, 5 pages.Applicant
- Ding et al., “Efficient Crosstalk Noise Modeling Using Aggressor and Tree Reductions,” ICCAD, pp. 595-600, Nov. 2002, 6 pages.Applicant
- Franzini et al., “Crosstalk Aware Static Timing Analysis: A Two-Step Approach,” Int. Symposium on Quality Electronic Design, pp. 499-503, 2000, 5 pages.Applicant
- Kahng et al., “On Switch Factor Based Analysis of Coupled RC Interconnects,” DAC, pp. 79-84, Jun. 2000, 6 pages.Applicant
- Kuhlmann et al., “Efficient Crosstalk Estimation,” ICCD, 1999, 10 pages.Applicant
- Odabasioglu et al., “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm,” IEEE Transactions on Computer-Aided Design, 1997, pp. 1-8.Applicant
- Pillage et al., “Asymptotic Waveform Evaluation for Timing Analysis,” IEEE Transactions on Computer-Aided Design, pp. 352-366, Apr. 1990, 16 pages.Applicant
- Rajappan et al., “An Efficient Algorithm for Calculating the Worst-Case Delay Due to Crosstalk ,” ICCD, pp. 76-81, Oct. 2003, 7 pages.Applicant
- Ringe et al., “Static Timing Analysis Taking Crosstalk into Account,” DATE, pp. 639-649, May 1995, 5 pages.Applicant
- Sasaki et al., “Building a Crosstalk Library for Relative Window Methods—Timing Analysis that Includes Crosstalk Delay Degradation,” Proc. of the Asia-Pacific Conference on ASIC, Aug. 2000, 17 pages.Applicant
- Sentovich et al., “SIS: A System for Sequential Circuit Synthesis,” Memorandum No. UCB/ERL M92/41, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, California, 94720, May 1992, 45 pages.Applicant
- Vittal et al., “Crosstalk in VLSI Interconnections,” IEEE Transactions on Computer-Aided Design, Dec. 1999, 9 pages.Applicant
- Xiao et al., “Worst Delay Estimation in Crosstalk Aware Status Timing Analysis,” ICCD, Oct. 2000, 8 pages.Applicant