Method to maximize receiver performance in a multi-stream system

[0001] The present invention generally relates to receivers and, more particularly, to a satellite-based digital audio radio receiver that finds wireless satellite signals and minimizes errors in the receiver system.

[0002] Automotive vehicles are commonly equipped with audio radios for receiving broadcast radio frequency (RF) signals, processing the RF signals, and broadcasting audio information to passengers in the vehicle. More recently, satellite digital audio radio (SDAR) services have become available. SDAR services offer digital radio service covering a large geographic area, such as North America. Satellite-based digital audio radio services are available in North America, which generally employ either geo-stationary orbit satellites or highly elliptical orbit satellites that receive up-linked programming which, in turn, is rebroadcast directly to digital radios in vehicles on the ground that subscribe to the service. These systems also use terrestrial repeater networks in urban areas to supplement the availability of service. Each vehicle subscribing to the digital service generally includes a digital radio having a receiver and one or more antennas for receiving the digital broadcast.

[0003] The radio receivers are programmed to receive and unscramble the digital data signals, which typically include many channels of digital audio. In addition to broadcasting the encoded digital quality audio signals, the satellite-based digital audio radio service may also transmit data within a data bandwidth that may be used for various applications. The broadcast signal may also include other information for reasons such as advertising, informing the driver of warranty issues, providing information about the broadcast audio information, and providing news, sports, and entertainment broadcasting. Accordingly, the digital broadcast may be employed for any of a number of satellite audio radio, satellite television, satellite Internet, and various other consumer services.

[0004] In some systems with more than one signal source (i.e. multi-stream systems) and different data sources (i.e. same data with different signal sources), there is a need to find signal(s), such as, for example, wireless satellite signals, that maximizes performance of a receiver by minimizing errors in the receiver system, which results in an improved user experience. As illustrated in FIG. 1, traditional satellite-based digital audio radio services receivers 1a typically include multiple forward error correction (FEC) circuits that receive terrestrial and satellite signals provided over a terrestrial and satellite channel, respectively, to detect which communication path does not have an error, such as a burst-type error (i.e. where the signal to noise ratio is temporarily degraded). A form of FEC, which is known in the art as ‘concatenated coding,’ combines a convolutional code and a block code, which results in a code that has an inner code and an outer code.

[0005] As illustrated in FIG. 2, other known satellite-based digital audio radio services using more than one signal (or antenna), comprises a receiver 1b including a maximum ratio combiner (MRC) that combines the satellite and terrestrial channel signals. Typically, an MRC receives and aligns two signals in time or phase, weights (magnitude adjusted) signals according to a quality criteria, which results in an improved signal magnitude upon being combined together. For example, the MRC can be thought of as adding a desired signal coherently (i.e. in phase) and adding noise non-coherently (i.e. random noise where phase is unknown) such that the signal will double in voltage (i.e. a 6 dB increase). Because noise is typically non-coherent for each source, the noise will, over some time, add at a square root of two (i.e. a 3 dB increase). Since the desired signal is increased by 6 dB and the noise is increased by 3 dB, the result is a net 3 dB increase in the signal to noise ratio. Accordingly, an MRC provides an improved system performance.

[0006] The advantage of the system seen in FIG. 1, which uses multiple FEC circuits for each frequency or antenna source, is a direct selection of the frequency or antenna source that does not have any errors. By using multiple FEC algorithms, the best signal path having the least amount of bit errors carrying the RF signal from the antenna to the FEC hardware may be chosen for the source decoder. On the other hand, as seen in FIG. 2, the use of an MRC circuit prior to an FEC circuit optimally combines phase- and time-aligned signals to improve coded signal performance in a digital communication system. Essentially, the advantage of implementing an MRC circuit prior to the FEC circuit allows the receiver to obtain better performance in low signal to thermal noise (SNR) environments, such as additive white Gaussian noise (AWGN) environments.

[0007] Although adequate for most situations, there are situations where the undistorted channels are combined with distorted channels, which produces a distorted input to the FEC algorithm. The combination of a distorted signal (that has a good quality measurement) and an undistorted signal may degrade the system performance. Thus, the FEC algorithm may be undesirably corrupted by the bad signal, which produces an output error, such as an audio mute in an SDAR system. In this situation, the receiver may actually use corrupted signals that appear to be in a usable condition. For example, a terrestrial signal, which may be typically corrupted more so than satellite signals, is then passed through the MRC into the FEC, which outputs an error, where, conversely, if only the satellite signal was used, no error would have occurred. Accordingly, it is therefore desirable to provide a satellite-based digital audio radio receiver that finds wireless satellite signals and minimizes errors in the receiver system to improve the overall system performance such that undesirable errors, such as audio mutes, do not occur.

[0008] The present invention relates to a receiver. Accordingly, one embodiment of the invention is directed to a receiver that includes a channel decoder select circuit, a plurality of communication channels, at least one maximum ratio combiner circuit, and a forward error correction circuit. The plurality of communication channels receives wireless information from channel demodulators and are in communication with respective channel decoder circuits, which are in communication with the channel decoder select circuit. The at least one maximum ratio combiner circuit receives the wireless information from the plurality of communication channels. The output of the maximum ratio combiner is communicated to the forward error correction circuit, the output of which is communicated to the channel decoder select circuit. A pseudo bit error measurement feedback signal communicated to the maximum ratio combiner from one of the plurality of channel decoder circuits.

[0009] Another embodiment of the invention is directed to a receiver that includes first and second wireless signals provided from respective first and second satellite channel demodulators, and a third wireless signal provided from a terrestrial channel demodulator. First, second, and third pseudo bit error measurement signals corresponding to the first, second, and third wireless signals are communicated to a maximum ratio combiner, and a Reed-Solomon decoder processes the output of the maximum ratio combiner.

[0010] A method for finding wireless satellite signals that minimizes errors in a receiver system is also disclosed.

[0018] The above described disadvantages are overcome and a number of advantages are realized by the inventive receivers that are illustrated in FIGS. 3-6. As illustrated in FIG. 3, a receiver 10 includes a plurality of communication channels, which are labeled Channel 1 through Channel N. Channels 1 through N receive information from channel demodulators and are each input into an MRC 12, whose output is communicated to FEC 14a over line 2. Channels 1 through N are also each input to respective FEC circuits 14b, 14n. Feedback from the FEC circuit 14n is communicated over line 5a to the MRC 12, which is explained in greater detail below. The output of the FECs 14a, 14b, 14n (i.e. channel decoder circuits) is communicated to an FEC Select circuit 16 (i.e. channel decoder select circuit) over lines 3, 4, 5b, respectively. The FEC select circuit 16 outputs the FEC path that contains the minimum number of decoded errors. The minimum error output of the FEC Select circuit 16 is communicated over line 6 to a source decoder that converts the data to audio.

[0019] Communication Channels 1 through N may carry any desirable signal. According to one embodiment of the invention, if the receiver 10 is a satellite digital audio radio services (SDARS) receiver, two, three or four channels may be implemented in a design that includes multiple FEC circuits to receive satellite and terrestrial signals. For example, Channel 1-3 may carry satellite signals and Channel 4 may carry terrestrial signals. If desired, an additional MRC circuit may be implemented in the design of the receiver 10 such that one MRC processes (i.e. adds) terrestrial and satellite signals communicated over multiple channels and the second MRC processes (i.e. adds) only satellite signals communicated over other multiple channels. Essentially, the receiver 10 takes advantage of both the MRC and FEC signal switching methods such that multiple FECs are being processed and the FEC circuit having the best output is selected by the FEC Select 16. The FEC path, which is seen over communication lines 2, 3 that includes the MRC circuit 12, may be selected when the receiver 10 encounters a weak SNR environment and provides the channel decoder extra small signal performance (i.e. small signal to noise performance) to ensure that a strong corrupted signal (i.e. a signal having a signal to interference ratio) does not contaminate the channel decoder output, which results in a cross-mute.

[0020] In operation, the FEC circuits 14a-14n may be ‘time sliced.’ Essentially, the FEC circuits 14a-14n can share the same hardware (circuits) and process each path during a specific time interval. All of the channels may appear to carry a usable signal, however, corrupted signals may be detected quicker by phasing-out the MRC circuit 12, thus providing the best signal for the source decoder. Without the additional FEC processing, undetected corrupted signals cause system degradation. The additional FEC circuits 14a-14n essentially act as independent error correction devices in the receiver 10 such that when a corrupted signal is used in the MRC, the receiver 10 is able to detect an error and switch to a FEC circuit that is processing satellite signals.

[0021] The FEC circuit 14n also provides pseudo-bit error measurement feedback to the MRC 12. According to one possible implementation of the receiver system, Channel N, which communicates with the FEC circuit 14n and the MRC 12, may carry the terrestrial signal. When received in cities, the terrestrial signal typically encounters multipath conditions, which can lead to inter-symbol-interference. This phenomenon can also cause the received terrestrial signal to appear strong. Strong signals may become corrupted via the inter-symbol-interference when a far away repeater is seen by the antenna and a near repeater is blocked. The far away repeater may be on a different multi-carrier-modulation (MCM) symbol, Orthogonal Frequency Division Multiplexing (OFDM) symbol, or coded OFDM (COFDM) symbol than the near repeater, which results in the corrupted signal or error. The actual signal level may be sufficient signal to noise, but the environment has corrupted the signal information before it reaches the antenna. If the terrestrial signal is corrupted, the receiver detects the corrupted signal and provides feedback over line 5a so that the combined terrestrial and satellite signal is not used by the source decoder. Thus, the use of the FEC circuits 14b through 14n allows the receiver 10 to quickly detect when one signal is corrupted, and if neither signal is corrupted, the MRC 12 does not get phased out.

[0022] Referring now to FIG. 4, another embodiment of the receiver is seen generally at 100. The receiver 100 also includes a plurality of communication channels, which are labeled Channel 1 through Channel N. In this embodiment, Channel N is directly input to an FEC 104n while Channel 1 is input to an FEC 104a via a switch 108. Channels 1 though N are also input into an MRC circuit 102 whose output also communicates over line 2 with the FEC 104a via the switch 108. Similar to the operation of the receiver 10 described above, feedback from the FEC circuit 104n is communicated over line 8a to the MRC 102. The FEC 104a also receives a feedback signal over line 9, which is labeled “Error Detection Signal From System Controller.” More specifically, the feedback signal may be an uncorrectable error detection signal from the Reed Solomon Decoder. The bit error may arise from a corrupted terrestrial signal, a corrupted satellite signal, or even a combination of usable signals that when added together, results in an error. The output of the FECs 104a, 104n (i.e. channel decoder circuits) is communicated to an FEC Select circuit 106 (i.e. channel decoder select circuit) over lines 7, 8b respectively. The output of the FEC Select circuit 106 is communicated over line 6 to the source decoder that converts the data to audio.

[0023] Functionally, the MRC circuit 102 of the receiver 100 is disabled when the signal levels from Channels 1 through N are strong, and conversely, the MRC circuit 102 may be activated when the signal levels from Channels 1 through N are weak. Accordingly, some protection is provided against a strong corrupted signal dominating the input of the MRC circuit 102 and FECs 104a, 104n. The receiver 100 may be able to estimate the strength of the received corrupted signal relative to the noise floor since narrow band power detection may be available to the system microcontroller.

[0024] In this embodiment, the switch 108 may be adjusted based on the terrestrial and satellite power level seen by the receiver. For example, Channel 1 may carry the satellite signal and Channel N may carry the terrestrial signal. In this scenario, the receiver 100 may just look at the terrestrial and satellite signals independently by positioning the switch 108 at position B to monitor each signal on the respective FEC circuits 104a, 104n. Conversely, the terrestrial and satellite signals maybe combined and monitored by positioning the switch 108 to position A such that the receiver sees the output from the MRC 102 at line 2. Thus, signal processing time may be saved because one less FEC block is implemented (in view of FIG. 3), however, additional hardware is needed to enable the receiver 100 to choose whether or not the MRC circuit 102 is to be used. Even further, the receiver 100 is less complex than the receiver 10 (because there aren't as many FECs) while also providing channel decoding enhancements. Essentially, the switch 108 acts as a blind switch because the receiver 100 does not look for all error possibilities simultaneously, whereas the receiver 10 does.

[0025] Essentially, if all of the received signals from the Channels are sufficiently strong in the signal noise estimation, then the receiver 100 operates by just using the FECs 104a, 104n without the MRC 102, because, if the signals are good to begin with, there is no need to use the MRC 102. Accordingly, the receiver 100 keeps track of the occurrence of a bad signal (e.g. a corrupted terrestrial signal) input to an FEC. Conversely, if a weak signal is present, then the receiver 100 takes advantage of the MRC circuit 102 because the corrupted signal may not be some type of interference, but rather, noise.

[0026] Referring now to FIG. 5, another embodiment of the receiver is seen generally at 200. The receiver 200 also includes a plurality of communication channels, which are labeled A, B, and C. Communication channels A and B receive information from Satellite Channel Demodulators 1 and 2, respectively, whereas, communication channel C receives information from a Terrestrial Channel Demodulator. As illustrated, communication channels A, B, C are directly fed into an MRC weighting block, which is seen generally at 202, the output of which is communicated to an MRC 204 over lines 11, 13, 15. The output of the MRC 204 is communicated over line 17 to an FEC circuit 206, the output of which is communicated over line 19 to an FEC Select circuit 208.

[0027] In this embodiment, communication channel C, which carries the terrestrial signal, is split three ways. The first split enters the MRC weighting block 202, the second split enters a hard detection circuit 212, and the third split enters an FEC circuit 214. The output of the FEC circuit 214 is communicated to an encoder 216 and to the FEC Select circuit 208 over line 21. The output of the encoder 216 is communicated to a pseudo bit error rate (BER) circuit 218 over line 23, which also receives the output of the hard detection circuit 212 over line 25. The output of the pseudo BER circuit 218 is communicated over 27 to a weighting algorithm 220, the output of which is communicated over line 29 to the MRC weighting block 202.

[0028] The receiver 200 permits weighting of a multi-carrier OFDM or COFDM signal, such as the terrestrial signal, into the MRC circuit 204 by using a pseudo bit error rate of the FEC circuit 214. The FEC circuit 214 receives information over communication channel C in the form of soft bits (i.e. 0.50 or 0.25 are considered soft bits, whereas 1 or 0 are considered hard bits). In an SDARS implementation associated with the illustrated receiver 200, the FEC circuit 214, which may comprise a Viterbi or Turbo decoder, decodes soft bits and outputs hard bits, which are subsequently re-encoded by the encoder 216 into hard bits. Assuming that the output of the FEC circuit 214 is truth data (i.e. a corrected, decoded signal), the encoder 216 outputs hard bits that correspond to a corrected signal. The received transmitted signal from communication channel C is simultaneously processed by the hard detection circuit 212, which produces a hard bit of the original terrestrial signal. The hard decision output and FEC corrected data output seen at lines 23, 25 is compared by the pseudo BER circuit 218. As illustrated, the weighting algorithm 220 receives the output of the pseudo BER circuit 218. The weighting algorithm may comprise a look-up table or other non-linear control, and is based upon the number of estimated errors for uncorrected bit error rates.

[0029] The MRC weighting block 202 receives the output from the weighting algorithm 220 at a weighting amplifier 222c. Two additional weighting amplifiers 222a, 222b process an SNR estimation and the information received from Satellite Channels 1 and 2 over communication lines A and B, respectively. The SNR estimation may be based on the power level into the receiver 200, which may be signal power or noise power. The SNR estimation may also include a straight power detection where noise is assumed at some level, a correlation measurement where some known data signal is auto-correlated and compared to noise, or an examination at the carrier tracking loop (i.e. a noisy loop indicates a lower signal to noise ratio). The output of each weighting amplifier 222a-222c is communicated to the MRC circuit 204. Functionally, the output of the MRC 204, FEC 206, and FEC 214 that is communicated into the FEC Select 208 behaves in a similar fashion as described above with respect to the receivers 10, 100.

[0030] Referring now to FIG. 6, another embodiment of the receiver is seen generally at 300. The receiver 300 also includes a plurality of communication channels, which are labeled A, B, and C. Communication channels A and B receive information from Satellite Channel Demodulators 1 and 2, respectively, whereas, communication channel C receives information from the Terrestrial Channel Demodulator. Similar to the receiver 200, the receiver 300 provides a pseudo-bit error measurement prior to processing at the MRC circuit 308. As illustrated, communication channels A, B, C are directly fed into convolutional decoders 302a-302c and Pseudo BER circuits 306a-306c over communication lines 33a-33c, respectively. The output of the convolutional decoders 302a-302c are communicated to convolutional encoders 304a-304c over lines 35a-35c, and an MRC circuit 308 over communication lines 37a-37c, respectively. The output of the convolutional encoders 304a-304c are communicated to the Pseudo BER circuits 306a-306c. The output of the Pseudo BER circuits 306a-306c is also communicated to the MRC circuit 308 over lines 39a-39c. The output of the MRC circuit is communicated over line 41 to a Reed-Solomon decoder 310, the output of which is communicated over line 43.

[0031] In this embodiment, the elements comprising an FEC circuit is split between the MRC circuit 308. The FEC circuit typically includes a convolutional decoder, seen at elements 302a-302c, and a Reed-Solomon decoder, seen at element 310. In the illustrated SDARS-related implementation, the convolutional decoder 302a-302c may be Viterbi or Turbo decoders, which produces the inner code of a concatenated code. The Reed-Solomon decoder, on the other hand, produces the outer code of a concatenated code. As illustrated, the convolutional decoder 302a-302c, convolutional encoder 304a-304c, and pseudo BER 306a-306c each provide the MRC circuit 308 with an approximated bit error rate on the inner code and the Reed Solomon detector 310 provides improved signal to noise estimates based on the bit error rates.

[0032] Accordingly, by ‘splitting the FEC circuit,’ the number of Reed-Solomon circuits is reduced to one unit that serves a plurality of convolutional decoders, which also reduces the number of computations carried out in the associated software. The output of the Reed-Solomon circuit 310 is time-division multiplexed such that the source decoder may acquire the desired data aligned in a specific time-slot. Although not illustrated, the MRC circuit 308 includes the weighting algorithm which can be carried out by a multiplier in an application specific integrated circuit (ASIC), based on the SNR to ensure that a good signal is not degraded by the noise of a bad signal.

[0033] The present invention has been described with reference to certain exemplary embodiments thereof. However, it will be readily apparent to those skilled in the art that it is possible to embody the invention in specific forms other than those of the exemplary embodiments described above. This may be done without departing from the spirit of the invention. The exemplary embodiments are merely illustrative and should not be considered restrictive in any way. The scope of the invention is defined by the appended claims and their equivalents, rather than by the preceding description.