Multi-phase techniques for tuning and/or measuring operations of an amplifier

[0001] 1. Field of the Invention

[0002] The present invention relates to electronics, and, in particular, to techniques for tuning and/or measuring operations of an amplifier, such as an operational transconductance amplifier or a variable gain amplifier.

[0003] 2. Description of the Related Art

[0004] FIG. 1 illustrates a block diagram of a conventional circuit 100 for tuning an operational transconductance amplifier (OTA) 102. In addition to OTA cell 102, tuning circuit 100 includes reference OTA cell 101 and comparator 103. The output nodes of OTA cells 101 and 102 are connected together and to the positive input node of comparator 103, which shared node is at voltage V_o,gm.

[0005] V_tune is a tuning voltage that is used to adjust the transconductance (g_m2) of OTA cell 102. Input voltages V₁ and V₂ are applied across the input nodes of OTA cells 101 and 102, respectively, where voltages V₁ and V₂ have identical magnitude, but opposite polarities as indicated in FIG. 1. With voltages V₁ and V₂ applied with the polarities indicated in FIG. 1, reference OTA cell 101 sources current i_out, and OTA cell 102 sinks current i_in. If i_out equals i_in, then the shared node voltage V_o,gm is zero, since voltage V_o,gm corresponds to the current flowing into the positive input node of comparator 103 times the impedance of that input node. If i_out≠i_in, then the excess current is either sourced or sunk by the positive input node of comparator 103, which causes V_o,gm to be either greater than or less than zero. Because the negative input node of comparator 103 is connected to ground, the output voltage V_out of comparator 103 toggles between a logical 0 and a logical 1 when the value of the difference in current, i_out−i_in, changes polarity, thus causing the shared node voltage V_o,gm to change its polarity.

[0006] A balanced condition occurs when i_out=i_in and V_o,gm=0. Stated differently, the balanced condition occurs when g_m1V₁=g_m2V₂ (i.e., g_m2=g_m1(V₁/V₂)). As such, OTA cell 102 may be successfully tuned by adjusting voltage V_tune to determine when such a balanced condition between currents i_in, and i_out exists by monitoring the output of comparator 103.

[0007] FIG. 2 illustrates a more-detailed block diagram of the tuning circuit of FIG. 1. As indicated in FIG. 2, real-world (i.e., actual, physical) implementations of OTA cells 101-102 and comparator 103 include non-idealized electrical properties such as finite output impedances and offsets voltages. In particular, in addition to reference transconductance g_m1, reference OTA cell 101 has an offset voltage measured at its input nodes (represented by V_os1 in FIG. 2) and a finite output impedance (represented by g_o1 in FIG. 2). Similarly, in addition to transconductance g_m2 to be tuned, OTA cell 102 has an offset voltage (represented by V_os2 in FIG. 2) and a finite output impedance (represented by g_o2 in FIG. 2). Comparator 103 also has an offset voltage (represented by V_osc in FIG. 2). By taking all of these non-ideal circuit properties into account, a more-accurate model for the operation of tuning circuit 100 may be developed and transconductance g_m2 may be tuned more accurately.

[0008] By using node analysis on node V_o,gm, the balanced condition is defined by Equation (1):
g_m1·(V₁+V_os1)=(−V_osc)·(g_o1+g_o2)+g_m2·(V₂+V_os2)  (1)
Equation (1) may be rewritten in terms of g_m2 as Equation (2):

[0009] $\begin{array}{cc}{g}_{m2}=g_{m1}·\left(\frac{V_1+V_{\mathrm{os}1}}{V_2+V_{\mathrm{os}2}}\right)+\left(\frac{V_{\mathrm{osc}}}{V_2+V_{\mathrm{os}2}}\right)·\left(g_{o1}+g_{o2}\right)& \left(2\right)\end{array}$

[0010] From Equation (2), transconductance g_m2 may be different from transconductance g_m1 even with the magnitude of voltage V₁ equal to the magnitude of voltage V₂. The finite output impedances (g_o1 and g_o2) and offset voltages (V_os1 and V_os2) of OTA cells 101 and 102, and the offset voltage (V_osc) of comparator 203 limit the ability to accurately match transconductance g_m1 and transconductance g_m2. The relative error between transconductance g_m2 and reference transconductance g_m1 depends on these values as well as on voltages V₁ and V₂.

[0011] Finite output impedance g_o1 may be made fairly small, since reference OTA cell 101 does not need to process data while in use and, as a result, may be operated slowly. But finite output impedance g_o2 may correspond to a relatively large fraction of g_m2. This condition is especially likely with advanced technologies and high-speed applications. Even without offset voltages V_os1 and V_os2, an error of a few percent may be observed because of the finite output impedances of OTA cells 101-102 and the offset voltage V_osc of comparator 203. This amount of error might not be acceptable for some applications.

[0012] In one embodiment, the present invention is a method for operating an amplifier having at least one operating parameter, the method comprising first and second phases. During the first phase, (1) a first-phase input voltage is applied to the amplifier to generate a first-phase amplifier output signal and (2) the first-phase amplifier output signal and a first-phase reference signal are applied to a comparator to generate a first-phase comparison result. The first-phase comparison result depends on the at least one operating parameter. During the second phase, (1) a second-phase input voltage is applied to the amplifier to generate a second-phase amplifier output signal, wherein the second-phase input voltage is different from the first-phase input voltage and (2) the second-phase amplifier output signal and a second-phase reference signal are applied to the comparator to generate a second-phase comparison result. The second-phase comparison result depends on the at least one operating parameter. The first-phase and second-phase comparison results are combined to generate a final result such that dependence of the final result on the at least one amplifier operating parameter is negated or reduced.

[0013] In another embodiment, the present invention is circuitry comprising an amplifier, a comparator, and a control module. The amplifier has at least one operating parameter. The comparator is (1) connected to receive and compare an output signal from the amplifier and a reference signal and (2) generates a comparison result based on the comparison of the amplifier output signal and the reference signal. The control module controls selection of input voltages applied to the amplifier and processes comparison results from the comparator during first and second phases of operation of the circuitry. During the first phase, (1) a first-phase input voltage is applied to the amplifier to generate a first-phase amplifier output signal and (2) the first-phase amplifier output signal and a first-phase reference signal are applied to the comparator to generate a first-phase comparison result. The first-phase comparison result depends on the at least one operating parameter. During the second phase, (1) a second-phase input voltage is applied to the amplifier to generate a second-phase amplifier output signal, wherein the second-phase input voltage is different from the first-phase input voltage and (2) the second-phase amplifier output signal and a second-phase reference signal are applied to the comparator to generate a second-phase comparison result. The second-phase comparison result depends on the at least one operating parameter. The first-phase and second-phase comparison results are combined to generate a final result such that dependence of the final result on the at least one amplifier operating parameter is negated or reduced.

[0014] In yet another embodiment, the invention is circuitry comprising a variable-gain amplifier, a first switch module, a comparator, a second switch module, and a control module. The variable-gain amplifier comprises at least one operating parameter, a first amplifier input node, a second amplifier input node, and a gain control input node. The amplifier is adapted to (1) generate a first-phase amplifier output signal during a first phase and (2) generate a second-phase amplifier output signal during a first phase. The first switch module comprises a first S1 switch and a first S2 switch. The first S1 switch comprises a S1 first input node coupled to the first-phase input voltage and a second S1 input node coupled to the first amplifier input node of the amplifier. The first S2 switch comprises a S2 first input node coupled to the second-phase input voltage and a S2 second input node coupled to the first amplifier input node and to the second S1 input node of the first S1 switch. The comparator comprises a first comparator input node and a second comparator input node, and is adapted to (1) generate a first-phase comparison result during the first phase, wherein the first-phase comparison result depends on the at least one operating parameter and (2) generate a second-phase comparison result during the second phase, wherein the second-phase comparison result depends on the at least one operating parameter. The second switch module comprises a second S1 switch and a second S2 switch. The second S1 switch comprises a first S1a input node coupled to the first-phase reference signal and a second S1a input node coupled to the first comparator input node. The second S2 switch comprises a first S2a input node coupled to the second-phase reference signal and a second S2a input node coupled to the first comparator input node and to the second S1a input of second S1 switch. The control module has a gain control output node coupled to the gain control input node of the variable-gain amplifier, and is adapted to (1) adjust the gain of the variable gain amplifier during the first phase to generate the first-phase comparison result, (2) adjust the gain of the variable gain amplifier during the second phase to generate the second-phase comparison result, and (3) combine the first-phase and second-phase comparison results to generate a final result such that dependence of the final result on the at least one amplifier operating parameter is negated or reduced. The first S1 switch and the second S1 switch are closed during the first phase. The first S2 switch and the second S2 switch are closed during the second phase.

[0022] FIG. 3 illustrates a block diagram of circuit 300 for tuning operational transconductance amplifier 102, according to one possible embodiment of the present invention. In addition to tuning circuit 100 of FIGS. 1 and 2, tuning circuit 300 comprises a first switch module 301 connected between voltage V₁ and the input nodes of reference OTA cell 101 and a second switch module 302 connected between a voltage V_DAC and the input nodes of “to-be-tuned” OTA cell 102. Each switch module includes two pairs of switches S₁ and S₂. During two non-overlapping phases of the operation of tuning circuit 300, the input voltages, V₁ and V_DAC, are applied to the input nodes of OTA cells 101-102, respectively, but with different polarity configurations. Voltages V₁ and V_DAC are voltages having identical magnitudes but opposite polarities. Using node analysis similar to the analysis discussed above with reference to FIGS. 1-2, a set of equations may be developed.

[0023] During phase one, switches S₁ are closed and switches S₂ are open in both switch modules 301 and 302, in order to apply voltage V₁ and voltage V_DAC with a first polarity configuration to the input nodes of OTA cell 101 and OTA cell 102, respectively. V_tune is adjusted until a balanced condition exists, for which Equation (3) applies:
g_m1·(V₁+V_os1)=(−V_osc)·(g_o1+g_o2)+g_m2·(V₂+V_os2)  (3)
The particular value of tuning voltage V_tune corresponding to the phase-one balanced condition of Equation (3) may be denoted as a control voltage V_tune¹.

[0024] Similarly, during phase two, switches S₁ are open and switches S₂ are closed in both switch modules 301 and 302, in order to apply voltage V₁ and voltage V_DAC with a second polarity configuration to the input nodes of OTA cell 101 and OTA cell 102, respectively. V_tune is again adjusted until a balanced condition exists, for which Equation (4) applies:
g′_m2·(V₂−V′_os2)=(−V_osc)·(g_o1+g′_o2)+g_m1·(V₁−V_os1)  (4)
where g′_m2, V′_os2, and g′_o2 correspond to the transconductance, offset voltage, and finite output impedance of OTA cell 102 during phase two. The particular value of tuning voltage V_tune corresponding to the phase-two balanced condition of Equation (4) may be denoted as a control voltage V_tune².

[0025] Adding Equations (3) and (4) yields Equation (5) as follows:
(g_m2+g′_m2)·V₂=2g_m1V₁−(g_m2V_os2−g′_m2V′_os2)+(g_os2+g′_os2)·V_osc  (5)
Note that the output impedance of OTA cell 101, the offset voltage of OTA cell 101, and the offset voltage of comparator 103 do not appear in Equation (5). Because g_m2 is close to g′_m2 in Equation (5) where the difference between g_m2 and g′_m2 is caused by the non-ideal circuit properties, and because V_os2 is close to V′_os2, the term g_m2V_os2−g′_m2V′_os2 is small compared to 2 g_m1V₁. Similarly, g_o2 is close to g_o1, and (g_o2−g′_o2) is small compared to 2g_m1V₁. As such, Equation (5) may be simplified as follows:
(g_m2+g′_m2)·V₂=2g_m1V₁  (6)

[0026] By choosing

[0027] $V_{\mathrm{tune}}=\left(\frac{V_{\mathrm{tune}}^1+V_{\mathrm{tune}}^2}{2}\right),$
tuning circuit 300 may more accurately match the transconductance of OTA cell 102 to the transconductance of reference OTA cell 101. As long as transconductance g_m2 is proportional to V_tune monotonically, transconductance g_m2 may be accurately matched to transconductance g_m1. If V_tune is digitally controlled by a digital-to-analog converter (DAC), then a result may be determined using the average of the two DAC values corresponding to V_tune¹ and V_tune².

[0028] FIG. 4 illustrates a block diagram of a circuit 400 for measuring the transconductance of an operational transconductance amplifier 402, according to one possible embodiment of the present invention. Measurement circuit 400 is identical to tuning circuit 300 of FIG. 3, except that to-be-tuned OTA cell 402 does not utilize a tuning voltage V_tune.

[0029] The two-phase procedure discussed with regard to tuning circuit 300 may be used with circuit 400 to determine the transconductance of OTA cell 402. Instead of applying a fixed input voltage V_DAC having the same magnitude as V₁, input voltage V_DAC is adjusted until a balanced condition is achieved (i.e., where the output voltage of comparator 103 just begins to toggle between logical 0 and logical 1) during each of the two phases of operation. Switches S₁ are closed during phase one to determine input voltage V_DAC¹ at which the phase-one balanced condition exists. During phase two, switches S₂ are closed and input voltage V_DAC² is determined at which the phase-two balanced condition exists.

[0030] The following equations apply to phase one and phase two for circuit 400:
g_m1·(V₁+V_os1)=(−V_osc)·(g_os1+g_os2)+g_m2·(V_DAC¹+V_os2)  (7)
g_m2·(V_DAC²−V_os2)=(−V_osc)·(g_os1+g_os2)+g_m1·(V₁−V_os1)  (8)

[0031] Adding Equations (7) and (8) yields Equation (9) as follows:

[0032] $\begin{array}{cc}{g}_{m2}=g_{m1}·\left(\frac{2V_1}{V_{\mathrm{DAC}}^1+V_{\mathrm{DAC}}^2}\right)& \left(9\right)\end{array}$
All of the non-idealized circuit parameters disappear and a precise measurement for the transconductance of OTA cell 402 is obtained using Equation (9).

[0033] FIG. 5 illustrates a block diagram of a circuit 500 for measuring the transconductance of operational transconductance amplifier 402, according to another possible embodiment of the present invention. Measuring circuit 500 is identical to measuring circuit 400 of FIG. 4, except that switch modules 301 and 302 are omitted. Instead of switching the polarities of input voltages V₁ and V_DAC during the two phases of operation of measurement circuit 500, the magnitude of input voltage V₁ applied to reference OTA cell 101 is doubled for phase two. That is, input voltage V₁ is applied to OTA cell 101 during phase one, and input voltage 2V₁ is applied to OTA cell 101 during phase two. As in the measurement procedure of circuit 400, during each of the two phases for circuit 500, voltage V_DAC is adjusted to achieve a balanced condition.

[0034] The following equations apply to phase one and phase two for circuit 500:
g_m2·(V_DAC¹+V_os2)=(−V_osc)·(g_o1+g_o2)+g_m1·(V₁−V_os1)  (10)
g_m2·(V_DAC²+V_os2)=(−V_osc)·(g_o1+g_o2)+g_m1·(2V₁−V_os1)  (11)

[0035] Subtracting Equation (10) from Equation (11) yields Equation (12) as follows:

[0036] $\begin{array}{cc}{g}_{m2}=g_{m1}·\left(\frac{V_1}{V_{\mathrm{DAC}}^2-V_{\mathrm{DAC}}^1}\right)& \left(12\right)\end{array}$

[0037] Therefore, by measuring the voltage V_DAC during each of the two phases that generates a balanced condition and using the known transconductance g_m1, from reference OTA cell 101, a precise measurement of the transconductance g_m2 of OTA cell 402 may be determined using Equation (12).

[0038] The above examples illustrate techniques for tuning an OTA or measuring the transconductance of an OTA. The present invention may also be applied to other types of amplifiers such as variable gain amplifiers.

[0039] FIG. 6 illustrates a block diagram of a circuit 600 for tuning the gain A of a variable gain amplifier (VGA) 601, according to one embodiment of the present invention. In addition to VGA 601, circuit 600 comprises comparator 602, control module 603, voltage-dividing resistor network 604, first switch module 611, and second switch module 612. In this exemplary implementation, circuit 600 tunes the VGA gain to have a value A of 4.

[0040] Resistor network 604 divides an 8Vi differential voltage range, such that voltages +V_i and 0 are applied to the two inputs of first switch module 611, and voltages +4V_i and −4V_i are applied to the two inputs of second switch module 612. The number and value of the resistors within voltage divider resistor network 604 are selected to provide voltages having a desired magnitude ratio of 4:1. One skilled in the art will recognize that other circuitry may be implemented to provide input voltages with that same 4:1 magnitude ratio (or a different magnitude ratio) without departing from the spirit and scope of the present invention.

[0041] The output from first switch module 611 is applied to a first input of VGA 601. A zero-volt voltage is applied to a second input of VGA 601. The output of VGA 601 is connected to one of the two inputs of comparator 602, and the single output of switch module 612 is connected to the other input of comparator 602. The output (621) of comparator 602 is applied to control module 603, which generates control signal 622 for controlling the gain A of VGA 601.

[0042] During phase one of a two-phase tuning operation for circuit 600, switches S₁ are closed and switches S₂ are open in both switch modules, such that input voltages +V_i and 0 are applied to the inputs of VGA 601, and +4V_i is applied to the second input of comparator 602. During phase two, switches S₁ are open and switches S₂ are closed, such that input voltages −V_i and 0 are applied to the inputs of VGA 601, and −4V_i is applied to the second input of comparator 602.

[0043] During phase one, VGA 601 generates an output voltage V_amp that corresponds to AV_i, and comparator 602 generates digital signal 621 having a logical value of 1 when V_amp>4V_i and a logical value of 0 when V_amp<4V_i. Digital signal 621 is transmitted to control module 603 for use in adjusting the gain value A within VGA 601. If digital signal 621 is a logical 1, then control module 603 lowers gain value A within VGA 601 using gain control signal 622. If digital signal 621 is a logical 0, then control module 603 raises gain value A within VGA 601 using gain control signal 622. When digital signal 621 just toggles between a logical 1 and a logical 0, comparator 602 indicates that V_amp=4V_i. As such, control module 603 adjusts the gain value A within VGA 601 until digital signal 621 just toggles between a logical 0 and a logical 1.

[0044] Control module 603 may adjust the gain value A to tune VGA 601 using any number of search procedures. In one embodiment, control module 603 may adjust the gain value A by sequentially increasing or decreasing the value of gain control signal 622 by a single step within a plurality of equally-spaced values across a range of possible values until digital signal 621 changes state. In another embodiment, control module 603 may increase or decrease the value of gain control signal 622 within the range of possible values using a binary search algorithm to determine more quickly the value for gain control signal 622 corresponding to the desired gain value of 4. One skilled in the art will recognize that different possible search procedures affect both the complexity of control module 603 and the number of adjustments required for control module 603 to successfully tune the gain value A. More complex search procedures will typically generate a faster search.

[0045] Control module 603 may be implemented using a programmable processor that executes instructions to implement the variable gain search procedure that adjusts the gain value A by altering gain control signal 622. Control module 603 may also be implemented using a state machine and/or digital logic functions to implement the variable gain search procedure that adjusts the gain value A.

[0046] In one possible implementation of circuit 600, gain control signal 622 corresponds to a bias current within variable gain amplifier 601. When the bias current is modified, the gain value A changes. One skilled in that art recognizes that other input control signals may be used that provide a relationship between the particular control signal and the gain value A without departing from the spirit and scope of the present invention.

[0047] As is the case with respect to the OTAs and comparators in FIGS. 1-5, and as indicated in FIG. 6, real-world implementations of VGA 601 and comparator 602 have offset voltages V_osa and V_osc, respectively, that may need to be considered when tuning a variable gain amplifier. Using the two-phase procedure discussed previously, during phase two, the input voltages to VGA 601 are swapped and an input voltage of −4V_i is applied to comparator 602. In this case, V_amp=−AV_in, and digital signal 621 is a logical 1 when V_amp>−4V_i and a logical value of 0 when V_amp<−4V_i. An analogous search procedure is implemented to adjust the gain value A until the state of digital signal 621 just toggles.

[0048] The following equations apply to phase one and phase two for circuit 600:
A₁·(V_i+V_osa)=4V_i−V_osc  (13)
A₂·(−V_i+V_osa)=−4V_i−V_osc  (14)
where A₁ is the phase-one tuned VGA gain and A₂ is the phase-two tuned VGA gain.

[0049] Subtracting Equation (14) from Equation (13) yields Equation (15) as follows:
(A₁+A₂)·V_i+(A₁−A₂)·V_osa=8V_i  (15)
Because the term (A₁−A₂)V_osa in Equation (15) is very small (because A₁ and A₂ are nearly identical), Equation (15) may be simplified as follows:

[0050] $\begin{array}{cc}\left(A_1+A_2\right)·V_i=8V_i& \left(16\right)\\ \left(A_1+A_2\right)=8& \left(17\right)\\ \frac{\left(A_1+A_2\right)}{2}=4& \left(18\right)\end{array}$
Therefore, by setting the gain of VGA 601 to the average of A₁ and A₂, VGA 601 will operate with an effective gain that is close to the desired gain value of 4 over the entire range of voltages from +4V_i to −4V_i and possibly over an even wider voltage range.

[0051] In the example of circuit 600, a desired gain value of 4 was used. Different desired gain values may be obtained by using the voltage ratio of NV₁/V_i where N corresponds to the desired gain value. A different voltage-divider resistor network 603 would be needed to generate the proper ratio of NV_i to V_i for values of N other than 4. Because the V_i term drops from Equation (16) when it is simplified further in Equation (17), the voltage value V_i and NV_i may correspond to any voltage value having a ratio of N without departing from the spirit and scope of the present invention.

[0052] Although the present invention has been described in the context of two-phase procedures for tuning or measuring the operations of amplifiers, where the results of the two phases are combined to generate a final result, in which the effects of certain real-world properties such as finite output impedances or offset voltages are either negated or negligible, the invention can also be implemented using multi-phase procedures having more than two phases in which the results of the different phases are combined to generate a final result that negates or reduces the effects of such real-world properties. Such procedures may be designed to negate or reduce the effects of real-world properties other than output impedances and offset voltages, such as mismatch, non-linearity, systematic errors, etc.

[0053] While the exemplary embodiments of the present invention have been described with respect to processes of circuits, including possible implementation as a single integrated circuit, a multi-chip module, a single card, or a multi-card circuit pack, the present invention is not so limited. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing steps in a software program. Such software may be employed in, for example, a digital signal processor, a micro-controller, or a general-purpose computer.

[0054] Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.

[0055] It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.

[0056] The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.

[0057] Although the steps in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.