Liquid crystal display and driving method thereof

[0001] (a) Field of the Invention

[0002] The present invention relates to a liquid crystal display and a driving method thereof.

[0003] (b) Description of the Related Art

[0004] Liquid crystal displays (LCDs) are the most commonly used one of flat panel displays (FPDs) handy to carry.

[0005] An LCD includes a pair of panels having field-generating electrodes and polarizers, and a liquid crystal (LC) layer with dielectric anisotropy, which is interposed between the panels and subject to electric field generated by the electrodes. The variation of the field strength changes molecular orientations of the LC layer, which tend to align parallel or perpendicular to the field direction. The LCD passes light through the LC layer via the polarizers and reorients the LC molecules to change the polarization of the light. The polarizers convert the change of the polarization into the change of the light transmittance and enable to obtain desired images.

[0006] The LCD has a narrow viewing angle. In particular, a twisted-nematic (TN) mode LCD having nematic LC with twisted alignment is widely used due to its many advantages, its application to monitors and television sets is limited due to its narrow viewing angle.

[0007] Several techniques such as multi-domains and compensation films for widening the viewing angle of the LCD are developed. In particular, compensation films often called wide viewing films give viewing characteristics in a lateral direction as good as other wide viewing techniques. However, gray inversion (that the brightness decreases as the gray voltage increases in a normally black mode LCD or vice versa in a normally white mode LCD) in a vertical direction still remains, which is severe particularly when viewing from the bottom.

[0008] Furthermore, a multi-domain LCD shows poor visibility at a lateral view compared with a normal TN mode LCD due to the inconsistency of gamma curves for a lateral view and for a front view. For example, a patterned-vertically-aligned (PVA) mode LCD having cutouts for forming domains displays brighter and whiter images as it goes away from the front to the lateral side. Sometimes, the brightness of the higher grays becomes indistinguishable to make the image mashed.

[0009] A liquid crystal display according to an aspect of the present invention includes: a plurality of pixels arranged in a column; a plurality of gate lines; and first and second data lines adjacent to the pixels, wherein each pixel is connected to one of the gate lines, the pixels are alternately connected to the first and the second data lines at least every one row, and the first and the second data lines provide data signals having polarity reversed at least every one row such that the pixels receive the data voltages having the same polarity.

[0010] A liquid crystal display according to an aspect of the present invention includes: a liquid crystal panel assembly including a plurality of pixels arranged in a matrix including a plurality of rows and a plurality of columns, a plurality of gate lines, and a plurality of data lines, wherein the number of the data lines is larger than the number of the columns, the data lines are separated from each other in the panel assembly, each pixel is connected to one of the gate lines and adjacent to two of the data lines, and the pixels in each column are alternately connected to the adjacent data lines at least every one row.

[0011] Each pixel includes two subpixels, and each subpixel includes a switching element. Two of the pixels adjacent to each other in a column are capacitively coupled.

[0012] Preferably, at least two of the data lines, particularly a first data line and a last data line are supplied with the same data signals.

[0013] The liquid crystal display further includes a plurality of data driving ICs having a plurality of output terminals connected to the data lines and including a first driving IC having a first output terminal electrically connected to the first data line and the last data line.

[0014] The liquid crystal display further includes a printed circuit board including a circuit element for driving the data driving ICs; and first and second flexible printed circuit films connecting the panel assembly and the printed circuit board, mounting the data driving ICs, and including a first signal line connected to the first output terminal of the first driving IC and a second signal line connected to the first data line, respectively, wherein the printed circuit board includes a third signal line connected between the first signal line and the second signal line.

[0015] The liquid crystal display further includes a signal controller for providing image signals and a control signal for controlling the image signals for the data driving ICs, the signal generator last supplying the image signals for the pixels in a first column connected to the first data line and first supplying the image signals for the pixels in the first column connected to a second data line.

[0016] According to an embodiment of the present invention, a method of driving a liquid crystal display including a plurality of pixels arranged in a matrix including a plurality of rows and a plurality of columns, a plurality of gate lines, and a plurality of data lines, each pixel connected to one of the gate lines and adjacent to two of the data lines, the pixels in each column alternately connected to the adjacent data lines at least every one row is provided which includes: receiving a plurality of image signals for the pixel in a row; storing a first image signal among the received image signals; sequentially outputting the image signals from a second image signal; and outputting the stored first image signal.

[0017] The method further includes: converting the image signals into data signals; and supplying the data signals for the data lines, the data signals to be applied to adjacent two pixels in a row having opposite polarities and the data signals to be applied to adjacent two pixels in a column having the same polarity.

[0036] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0037] In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region, substrate or panel is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0038] Then, liquid crystal displays and driving methods thereof according to embodiments of the present invention will be described with reference to the drawings.

[0039] FIG. 1 is a block diagram of an LCD according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of an LCD according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an LCD according to an embodiment of the present invention.

[0040] Referring to FIG. 1, an LCD according to an embodiment includes an LC panel assembly 300, a gate driver 400 and a data driver 500 which are connected to the panel assembly 300, a driving voltage generator 560 connected to the gate driver 400, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 controlling the above elements.

[0041] The panel assembly 300 includes a plurality of display signal lines G₁-G_n, D₀-D_m and 131 and a plurality of pixels connected thereto and arranged substantially in a matrix.

[0042] The display signal lines G₁-G_n and D₀-D_m include a plurality of gate lines G₁-G_n transmitting gate signals (called scanning signals) and a plurality of data lines D₀-D_m transmitting data signals. The gate lines G₁-G_n extend substantially in a row direction and are substantially parallel to each other, and the data lines D₀-D_m extend substantially in a column direction and are substantially parallel to each other.

[0043] The display signal lines 131 further includes a plurality of storage electrode lines 131 located between the gate lines G₁-G_n and between the pixels and supplied with a common voltage Vcom.

[0044] Referring to FIG. 2, each pixel P_ij (i=1, 2, . . . , n and j=1, 2, . . . , m) includes a pair of subpixels P_i,j¹ and P_i,j², and each subpixel P_i,j¹ or P_i,j² includes a switching element Q1 or Q2 connected to a pair of one of the gate lines G₁-G_n and one of the data lines D₀-D_m, and an LC capacitor C_LC1 or C_LC2 and a storage capacitor C_ST1 or C_ST2 that are connected to the switching element Q1 or Q2.

[0045] Two adjacent pixels in the column direction are capacitively coupled by a coupling capacitor Cpp. For example, an upper subpixel P_i,j¹ of a pixel P_ij is capacitively coupled with a lower subpixel P_i,j² of an upper pixel P_i−1,j, and a lower subpixel P_i,j² of a pixel P_ij is capacitively coupled with an upper subpixel P_i+1;j¹ of a lower pixel P_i+1,j.

[0046] The pixels in one pixel column are alternately connected to two data lines located on both hands of the pixel column. For example, a pixel P_ij in the j-th column is connected to the (j−1)-th data line D_j−1, while a next pixel P_i+1,j is connected to the j-th data line D_j. On the contrary, the pixels in one pixel row are connected to the data lines on the same hand. For example, all pixels in the i-th row is connected to the left data lines, while all pixels in the (i+1)-th are connected to the right data lines.

[0047] Such a connection between the pixels and the data lines D₀-D₁ requires the data lines D₀-D₁ more than the pixel columns by one.

[0048] According to another embodiment of the present invention, all pixels in one pixel column are connected to the same data line. In this case, the number of the data lines D₀-D₁ is equal to the number of the pixel columns.

[0049] The switching element Q1 or Q2 has three terminals: a control terminal connected to one of the gate lines G₁-G_n; an input terminal connected to one of the data lines D₀-D_m; and an output terminal connected to the LC capacitor C_LC1 or C_LC2, the storage capacitor C_ST1 or C_ST2, and the coupling capacitor Cpp.

[0050] The LC capacitor C_LC1 or C_LC2 is connected between the switching element Q1 or Q2 and a common voltage Vcom. The storage capacitor C_ST1 or C_ST2 is connected between the switching element Q1 or Q2 and the storage electrode line 131.

[0051] This pixel structure that a pixel includes two switching elements and two LC capacitors and adjacent pixels are capacitively coupled by a coupling capacitor prevents gray inversion at a bottom view and improves visibility at all directions.

[0052] Referring to FIG. 1 again, the driving voltage generator 700 generates a gate-on voltage V_on for turning on the switching elements Q1 and Q2 and a gate-off voltage V_off for turning off the switching elements Q1 and Q2.

[0053] The gray voltage generator 800 generates two sets of a plurality of gray voltages related to the transmittance of the pixels. The gray voltages in one set have a positive polarity with respect to the common voltage Vcom, while those in the other set have a negative polarity with respect to the common voltage Vcom.

[0054] The gate driver 400 often called a scanning driver is connected to the gate lines G₁-G_n of the panel assembly 300 and applies gate signals to the gate lines G₁-G_n, each gate signal being a combination of the gate-on voltage V_on and the gate off voltage V_off from the driving voltage generator 700.

[0055] The data driver 500 often called a source driver is connected to the data lines D₀-D_m of the panel assembly 300 and applies data voltages selected from the gray voltages from the gray voltage generator 800 to the data lines D₀-D_m.

[0056] The signal controller 600 controls the gate driver 400, the data driver 500, and the driving voltage generator 560.

[0057] Referring to FIG. 3, the signal generator 600, the driving voltage generator 700, and the gray voltage generator 800 are provided on printed circuit boards (PCBs) 450 and 550, and the gate driver 400 and the data driver 500 include a plurality of gate driving integrated circuits (“ICs”) 440 and a plurality of data driving ICs 541-543, respectively.

[0058] In detail, a gate PCB 450 is located at the left of the panel assembly 300 and connected to the panel assembly 300 via a plurality of gate flexible printed circuit films (FPC) 410. A data PCB 550 are located at the top of the panel assembly 300 and connected to the panel assembly 300 via a plurality of data FPC films 511-513. A gate driving IC 440 is mounted on each gate FPC film 410, while a data driving IC 541-543 is mounted on each data FPC film 511-513. An additional FPC film 412 is attached to the gate PCB 450 and the data PCB 550. The FPC film 412 includes a plurality of signal lines (not shown) for electrical connection between the gate PCB 450 and the data PCB 550.

[0059] A plurality of signal lines 521 connecting the output terminals of the data driving ICs 541-543 to the data lines D₀-D_m of the panel assembly 300 are formed on the data FPC films 511-513. The last terminal of the rightmost data driving IC 542 connected to the rightmost data line D_m is electrically connected to the leftmost data line called a dummy data line D₀ via a signal line 522a formed on the rightmost FPC film 512 mounting the rightmost driving IC 542, a signal line 522 formed on the data PCB 550, and a signal line 522b formed on the leftmost FPC film 511 mounting the leftmost data driving IC 541. An amplifier (not shown) such as an operational amplifier for compensating the voltage drop between the last terminal of the rightmost data driving IC 542 and the dummy data line D₀ due to the resistance of the signal line 522 may be provided at an end point or an intermediate point of the signal line 522 of the data PCB 550.

[0060] Unlike FIG. 3, the gate driver 400 and the data driver 500 may be mounted on the panel assembly 300, or may be formed on the panel assembly 300 by means of a process for forming the display signal lines G₁-G_m, D₀-D_m and 131. The gray voltage generator 800 may be partially provided in both the data PCB 550 and the data driving ICs 541-543.

[0061] If all pixels in one pixel column are connected to the same data line according to another embodiment of the present invention, the dummy data line D₀ and the signal lines 522, 522a and 522b are omitted.

[0062] Now, the operation of the LCD will be described in detail.

[0063] The signal controller 600 is supplied with RGB image signals R, G and B and input control signals controlling the display thereof such as a vertical synchronization signal V_sync, a horizontal synchronization signal H_sync, a main clock CLK, and a data enable signal DE, from an external graphic controller (not shown). After generating gate control signals CONT1 and data control signals CONT2 on the basis of the input control signals and processing the image signals R, G and B suitable for the operation of the panel assembly 300, the signal controller 600 provides the gate control signals CONT1 for the gate driver 400, and the processed image signals R′, G′and B′ and the data control signals CONT2 for the data driver 500.

[0064] The gate control signals CONT1 include a vertical synchronization start signal STV for informing of start of a frame, a gate clock signal CPV for controlling the output time of the gate-on voltage V_on, and an output enable signal OE for defining the width of the gate-on voltage V_on. The data control signals CONT2 include a horizontal synchronization start signal STH for informing of start of a horizontal period, a load signal LOAD or TP for instructing to apply the appropriate data voltages to the data lines D₀-D_m, an inversion control signal RVS for reversing the polarity of the data voltages (with respect to the common voltage Vcom) and a data clock signal HCLK.

[0065] The data driver 500 receives a packet of the image data R′, G′ and B′ for a pixel row from the signal controller 600 and converts the image data R′, G′ and B′ into the analogue data voltages selected from the gray voltages supplied from the gray voltage generator 800 in response to the data control signals CONT2 from the signal controller 600.

[0066] Responsive to the gate control signals CONT1 from the signals controller 600, the gate driver 400 applies the gate-on voltage V_on to the gate line G₁-G_n, thereby turning on the switching elements Q1 and Q2 connected thereto.

[0067] The data driver 500 applies the data voltages to the corresponding data lines D₀-D_m for a turn-on time of the switching elements Q1 and Q2 due to the application of the gate line G₁-G_n connected thereto (which is called “one horizontal period” or “1H” and equals to one periods of the horizontal synchronization signal H_sync, the data enable signal DE, and the gate clock signal CPV). Then, the data voltages in turn are supplied to the corresponding pixels via the turned-on switching elements Q1 and Q2.

[0068] The difference between the data voltage and the common voltage Vcom applied to a pixel is expressed as a charged voltage of the LC capacitor C_LC1 or C_LC2, i.e., a pixel voltage. The liquid crystal molecules have orientations depending on the magnitude of the pixel voltage and the orientations determine the polarization of light passing through the LC capacitor C_LC1 or C_LC2. Polarizers (indicated by reference numerals 11 and 21 in FIG. 11A) convert the light polarization into the light transmittance.

[0069] By repeating this procedure, all gate lines G₁-G_n are sequentially supplied with the gate-on voltage V_on n during a frame, thereby applying the data voltages to all pixels. When the next frame starts after finishing one frame, the inversion control signal RVS applied to the data driver 500 is controlled such that the polarity of the data voltages is reversed (which is called “frame inversion”). The inversion control signal RVS may be also controlled such that the polarity of the data voltages flowing in a data line in one frame are reversed (which is called “line inversion”), or the polarity of the data voltages in one packet are reversed (which is called “dot inversion”).

[0070] Next, a method of applying data voltages to an LC panel assembly according to an embodiment of the present invention will be described in detail with reference to FIGS. 4-6.

[0071] FIG. 4 shows the connections between pixels and data lines of an LC panel assembly according to an embodiment of the present invention, FIG. 5 is a diagram showing waveforms of data signals applied to adjacent data lines of an LC panel assembly by a data driver of an LCD according to an embodiment of the present invention, and FIG. 6 is a diagram showing waveforms of image signals supplied from a signal controller to a data driver of an LCD according to an embodiment of the present invention.

[0072] The pixels in a row of an LCD according to an embodiment of the present invention are connected to data lines on the same hand, while the pixels in adjacent two rows are connected to the data lines on the opposite hands. As shown in FIG. 4, the j-th pixels in odd rows are connected to the data lines D_j on the right hand, while the j-th pixels in even rows are connected to the data lines D_j−1 on the left hand.

[0073] The data voltages applied to adjacent two pixels in a row have opposite polarity, while the data voltages applied to adjacent two pixels in a column have the same polarity. For obtaining this polarity arrangement, two data signals d_j and d_j+1 applied to adjacent two data lines have opposite polarity, and each of the data signals d_j and d_j+1 reverses its polarity every row, as shown in FIG. 5.

[0074] FIG. 6 shows image data R′, G′ and B′ supplied for the data driver 500 from the signal controller 600. For the odd rows, the signal generator 600 sequentially supplies from the image data d₁₁,d₃₁, . . . for the first column to the image data d₁^m,d₃^m, . . . for the last column. For the even rows, however, since the pixels in the first column are connected to the dummy data line D₀, which in turn is connected to the last data line D_m, the signal generator 600 sequentially supplies from the image data d₂²,d₄², . . . for the second column to the image data d₂^m,d₄^m, . . . for the last column and then, finally supplies the image data d₂¹,d₄¹, . . . for the first column. For this purpose, the signal generator 600 temporarily stores the image data d₂¹,d₄¹, . . . for later output.

[0075] If the connections between pixels and data lines are opposite to those shown in FIG. 4, that is, the j-th pixels in odd rows are connected to the data lines D_j−1 on the left hand and the j-th pixels in even rows are connected to the data lines D_j on the right hand, the output sequence of the signal processor 600 for the image data R′, G′ and B′ is changed. In detail, for the odd rows, the signal. generator 600 sequentially supplies from the image data d₁²,d₃², . . . for the second column to the image data d₁^m,d₃^m, . . . for the last column and then, finally supplies the image data d₁¹,d₃¹, . . . for the first column, while for the even rows, the signal generator 600 sequentially supplies from the image data d₂¹,d₄¹, . . . for the first column to the image data d₂^m,d₄^m, . . . for the last column.

[0076] Then, the inversion type for the pixels in the panel assembly 300 is column inversion, while the inversion type for the data lines D₀-D_m is dot inversion.

[0077] If all the pixels in a column are connected to the same data line D₀-D_m according to another embodiment of the present invention, the polarity of adjacent pixels in a row is opposite. The polarity along the columns is subject to either the dot inversion (that adjacent pixels in a column have different polarity) or the column inversion (that adjacent pixels in a column have the same polarity).

[0078] The dot inversion controls the polarity of the data signals such that the data signals applied to two adjacent data lines are opposite and the data signals along a data line reverses their polarity whenever the application row is changed.

[0079] The column inversion controls the polarity of the data signals such that the data signals applied to two adjacent data lines are also opposite while the data signals along a data line have the same polarity.

[0080] In this case, it is not required for rearranging the sequence of the image data R′, G′ and B′. That is, for all the rows, the signal controller 600 sequentially outputs from the image data d₁¹, d₂¹, . . . for the first column to the image data d₁^m, d₂^m, . . . for the last column.

[0081] Compared with this another embodiment, the connections between pixels and data lines shown in FIG. 4 have advantages that the column inversion for the pixels of an LC panel assembly 300 particularly having a configuration that a pixel includes two switching elements and the pixels are capacitively coupled by coupling capacitors gives the brightness higher than the dot inversion to improve visibility and decrease flicker. In addition, since the dot inversion for the data lines is still remained, the polarity of the off-current of the switching elements connected to a data line is reversed to decrease the crosstalk.

[0082] Next, a method of applying data voltages to an LC panel assembly according to another embodiment of the present invention will be described in detail with reference to FIGS. 7-9.

[0083] FIG. 7 shows the connections between pixels and data lines of an LC panel assembly according to another embodiment of the present invention, FIG. 8 is a diagram showing waveforms of data signals applied to adjacent data lines of an LC panel assembly by a data driver of an LCD according to another embodiment of the present invention, and FIG. 9 is a diagram showing waveforms of image signals supplied from a signal controller to a data driver of an LCD according to another embodiment of the present invention.

[0084] The connections between pixels and data lines according to another embodiment of the present invention are different from those shown in FIG. 4 in that the connected data lines are reversed every two rows. That is, if the j-th pixels in previous two rows are connected to the data line D_j, then the j-th pixels in the next two rows are connected to the data line D_j−1. As shown in FIG. 7, the j-th pixels in the (4k+1)-th row (k=0, 1, . . . ) and the (4k+2)-th row are connected to the data lines D_j on the right hand, while the j-th pixels in the (4k+3)-th row and the (4k+4)-th row are connected to the data lines D_j−1 on the left hand.

[0085] As shown in FIG. 7, the polarity arrangement is the same as that shown in FIG. 4. That is, the data voltages applied to adjacent two pixels in a row have opposite polarity, while the data voltages applied to adjacent two pixels in a column have the same polarity. For obtaining this polarity arrangement, two data signals d_j and d_j+1 applied to adjacent two data lines have opposite polarity, and each of the data signals d_j and d_j+1 reverses its polarity every two rows, as shown in FIG. 8.

[0086] FIG. 9 shows image data R′, G′ and B′ supplied for the data driver 500 from the signal controller 600. For the (4k+1)-th and the (4k+2)-th rows, i.e., for the first row, the second row, the fifth row, the sixth row, and so on, the signal generator 600 sequentially supplies from the image data d₁¹,d₂¹, . . . for the first column to the image data d₁^m,d₂^m, . . . for the last column. For the (4k+3)-th and the (4k+4)-th rows, i.e., for the third row, the fourth row, the seventh row, the eighth row, and so on, however, the signal generator 600 sequentially supplies from the image data d₃²,d₄², . . . for the second column to the image data d₃^m,d₄^m, . . . for the last column and then, finally supplies the image data d₃¹,d₄¹, . . . for the first column. For this purpose, the signal generator 600 temporarily stores the image data d₂¹,d₄¹, . . . for later output.

[0087] If the connections between pixels and data lines are opposite to those shown in FIG. 7, that is, the j-th pixels in the (4k+1)-th and the (4k+2)-th rows are connected to the data lines D_j−1 on the left hand and the j-th pixels in the (4k+3)-th and the (4k+4)-th rows are connected to the data lines D_j on the right hand, the output sequence of the signal processor 600 for the image data R′, G′ and B′ is changed. In detail, for the (4k+1)-th and the (4k+2)-th rows, the signal generator 600 sequentially supplies from the image data d₁²,d₂², . . . for the second column to the image data d₁^m,d₂^m, . . . for the last column and then, finally supplies the image data d₁¹,d₂¹, . . . for the first column, while for the (4k+3)-th and the (4k+4)-th rows, the signal generator 600 sequentially supplies from the image data d₃¹,d₄¹, . . . for the first column to the image data d₃^m,d₄^m, . . . for the last column.

[0088] Then, the inversion type for the pixels in the panel assembly 300 is column inversion, while the inversion type for the data lines D₀-D_m is two-dot inversion.

[0089] The connections between pixels and data lines may be reversed at least every three rows.

[0090] Now, an LC panel assembly for an LCD according to an embodiment of the present invention is described in detail with reference to FIGS. 10 to 11C.

[0091] FIG. 10 is a layout view of an LC panel assembly according to an embodiment of the present invention, FIG. 11A is a sectional view of the LC panel assembly shown in FIG. 10 taken along the line XIB-XIB′, and FIG. 11B is a sectional view of a TFT array panel shown in FIG. 11A, which is a portion of the LC panel assembly shown in FIG. 11A except for a color filter array panel and polarization films. FIG. 11C is a sectional view of a TFT array panel shown in FIG. 10 taken along the line XIC-XIC′.

[0092] Referring to FIG. 11A, an LC panel assembly according to this embodiment includes a TFT array panel 100, a color filter array panel 200 facing the TFT array panel 100, and an LC layer 3 interposed therebetween.

[0093] Referring to FIGS. 10 to 11C, the TFT array panel 100 includes a plurality of gate lines 121 and a plurality of storage electrode lines 131 formed on an insulating substrate 110 preferable made of transparent glass. Each gate line 121 extends substantially in a row direction and includes a plurality of gate electrodes 124. The storage electrode lines 131 extend substantially in the row direction and are partially curved.

[0094] A gate insulating layer 140 is formed on the gate lines 121 and the storage electrode lines 131, and a plurality of semiconductor islands 154 is formed on the gate insulating layer 140 opposite the gate electrodes 124. Each semiconductor island 154 is preferably made of amorphous silicon (“a-Si”) and forms a channel of a TFT. A plurality of ohmic contacts 163, 165a and 165b preferably made of a-Si heavily doped with N type impurity such as phosphorous (P) are formed on the semiconductor islands 154.

[0095] A plurality of data lines 171, a plurality of pairs of drain electrodes 175a and 175b, and a plurality of coupling electrodes 177 are formed on the ohmic contacts 163, 165a and 165b and the gate insulating layer 140.

[0096] Each data line 171 extends substantially in a column direction and includes a plurality of source electrodes 173, and each source electrode 173 is located opposite a pair of drain electrodes 175a and 175b separated therefrom with respect to the gate electrode 124. The positions of the source electrodes 173 are altered between a left side and a right side every row, and thus the position of a given source electrode 173 has a nearly bilateral symmetry with the position of a source electrode in a previous row.

[0097] Each pair of drain electrodes 175a and 175b extends opposite directions with respect to the gate line 124.

[0098] Each coupling electrode 177 extends in the column direction across the storage electrode line 131.

[0099] The portions of the semiconductor islands 154 located between the source electrode 173 and the drain electrodes 175a and 175b are exposed, and the ohmic contacts 163, 165a and 165b are disposed only between the semiconductor islands 154 and the data lines 171 and the drain electrodes 175a and 175b.

[0100] A passivation layer 180 is formed on the data lines 171, the drain electrodes 175a and 175b, and the coupling electrodes 177. The passivation layer 180 has a plurality of contact holes 183a and 183b exposing end portions of the drain electrodes 175a and 175b and a plurality of contact holes 187 exposing end portions of the coupling electrodes 177. The passivation layer 180 further has a plurality of contact holes 182 exposing end portions 179 of the data lines 171, and the passivation layer 180 and the gate insulating layer 140 have a plurality of contact holes 181 exposing end portions 129 of the gate lines 121.

[0101] A plurality of pairs of pixel electrodes 190a and 190b and a plurality of contact assistants 91 and 92 are formed on the passivation layer 180. The pixel electrodes 190a and 190b and the contact assistants 91 and 92 are preferably made of a transparent conductive material such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) or a reflective material.

[0102] Each pair of pixel electrodes 190a and 190b includes a lower pixel electrode 190a and an upper pixel electrode 190b connected to the drain electrodes 175a and 175b through the contact holes 183a and 183b, respectively. The upper electrode 190b is connected to the coupling electrode 177 through the contact hole 187 and the lower electrode 190a overlaps the coupling electrode 177 such that the lower pixel electrode 190a of an upper pixel and the upper pixel electrode 190b of a lower pixel are capacitively coupled. In addition, the lower pixel electrode 190a of an upper pixel and the upper pixel electrode 190b of a lower pixel are located opposite across the storage electrodes line 131 and overlap the storage electrode line 131 to form a plurality of storage capacitors. The edges of the pixel electrodes 190a and 190b opposite across the storage electrode line 131 are curved to form V shapes, and the V-shaped edge of the pixel electrode 190a is convex, while that of the pixel electrode 190b is concave.

[0103] Each lower pixel electrode 190a has upper, lower and central linear cutouts 191-193. The central cutout 193 is located at the middle portion in the column direction and enters into the pixel electrode 190a from the left to the right, thereby partitioning the pixel electrode 190a into upper and lower partitions. The upper and the lower cutouts 191 and 192 obliquely extend in the upper and the lower partitions, respectively, and are located symmetrically with respect to the central cutout 193.

[0104] The contact assistants 91 and 92 are connected to the exposed end portions 129 and 179 of the gate lines 121 and the data lines 171 through the contact holes 181 and 182, respectively, and provided for protecting the exposed end portions 129 and 179 but is optional.

[0105] An alignment layer 11 is coated on the entire surface of the TFT array panel 100 except for the contact assistants 91 and 92.

[0106] One gate electrode 124, one source electrode 173, and a pair of drain electrodes 175a and 175b along with one semiconductor island 154 form a pair of TFTs respectively connected to the pixel electrodes 190a and 190b.

[0107] Referring to FIGS. 10 and 11B, the color filter array panel 200 includes a black matrix 220 formed on an insulating substrate 210 preferably made of transparent glass. The black matrix 220 defines a plurality of windows where a plurality of red, green and blue color filters 230 are formed. An overcoat is formed on the color filters and a common electrode 270 is formed thereon. The common electrode 270 is preferably made of a transparent conductive material such as ITO and IZO, and has a plurality of sets of four linear cutouts 271-274. Three 271-273 of the cutouts 271-274 overlap the lower pixel electrode 190a to partition the pixel electrode 190a along with the cutouts 191-193 into a plurality of subareas. The cutout 274 having a V shape overlap the upper electrode 190b to bisect the upper pixel electrode 190b into two subarea. An alignment layer 21 is coated on the entire surface of the color filter array panel 200.

[0108] Each subarea defined by the cutouts 191-193 and 271-273 has substantially a shape of a tetragon having two major edges making an angle of about 45 degrees with the gate lines 121 and the data lines 171. The subareas defined by edges of the upper pixel electrode 190b and the cutout 274 have V shapes, which are combinations of two tetragons.

[0109] A pair of polarizers 12 and 22 are attached to outer surfaces of the panels 100 and 200, respectively. The polarization axes of the polarizers 12 and 22 are crossed and substantially parallel to the gate lines 121 or the data lines 171.

[0110] The molecules of the LC layer 3 are aligned such that their major axes are substantially perpendicular to the surfaces of the panels 100 and 200 in absence of electric field.

[0111] Next, a method of manufacturing the TFT array panel shown in FIGS. 10 to 11C according to an embodiment of the present invention is described in detail with reference to FIGS. 12A to 15C as well as FIGS. 10 to 11C.

[0112] As shown in FIGS. 12A to 12C, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on a glass substrate 110.

[0113] As shown in FIGS. 13A to 13C, a SiNx gate insulating layer 140, a semiconductor layer preferably made of amorphous silicon, and a doped amorphous silicon layer are deposited and the doped amorphous silicon layer and the semiconductor layer are patterned to form a plurality of islands 164 and 154.

[0114] As shown in FIGS. 14A to 14C, after forming a plurality of data lines 171, a plurality of drain electrodes 175a and 175b, and a plurality of coupling electrodes 177, portions of the doped amorphous silicon islands 164, which are not covered with the data lines 171, the drain electrodes 175a and 175b, and the coupling electrodes 177, are removed to expose underlying portions of the semiconductor islands 154. In order to stabilize the exposed surface of the semiconductor layer 154, oxygen plasma treatment is preferably performed.

[0115] As shown in FIGS. 15A to 15C, a passivation layer 180 is formed by coating or deposition such as plasma-enhanced chemical vapor deposition (PECVD) of silicon nitride or a photosensitive organic material having good planarization characteristic on the substrate 110. The passivation layer 180 together with the gate insulating layer 140 is photo-etched to form a plurality of contact holes 183a-185 exposing the drain electrodes 175a and 175b, the coupling electrodes 177, end portions 129 and 179 of the gate lines 121 and the data lines 171, respectively.

[0116] Referring to FIGS. 10 to 11C, a transparent conductive material is deposited and photo-etched to form a plurality of pixel electrodes 190a and 190b and a plurality of contact assistants 91 and 92. The pixel electrodes 190a and 190b are connected to the drain electrodes 175a and 175b through the contact holes 183a and 183b and to the coupling electrodes 177 through the contact holes 187. The contact assistants 91 and 92 are connected to the exposed end portions 129 and 179 of the gate lines 121 and the data lines 171 through the contact holes 181 and 182, respectively.

[0117] Finally, an alignment layer 11 is coated on the entire surface of the TFT array panel 100 and, if necessary, subject to surface treatment.

[0118] Now, an LC panel assembly of an LCD according to another embodiment of the present invention is described in detail with reference to FIGS. 16 to 17B.

[0119] FIG. 16 is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention, and FIGS. 17A and 17B are sectional views of the TFT array panel shown in FIG. 16 taken along the lines XVIIA-XVIIA′ and XVIIB-XVIIB′, respectively.

[0120] An LCD according to this embodiment also includes a TFT array panel 100, a color filter panel 200, and an LC layer 3 interposed therebetween.

[0121] A TFT array panel 100 includes a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 preferably made of transparent glass. Each gate line 121 extends substantially in a row direction and includes a plurality of expansions forming gate electrodes 124. Each storage electrode line 131 extends substantially parallel to the gate lines and may include a plurality of branches.

[0122] A gate insulating layer 140 is formed on the gate lines 121 and the storage electrode lines 131. A plurality of semiconductor stripes and islands 151 and 157 preferably made of hydrogenated a-Si are formed on the gate insulating layer 140. Each semiconductor stripe 151 includes a plurality of pairs of portions 154a and 154b overlapping the gate electrodes 124 to form channels of TFTs. A plurality of ohmic contact stripes and islands 161, 165a, 165b and 167 preferably made of silicide or hydrogenated a-Si heavily doped with n type impurity such as P are formed on the semiconductor stripes and islands 151 and 157.

[0123] A plurality of data lines 171, a plurality of pairs of drain electrodes 175a and 175b, and a plurality of coupling electrodes 177 are formed on the ohmic contact stripes and islands 161, 165a, 165b and 167, respectively. Each data line 171 extends along the semiconductor stripe 151 and includes a plurality of source electrodes 173 extending therefrom and located on the gate lines 121. The-drain electrodes 175a and 175b are located opposite each other with respect to the source electrodes 173 and extend upward and downward from the gate electrodes 124.

[0124] Each coupling electrode 177 extends substantially in the row direction and partly overlaps the storage electrode line 131.

[0125] The ohmic contacts 163, 165a, 165b and 167 are disposed only between the semiconductor stripes and islands 151 and 154 and the data lines 171, the drain electrodes 175a and 175b and the coupling electrodes 177.

[0126] The data lines 171 and the drain electrodes 175a and 175b have substantially the same planar shape as the ohmic contact stripes and islands 161, 165a and 165b, and the semiconductor stripes 151 have substantially the same planar shape as the data lines 171 and the drain electrodes 175a and 175b except for channel portions 154a and 154b located between the data lines 171 and the drain electrodes 175a and 175b. The coupling electrodes 177 have substantially the same planar shape as the ohmic contact islands 167 and the semiconductor islands 157.

[0127] A passivation layer 180 preferably made of silicon nitride or organic insulator is formed on the data lines 171, the drain electrodes 175a and 175b and the coupling electrodes 177 and the channel portions 154a and 154b of the semiconductor stripes 151.

[0128] The passivation layer 180 is provided with a plurality of contact holes 183a, 183b and 187 respectively exposing end portions of the drain electrodes 175a and 175b and the coupling electrodes 177, and a plurality of contact holes 187 exposing end portions of the data lines 171. The gate insulating layer 140 and the passivation layer 180 are provided with a plurality of contact holes 183a exposing end portions of the. gate lines 121.

[0129] A plurality of pairs of pixel electrodes 190a and 190b and a plurality of contact assistants 91 and 92 are formed on the passivation layer 180. The pixel electrodes 190a and 190b and the contact assistants 91 and 92 are preferably made of a transparent conductive material such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) or a reflective material.

[0130] Each pair of pixel electrodes 190a and 190b includes a lower pixel electrode 190a and an upper pixel electrode 190b connected to the drain electrodes 175a and 175b through the contact holes 183a and 183b, respectively. The upper electrode 190b is connected to the coupling electrode 177 through the contact hole 187 and the lower electrode 190a overlaps the coupling electrode 177 such that the lower pixel electrode 190a of an upper pixel and the upper pixel electrode 190b of a lower pixel are capacitively coupled. In addition, the lower pixel electrode 190a of an upper pixel and the upper pixel electrode 190b of a lower pixel are located opposite across the storage electrodes line 131 and overlap the storage electrode line 131 to form a plurality of storage capacitors.

[0131] Each lower pixel electrode 190a has a linear cutout 191 extending in the row direction. Each lower pixel electrode 190 may further have at least one cutout extending in the row direction, and each upper pixel electrode may have at least one cutout extending in the column direction. It is preferable that an area occupied by the lower pixel electrode 190a have a value of about 30 to 70 percents of the total area of the lower and the upper pixel electrodes 190a and 190b.

[0132] The contact assistants 91 and 92 are connected to the end portions 129 and 179 of the gate lines 121 and the data lines 171 through the contact holes 181 and 182, respectively.

[0133] An alignment layer 11 is coated on the entire surface of the TFT array panel 100 except for the contact assistants 91 and 92.

[0134] The color filter array panel 200 according to this embodiment has a structure similar to that shown in FIG. 11A. That is, the color filter array panel 200 also includes a black matrix 220, a plurality of color filters 230, a common electrode 270 and an alignment layer 21. However, the common electrode 270 has a plurality of sets of cutouts 271-273 having shapes and positions different from those shown in FIGS. 10 and 11A. A set of cutouts include a longitudinal cutout 271 extending in the column direction and two transverse cutouts 272 and 273 extending in the row direction. The longitudinal cutout 271 bisects the upper pixel electrode 190b into two subareas arranged in the row direction, and the transverse cutouts 272 and 273 are located opposite across the cutout 191 of the lower pixel electrode 190a and quarter the lower pixel electrode 190a into four quarter subareas arranged in the column direction.

[0135] According to another embodiment of the present invention, the coupling electrodes 177 are formed of the same layer as the gate lines 121, and in this case, the coupling electrodes 177 should not be connected to the storage electrodes lines 131.

[0136] Now, a method of manufacturing the TFT array panel shown in FIGS. 16, 17A and 17B according to another embodiment of the present invention is described in detail with reference to FIGS. 18A to 20C as well as FIGS. 16, 17A and 17B.

[0137] FIGS. 18A to 20C are layout views and sectional views of the TFT array panel shown in FIGS. 16, 17A and 17B in intermediate steps of a manufacturing method thereof according to another embodiment of the present invention.

[0138] As shown in FIGS. 18A to 18C, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110.

[0139] A silicon nitride gate insulating layer 140 with thickness of about 1,500-5,000 Å, an intrinsic a-Si semiconductor layer 150 with thickness of about 500-2,000 Å, and a doped a-Si layer 160 with thickness of about 300-600 Å, and a metal layer 170 with thickness of about 1,500-3,000 Å are sequentially deposited by CVD and sputtering, and a photoresist film with thickness of about 1-2 microns is coated thereon. Thereafter, the photoresist film is exposed to light through a photo mask (not shown) and is developed as shown in FIGS. 19B and 19C.

[0140] The photoresist film has position-dependent thickness and, for example, includes first to third portions having thickness decreasing in sequence. In FIGS. 19B and 19C, the first and the second portions are indicated by reference numerals 212 and 214, while there is no numeral indicating the third portions since the third portions are shown to have zero thickness and to expose the underlying metal layer 170. The ratio of the thickness of the photoresist film 212 and 214 is adjusted depending on process conditions of subsequent process steps, and it is preferable that the thickness of the second portion is equal to or less than a half of that of the first portion, for example, equal to or less than 4,000 Å.

[0141] The position-dependent thickness of the photoresist film is obtained by several techniques, for example, by providing semi-transparent areas on the exposure mask as well as transparent areas and opaque areas. The semi-transparent areas alternatively have a slit pattern, a lattice pattern, a thin film(s) with intermediate transmittance or intermediate thickness. When using a slit pattern, it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of a light exposer used for the photolithography. Another example is to use reflowable photoresist. That is, once a photoresist pattern made of a reflowable material is formed by using a normal exposure mask only with transparent areas and opaque areas, it is subject to reflow process to flow onto areas without the photoresist, thereby forming thin portions.

[0142] The different thickness of the photoresist film 212 and 214 enables to selectively etch the underlying layers when using suitable process conditions.

[0143] A plurality of data lines 171, a plurality of drain electrodes 175a and 175b and a plurality of coupling electrodes 177 as well as a plurality of ohmic contact stripes and islands 161, 165a, 165b and 167 and a plurality of semiconductor stripes and islands 151 and 157 are obtained by a series of etching steps.

[0144] An exemplary sequence is shown in FIGS. 19D to 19I:

[0145] (1) Removal of portions of the metal layer 170, the doped a-Si layer 160 and the semidconductor layer 150 under the third portion of the photoresist film (FIGS. 19D to 19G);

[0146] (2) Removal of the second portion 214 of the photoresist film (FIGS. 19F and 19G;

[0147] (3) Removal of portions of the metal layer 170 and the doped a-Si layer 160 under the second portion 214 of the photoresist film (FIGS. 19H and 19I); and

[0148] (4) Removal of the first portion 212 of the photoresist film.

[0149] Another exemplary sequence is as follows:

[0150] (1) Removal of portions of the metal layer 170 under the third portion of the photoresist film;

[0151] (2) Removal of the second portion 214 of the photoresist film;

[0152] (3) Removal of portions of the doped a-Si layer 160 and the semiconductor layer 150 under the third portion of the photoresist film;

[0153] (4) Removal of portions of the metal layer 170 under the second portion 214 of the photoresist film;

[0154] (5) Removal of the first portion 212 of the photoresist film; and

[0155] (6) Removal of the doped a-Si layer 160 under the second portion 214 of the photoresist film.

[0156] Although the removal of the second portion 214 of the photoresist film causes the thickness reduction of the first portion 212 of the photoresist film, it does not remove the first portion 212, which protects the underlying layers from removal or etching, since the thickness of the second portion 214 is smaller than the first portion 212.

[0157] By selecting an appropriate etching condition, the second portion 214 of the photoresist film and the portions of the doped a-Si layer 160 and the semiconductor layer 150 under the third portion of the photoresist film are simultaneously removed. Similarly, the removal of the first portion 212 of the photoresist film and the removal of the portions of the doped a-Si layer 160 under the second portion 214 of the photoresist film are simultaneously performed. For instance, the etched thicknesses of the photoresist film and the semiconductor layer 150 (or the doped a-Si layer 160) are nearly the same when using a gas mixture of SF₆ and HCl, or a gas mixture of SF₆ and O₂.

[0158] Photoresist remnants left on the surface of the metal layer 170, if any, are removed by ashing.

[0159] Examples of etching gases used for etching the doped a-Si layer 160 in the step (3) of the first example and in the step (4) of the second example are a gas mixture of CF₄ and HCl and a gas mixture of CF₄ and O₂. Use of the gas mixture of CF₄ and O₂ enables to obtain uniform thickness of etched portions of the semiconductor layer 150.

[0160] As shown in FIGS. 20A to 20C, a passivation layer 180 is formed, and the passivation layer 180 together with the gate insulating layer 140 is photo-etched to form a plurality of contact holes 181, 182, 183a, 183b and 187 exposing end portions of the gate lines 121, end portions of the data lines 171, the drain electrodes 175a and 175b, and the coupling electrodes 177, respectively.

[0161] Finally, an ITO layer or an IZO layer with thickness of about 500-1,000 Å is deposited and photo-etched to form a plurality of pairs of pixel electrodes 190a and 190b connected to the drain electrodes 175a and 175b and the coupling electrodes 177 through the contact holes 183a, 183b and 187, respectively, and a plurality of contact assistants 91 and 92 connected to the exposed end portions of the gate lines 121 and of the data lines 171 through the contact holes 181 and 182, respectively.

[0162] Although preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the present art will still fall within the spirit and scope of the present invention, as defined in the appended claims.