Method and apparatus for a symmetrical odd-number clock divider

[0001] The present invention relates generally to clock divider circuits and, more particularly, to clock divider circuits producing a symmetrical waveform that divides the original clock frequency by an odd number.

[0002] A clock divider circuit is an integral component of radio frequency integrated circuits and microwave circuits, often as part of a phase-locked loop circuit. A circuit designer may need to divide a clock frequency by either an even number or an odd number. An even-number clock divider circuit may be implemented with a T-type flip-flop or other simple circuit. But, implementation of an odd-number clock divider circuit generally requires a more complex circuit.

[0003] Some odd-number clock dividers produce an asymmetrical clock signal—i.e., they have a duty cycle other than fifty percent (50%). Furthermore, the design of a clock divider circuit for division by one odd number may often not be easily generated to a design for a different odd number.

[0004] Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; “each” means every one of at least a subset of the identified items; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future, uses of such defined words and phrases.

[0014] FIGS. 1-8, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged operational amplifier.

[0015] A method is disclosed that permits implementation of an odd-number clock divider circuit having a symmetrical output waveform. The method may be employed to implement a clock divider circuit dividing an input clock signal by any desired odd number.

[0016] FIG. 1 illustrates a state diagram 100 for a finite state machine (FSM). The FSM has output 1 while in state One1 for one clock cycle and output 0 while in states Zero 1 and Zero2 for two clock cycles. This series of states repeats every three clock cycles. The FSM may also be described by the following state table:

[0017]

TABLE 1
Current State	Next State	Output
(Q0, Q1)	(D0, D1)	(OUT)
	One1	(0 1)	Zero1	(1 0)	1
	Zero1	(1 0)	Zero2	(0 0)	0
	Zero2	(0 0)	One1	(0 1)	0

and the following logic statements:
D₀=Q₁  (1)
D₁=˜(Q₀+Q₁)  (2)
OUT=Q₁  (3)
where “˜” is the NOT operator and “+” is the OR operator.

[0018] While the output states are denominated in FIG. 1 and the state table as one and zero, it will be understood that they may also be referred to as true and false or high and low. In a circuit embodying such an FSM, the two states may represent any pair of output voltages, for example +5 volts and 0 volts in a “positive logic” circuit or −5 volts and 0 volts in a “negative logic” circuit.

[0019] An exemplary circuit embodying an FSM described by the state diagram of FIG. 1 is depicted in FIG. 2. Asymmetrical clock divider circuit 200 comprises D-type flip-flops 202 and 206, and a NOR gate 204. Following assertion of a reset line RESET, electrically coupled to the reset inputs R of the D-type flip-flops 202 and 206, non-inverting outputs Q of the flip-flops 202 and 206 are false. A data input D of the flip-flop 202 and an input of the NOR gate 204 are electrically coupled to the output Q of the flip-flop 206. Another input of the NOR gate 204 is electrically coupled to the output Q of the flip-flop 202. Because both inputs of the NOR gate 204 are false, an output of the NOR gate 204 is true, which is electrically coupled to a data input D of the flip-flop 206.

[0020] On the first rising edge of a clock line CK, electrically coupled to the clock inputs C of the flip-flops 202 and 206, the true level at the output D of the flip-flop 206 is clocked through to the output Q of the flip-flip 206. The rising edge also clocks the false level at the input D of the flip-flop 202 through to its output Q. The true level at the output Q of the flip-flop 206 causes the output of the NOR gate 204 to go low, which is applied to the data input D of the flip-flop 206.

[0021] The second rising edge of the clock line CK clocks the true level from the data input D of the flip-flop 202 through to its output Q. The rising edge also clocks the false level at the output of the NOR gate 204 through to the output Q of the flip-flop 206. The output of the NOR gate 204 remains false because of the true level at the output Q of the flip-flop 202.

[0022] The third rising edge of the clock line CK clocks the false level at the input D of the flip-flop 202 through to its output. The rising edge also clocks the false level at the output of the NOR gate 204 through to the output Q of the flip-flop 206. Both the inputs to the NOR gate 204 are again false, and the circuit has returned to the state it was in after the assertion of the reset line RESET.

[0023] The output Q of the flip-flop 206 is true for one clock cycle and false for the two succeeding clock cycles and repeats these states every three clock cycles.

[0024] FIG. 3 depicts a timing diagram of the two exemplary embodiments of the present invention shown in FIGS. 4 and 5. Trace 302 shows a reset line RESET asserted to reset a clock divider circuit. In this embodiment, the circuit is used to divide input clock signal CK, shown in trace 304, by 3. Trace 306 shows the signal PCK of a circuit such as that shown in FIG. 2, which is true for one clock cycle and false for two clock cycles. Trace 308 is a similar signal NCK, delayed from the signal PCK by one half-cycle of input clock signal CK. An output divided clock signal CLK, seen in trace 310, is a combination of the signals PCK and NCK. The divided clock signal CLK has a period three times the period of input clock signal CK and a symmetrical duty cycle.

[0025] A schematic electrical diagram for one exemplary circuit embodying the present invention is shown in FIG. 4. A clock divider circuit 400 comprises FSMs 402 and 404 and a signal combiner 406, in this embodiment, an OR gate. The FSM 402 is the same asymmetrical clock divider circuit shown in FIG. 2, and produces the signal PCK shown in the timing diagram in FIG. 3.

[0026] The FSM 404 is a similar asymmetrical clock divider circuit, with the difference being that flip-flops 408 and 410 have inverting clock inputs. As a result the FSM 404 is clocked by an inverted input clock signal CK, causing it to exhibit the same sequence of states as the FSM 402 delayed by one half-cycle of the input clock signal CK. Thus, the FSM 404 produces the signal NCK shown in FIG. 3. The OR gate 406 combines the signals PCK and NCK of the asymmetrical clock divider circuits 402 and 404 to produce divided clock signal CLK, which has a period three times that of input clock signal CK and a frequency one-third that of input clock signal CK.

[0027] Thus, a symmetrical clock divider circuit according to the present invention may be formed from two asymmetrical clock dividers, as shown in FIG. 4. Such a circuit may divide a symmetrical input clock signal having a period P_C into a symmetrical divided clock signal having a period N*P_C, where N is an odd integer (N=3 in the circuit of FIG. 4). A first of the two clock dividers goes true to begin a divided clock cycle and remains true for some portion of the first half-cycle of the divided clock signal. The second of the two clock dividers goes true while the first clock divider is still true and remains true until the end of the half-cycle. Both clock dividers remain false through the second half-cycle of the divided clock signal until the first divider goes true again at the beginning of the next divided clock cycle.

[0028] Another circuit embodying the present invention is depicted in FIG. 5. In this circuit, a clock divider circuit 500 comprises an FSM 502, a delay circuit 504, and a signal combiner 506. The FSM 502 is, again, the same asymmetrical clock divider circuit shown in FIG. 2. Delay circuit 504 comprises a single D-type flip-flop 508, having its data input D electrically connected to the output PCK of FSM 502. Because the flip-flop 508 has an inverting clock input, electrically coupled to the input clock signal CK, the signal PCK appears at its non-inverting output Q delayed by one half-cycle of the input clock signal CK. Thus, the output of the delay circuit 504 is the signal NCK. The OR gate 506 combines the signals PCK and NCK to produce divided clock signal CLK.

[0029] As such, a symmetrical clock divider circuit according to the present invention may also be formed from an asymmetrical clock divider and a delay circuit, as shown in FIG. 5. The asymmetrical clock divider goes true to begin a divided clock cycle and remains true until one half-cycle of the input clock signal before the end of the first half-cycle of the divided clock signal. The delay circuit delays the output of the asymmetrical clock divider by one half-cycle of the input clock signal.

[0030] Exemplary embodiments of the present invention that divide an input clock signal by 13 are shown in FIGS. 6-8. FIG. 6 depicts a state diagram 600 of an FSM suitable for such an embodiment. The FSM has output 1 while in states One1 through One6 and output 0 while in states Zero 1 through Zero7. The FSM makes a transition from one state to the next on each clock cycle. Thus, the FSM is an asymmetrical clock divider, dividing its input clock signal by 13.

[0031] The FSM may also be described by the following state table:

[0032]

TABLE 2
Current State	Next State	Output
(Q3, Q2, Q1, Q0)	(D3, D2, D1, D0)	(PCK)
	One1	(0 0 0 0)	One2	(0 0 0 1)	1
	One2	(0 0 0 1)	One3	(0 0 1 0)	1
	One3	(0 0 1 0)	One4	(0 0 1 1)	1
	One4	(0 0 1 1)	One5	(0 1 0 0)	1
	One5	(0 1 0 0)	One6	(0 1 0 1)	1
	One6	(0 1 0 1)	Zero1	(0 1 1 0)	1
	Zero1	(0 1 1 0)	Zero2	(0 1 1 1)	0
	Zero2	(0 1 1 1)	Zero3	(1 0 0 0)	0
	Zero3	(1 0 0 0)	Zero4	(1 0 0 1)	0
	Zero4	(1 0 0 1)	Zero5	(1 0 1 0)	0
	Zero5	(1 0 1 0)	Zero6	(1 0 1 1)	0
	Zero6	(1 0 1 1)	Zero7	(1 1 0 0)	0
	Zero7	(1 1 0 0)	One1	(0 0 0 0)	0

and the following logic statements:
D₃=Q₃·˜Q₂+Q₂·Q₁·Q₀  (4)
D₂=˜Q₃·Q₂˜Q₁+(Q₂^Q₀)·Q₁  (5)
D₁=Q₁^Q₀  (6)
D₀=(˜Q₃+˜Q₂)·˜Q₀  (7)
PCK=˜Q₃·(˜Q₂+˜Q₁)  (8)
where “·” is the AND operator, “˜” is the NOT operator, “+” is the OR operator, and “^” is the XOR operator.

[0033] FIG. 7 shows a symmetrical divide-by-thirteen clock divider 700 according to the present invention, comprising an asymmetrical divide-by-thirteen clock divider 702, a delay circuit 704, and a signal combiner 706. Similar to the operation of the symmetrical divide-by-three clock divider shown in FIG. 5, an output PCK of the clock divider 702 goes true for 6 cycles of input clock signal CK. The signal NCK at the output of the delay circuit 704 is the signal PCK, delayed by one half-cycle of the input clock signal CK. The OR gate 706 combines the signals PCK and NCK to form divided clock signal CLK, which has a symmetric waveform and a period 13 times longer than input clock signal CK.

[0034] Timing diagrams for several embodiments of the present invention are illustrated in FIG. 8. With reference to the embodiment shown in FIG. 7, the input clock signal CK is shown in trace 802 and the divided clock signal CLK in trace 804. Trace 806 depicts the signal PCK and the solid line in trace 808 depicts the signal NCK.

[0035] The dotted lines in trace 808 illustrate alternative embodiments that may be formed using the two FSMs 402 and 404, as discussed with regard to FIG. 4. The FSM 402 may be designed with output signal 806. The FSM 404 may then be designed with output signal as shown by the solid line in trace 808. Alternatively, the FSM 404 may be designed to go true at any of half-cycle edges 810 through 818 and stay true until half-cycle edge 819. The combination of asymmetrical clock divider waveform 806 and any of the alternative waveforms 808 produces symmetrical divided clock signal waveform 804.

[0036] In another alternative embodiment, the FSM 820 may be an asymmetric clock divider with the output waveform shown in trace 820. Such a circuit is true for 3 cycles and false for 10 cycles of input clock signal 802. Trace 822 shows three alternative waveforms for the FSM 404. The solid line illustrates a signal that goes true 2½ input clock cycles after the FSM 402 and remains true for 4 clock cycles. Dashed lines 824 and 826 represent signals that go true 1½ and ½ input clock cycles, respectively, after the FSM 402 and remain true for 5 and 6 clock cycles, respectively.

[0037] In the limiting case shown in traces 828 and 830, the FSM 402 is designed to be true for one input clock cycle and false for 12 cycles. Correspondingly, the FSM 404 goes true on the first half-cycle and remains true for 6 full cycles. The combination of any of the pairs of waveforms (806/808, 820/822, or 828/830) produces the symmetrical waveform of trace 804.

[0038] Thus, as discussed with regard to FIG. 4, a symmetrical clock divider circuit according to the present invention may from two asymmetrical clock dividers. A first of the two clock dividers goes true to begin a divided clock cycle and remains true for some portion of the first half-cycle of the divided clock signal. The second of the two clock dividers goes true while the first clock divider is still true and remains true until the end of the half-cycle. Both clock dividers remain false through the second half-cycle of the divided clock signal until the first divider goes true again at the beginning of the next divided clock cycle.

[0039] Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.