Multi-mode ADC and its application to CMOS image sensors

1. An analog-to-digital converter (ADC) apparatus for analog source signals of one polarity, comprising one comparator (111) consisting of transistors T2, T3, T4, T5 and T6, pass transistors T1 & T10, a block of digitally addressable voltage sources (113) to set the reference voltage (Vref) of the comparator (111), asynchronous n-bit digital counter (114), a block of digitally addressable voltage sources (115) to set the potential to be applied to the signal source, a digital control unit (116), a block (117) storing the calibration data for the input capacitor (Cref) of the comparator (111), and a base-2 multiplier block (118), being interconnected by the following branches or lines: line (121) connecting the input analog signal (source signal) to the drain of pass transistor T1, line (124) connecting the source of T1 to the source of T3, and to the block of voltage sources (115) to be connected to the signal source, line (123) connecting the digital control unit (116) to the gates of T1, T2, T3, T4, T7, and drain of T10, line (122) carrying the signal Vref from the block of digitally addressed voltage sources (113) to the source of transistor T2 of the comparator (111), line (126) connecting the digital control unit (116) to the gate of T10, line (125) connecting the output of the comparator (111) to the digital control unit (116) and the source of T10, group of lines (127) connecting the digital control unit (116) to the gates of the pass transistors in block of digitally addressable voltage sources (115) to set the potential to be applied to the signal source, group of lines (132) connecting the digital control unit (116) to the gates of the pass transistors in the block of digitally addressable voltage sources (113) to set the signal Vref for the source of transistor T2 inside the comparator (111), one or several lines (133) connect the output of the asynchronous n-bit digital counter (114) to the digital control unit (116), line (134) connecting the digital control unit (116) to the asynchronous n-bit digital counter (114), to provide a “Reset” signal, line (135) connecting the digital control unit (116) to the asynchronous n-bit digital counter (114), to provide an “Enable” signal, line (136) connecting the digital control unit (116) to the input of the asynchronous n-bit digital counter (114), to provide said input with either the output signal (125) of the comparator (111), or an oscillating signal, such as that provided by a “ring oscillator” (137), one or several lines (128) connecting the digital control unit (116) to the block (117) storing the calibration data for the input capacitor (Cref) of the comparator (111), one or several lines (129) connect the digital control unit to the (116) to the base-2 multiplier (118), one or several lines (130) connecting the block (117) storing the calibration data for the capacitor Cref, to the base-2 multiplier (118), group of lines (131) providing access to the output of the base-2 multiplier (118), that is, to the binary value corresponding to the analog input signal.

2. An analog-to-digital converter (ADC) apparatus for analog source signals of both polarities, comprising two comparators (111+ & 111−), consisting of transistors T2+, T3+, T4+, T5+ and T6+ and transistors T2−, T3−, T4−, T5− and T6−, respectively, four pass transistors (T1−, T1−, T10+ & T10−), two blocks of digitally addressable voltage sources 113+ & 113− to set the reference voltages Vref+ & Vref− respectively of the comparators 111+ & 111−, two asynchronous n-bit digital counters (114+ & 114−), two blocks of digitally addressable voltage sources (115+ & 115−) to set the potential to be applied to the signal source, a digital control unit (116), two blocks (117+ & 117−) storing the calibration data for the input capacitors Cref+ & Cref− respectively of the comparators (111+ & 111−), and two base-2 multiplier blocks (118+ & 118−), being interconnected by the following branches or lines: line 121+ (121) connecting the source signal to the drain of pass transistor T1+ (T1−), line 124+ (124−) connecting the source of T1+ (T1−) to the source of T3+ (T3−), and to the block of voltage sources 115+ (115−) to be connected to the signal source, line 123+ (123−) connecting the digital control unit 116 to the gates of T1+ (T1−), T2+ (T2−), T3+ (T3−), T4+ (T4−), T7+ (T7−), and drain of T10+ (T10−), line 122+ (122−) carrying the signal Vref+ (Vref−) from the block of digitally addressed voltage sources 113+ (113−) to the source of transistor T2+ (T2−) of the comparator 111+ (111−), line 126+ (126−) connecting the digital control unit 116+ (116−) to the gate of T10+ (T10−); line 125+ (125−) connects the output of the comparator 111+ (111−) to the digital control unit (116) and the source of T10+ (T10−), group of lines 127+ (127−) connecting the digital control unit 116 to the gates of the pass transistors in block of digitally addressable voltage sources 115+ (115−) to set the potential to be applied to the signal source, group of lines 132+ (132−) connecting the digital control unit 116 to the gates of the pass transistors in the block of digitally addressable voltage sources 113+ (113−) to set the signal Vref+ (Vref−) for the source of transistor T2+ (T2−) inside the comparator 111+ (111−), one or several lines 133+ (133−) connecting the output of the asynchronous n-bit digital counter 114+ (114−) to the digital control unit 116, line 134+ (134−) connecting the digital control unit 116 to the asynchronous n-bit digital counter 114+ (114−), to provide a “Reset” signal, line 135+ (135−) connecting the digital control unit 116 to the asynchronous n-bit digital counter 114+ (114−), to provide an “Enable” signal, line 136+ (136−) connecting the digital control unit 116 to the input of the asynchronous n-bit digital counter 114+ (114−), to provide said input with either the output signal 125+ (125−) of the comparator 111+ (111−), or an oscillating signal, such as that provided by a “ring oscillator” (137), one or several lines 128+ (128−) connecting the digital control unit 116 to the block 117+ (117−) storing the calibration data for the input capacitor Cref+ (Cref−) of the comparator 111+ (111−), one or several lines 129+ (129−) connecting the digital control unit to the 116 to the base-2 multiplier 118+ (118−), one or several lines 130+ (130−) connecting the block 117+ (117−) storing the calibration data for the capacitor Cref+ (Cref−), to the base-2 multiplier 118+ (118−), one or several output lines 131 providing the unified binary data stream, combining the binary streams generated by blocks 118+ & 118−.

3. The analog-to-digital converter (ADC) apparatus of claim 1 minus blocks 117 and 118, in which said block 118 may be interfaced with several ADCs operating in parallel, and in which said block 117 may be part of a table or array of such blocks from several ADCs operating in parallel.

4. The analog-to-digital converter (ADC) apparatus of claim 2 minus blocks 117+ & 117−, and 118+ and 118−, in which said blocks 118+ & 118− may be interfaced with several ADCs operating in parallel, and in which said blocks 117+ & 117− may be part of a table or array of such blocks from several ADCs operating in parallel.

5. Method of analog to digital conversion using the ADC of claim 1, operating in a “charge-to-frequency” or “charge-subtraction” mode, in which the input capacitor Cref of the comparator (111) is used to subtract a set of charges from the signal source, and the asynchronous n-bit digital counter (114) records how many sets of charges are subtracted, the method comprising the following steps A through I:

6. Method of analog to digital conversion using the ADC of claim 1, operating in a “voltage-to-time” or “voltage extrapolation” mode, in which the input capacitor Cref of the comparator (111) is exposed to the source signal, and from its partial charging an extrapolation is made about the actual value of the source signal, the method comprising the following steps A through N:

7. Method of analog to digital conversion using the ADC of claim 1, in which the mode of operation can be software-configured in real-time.

8. An image sensing system in which the ADC of claim 3 is used as column circuitry (“Column ADC”) 143 and 144 of a CMOS image sensor comprising a matrix of avalanche pixels 140, each comprising one avalanche photo-diode (APD) and one Row-Select Transistor (RST), a matrix controller (141) as well as a logic unit comprising a run length encoder (142), table (145) with Cref calibration data for ADCs of blocks 143 & 144, one or more base-2 multiplier (146), a timing table (147) for 3D imaging, and a number n of bit planes (148a to 148n), to be used in the Sub-Frame method of image formation.

9. Method for image acquisition and readout using the imaging sensing system of claim 8, in which analog to digital conversion is used to readout the light intensity signal from each pixel, when the pixel matrix is operated in a “Global Shutter” mode, comprising the following steps A through F, grouped into “signal acquisition” and “readout process”, which are repeated until all rows have been selected and all pixels have interacted with the ADC:

10. Method for image acquisition and readout using the imaging sensing system of the claim 8, in which digital conversion is used to readout the light intensity signal from each pixel, when the pixel matrix is operated in a “Rolling Shutter” mode, comprising the following steps A through H, repeated until all rows have been selected

11. Method for image acquisition and readout using the imaging sensing system of claim 8, in which analog to digital conversion is used to readout the timed edge/pulse signal from each pixel, when the pixel matrix is operated in a “Rolling Shutter” mode, comprising the following steps A through E, repeated until all rows have been selected:

12. Method for image acquisition and readout using the imaging sensing system of claim 8, in which analog to digital conversion is used to readout the signal from each pixel, simultaneously while the entire pixel matrix absorbing light, thereby having the entire imaging system operating in a “Shutter-less” mode, comprising the following steps A through F:

13. Method of image formation, the “Full-Frame” method of “Sequence A”, utilizing the image sensing system of claim 8 of the present invention, and comprising the following steps A through X, grouped into 2 principal phases and 4 main operations:

14. Method of image formation, a “Full-Frame” method of“Sequence B”, utilizing the image sensing system of claim 8, grouped into 3 principal phases and 4 main operations:

15. Method of image formation, comprising the following steps A through ZA, grouped into 4 principal phases and 4 mains operations:

16. Method of image formation, comprising the following steps A through G, grouped into 2 principal phases: