Symmetrical inductor

[0001] 1. Field of the Invention

[0002] The invention relates to semiconductor devices and in particular to a symmetrical inductor in differential operation.

[0003] 2. Description of the Related Art

[0004] Many digital and analog elements and circuits have been successfully applied to semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit includes a silicon substrate. One or more dielectric layers are disposed on the substrate, and one or more metal layers are disposed in the dielectric layers. The metal layers may be employed to form on-chip elements, such as on-chip inductors, by current semiconductor technologies.

[0005] Conventionally, the on-chip inductor is formed over a semiconductor substrate and employed in integrated circuits designed for radio frequency (RF) band. FIG. 1 is a plane view of a conventional on-chip inductor with a planar spiral configuration. The on-chip inductor is formed in an insulating layer 104 on a substrate 100, comprising a spiral conductive trace 103 and an interconnect structure. The spiral conductive trace 103 is embedded in the insulating layer 104. The interconnect structure includes conductive plugs 105 and 109, a conductive trace 107 embedded in an underlying insulating layer (not shown), and a conductive trace 111 embedded in the insulating layer 104. An internal circuit of the chip or an external circuit may provides a current passing through the coil, which includes the spiral conductive trace 103, the conductive plugs 105 and 109, and the conductive traces 107 and 111, and utilize the inductance induced by the coil.

[0006] A principle advantage of the planar spiral inductor is increased circuit integration due to fewer circuit elements located off the chip along with attendant need for complex interconnections. Moreover, the planar spiral inductor can reduce parasitic capacitance induced by the bond pads or bond wires between on-chip and off-chip circuits.

[0007] The planar spiral inductor, however, occupies a larger area of the chip and has lower quality factor (i.e. Q value). To reduce chip area and improve Q value, thickness of the spiral conductive trace 103 is increased, and trace line space S between the inner and outer coils is reduced.

[0008] However, wireless communication chip designs more frequently employ differential circuits to reduce common mode noise, with inductors applied therein symmetrically. The symmetrical application results in the inductor having the same structure from any end. The planar spiral inductor shown in FIG. 1 is not symmetrical, and, if applied in a differential circuit, will not suitably prevent common mode noise.

[0009] A detailed description is given in the following embodiments with reference to the accompanying drawings.

[0010] An inductor is provided. An embodiment of an inductor comprises first and second winding portions symmetrically arranged in an insulating layer on a substrate. Each winding portion comprises first, second and third semicircular conductive traces arranged in concentricity from the inside to the outside. Each semicircular conductive trace has first and second ends. And the first ends of the first semicircular conductive traces of the first and second winding portions are coupled to each other. A coupling portion comprises a first pair of connection layers, that cross connects the first ends of the second and third semicircular conductive traces of both winding portions, and a second pair of connection layers, that cross connects the second ends of the first and second semicircular conductive traces of both winding portions. The adjacent semicircular conductive traces of each winding portion have a trace line space therebetween and the outer trace line space is wider than the inner trace line space.

[0011] A symmetrical inductor is provided. An embodiment of an inductor comprises a plurality of semicircular conductive traces disposed in an insulating layer and arranged in concentricity. Each semicircular conductive trace has a first end and a second end, wherein the first ends of the two inmost semicircular conductive traces are coupled to each other. At least one first pair of connection layers is connected to the first ends of the semicircular conductive traces and at least one second pair of connection layers is connected to the second ends of the semicircular conductive traces. The adjacent semicircular conductive traces have a trace line space therebetween and the relatively outer trace line space is wider than the relatively inner trace line space.

[0012] A symmetrical inductor is provided. An embodiment of an inductor comprises a first winding portion and a second winding portion all disposed in an insulating layer, comprising a plurality of conductive traces, respectively. The second winding portion is symmetrically arranged with the first winding portion. At least two semicircular conductive traces are disposed in the insulating layer and outside the first or second winding portion. The semicircular conductive traces are electrically connected to the first and second winding portions, respectively. The semicircular conductive trace and the adjacent first or second winding portion have a trace line space therebetween, wider than a line space between the adjacent conductive traces in each winding portion.

[0019] The following description is of the best-contemplated modes of carrying out the invention. This description is provided for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. The symmetrical inductor of the invention will be described in the following with reference to the accompanying drawings.

[0020] FIG. 2 is a plane view of a three-turn symmetrical inductor of an embodiment of the invention. The symmetrical inductor comprises an insulating layer 210 disposed on a substrate 200. The substrate 200 may be a silicon substrate or other known semiconductor substrates. The substrate 200 may include various elements, such as transistors, resistors, or other well-known semiconductor elements. Moreover, the substrate 200 may also include other conductive layers (e.g. copper, aluminum, or alloy thereof) and insulating layers (e.g. silicon oxide, silicon nitride, or low-k dielectric material). Hereinafter, to simplify the diagram, only a flat substrate is depicted. Additionally, the insulating layer 210 may be a single low-k dielectric layer or multi-layer dielectrics. In this embodiment, the insulating layer 210 may include silicon oxide, silicon nitride, or low-k dielectric material.

[0021] The first winding portion is disposed in the insulating layer 210 and located at a first side of dashed line 2. The first winding portion may comprise a first semicircular conductive trace 201, a second semicircular conductive trace 203 and a third semicircular conductive trace 205 arranged in concentricity from inside to outside. The second winding portion is disposed in the insulating layer 210 and located at a second side opposite to the first side of dashed line 2. The second winding portion may comprise a first semicircular conductive trace 202, a second semicircular conductive trace 204 and a third semicircular conductive trace 206 arranged in concentricity from inside to outside. The second winding portion and the first winding portion aresymmetrical symmetrical with respect to the dashed line 2.

[0022] The first and second winding portions may be circular, rectangular, hexagonal, octagonal, or polygonal. Hereinafter, to simplify the diagram, only an exemplary octagonal shape is depicted. Moreover, the first and second winding portions may comprise copper, aluminum, or alloy thereof. In this embodiment, the first, second, and third semicircular conductive traces 201, 203 and 205 of the first winding portion and the first, second, and third semicircular conductive traces 202, 204 and 206 of the second winding portion have the same trace line width W.

[0023] Each semicircular conductive trace has a first end 10 and a second end 20. In this embodiment, the first end 10 of the first semicircular conductive trace 201 of the first winding portion and the first end 10 of the first semicircular conductive trace 202 of the second winding portion are coupled. The third semicircular conductive traces 205 and 206 of the first and second winding portions have lateral extending portions 30 and 40 as an input or an output for inputting differential signals.

[0024] In the embodiment, to maintain geometric symmetry, a coupling portion is disposed in the insulating layer 210 between the first and second winding portions, and the coupling portion comprises a first pair of connection layers and a second pair of connection layers. The first pair of connection layers cross-connects the first ends 10 of the second semicircular conductive trace 203 and the third semicircular conductive trace 206 and also cross-connects the first ends 10 of the second semicircular conductive trace 204 and the third semicircular conductive trace 205. Moreover, the second pair of connection layers cross-connects the second ends 20 of the first semicircular conductive trace 201 and the second semicircular conductive trace 204 and also cross-connects the second ends 20 of the first semicircular conductive trace 202 and the second semicircular conductive trace 203. For example, the first pair of connection layers may comprise an upper cross-connection 215 to couple the first ends 10 of the second semicircular conductive trace 203, and the third semicircular conductive trace 206 and the pair may comprise a lower cross-connection 217 to couple the first ends 10 of the second semicircular conductive trace 204 and the third semicircular conductive trace 205. The second pair of connection layers may comprise an upper cross-connection 213 to couple the second ends 20 of the first semicircular conductive trace 201 and the second semicircular conductive trace 204, and the pair may comprise a lower cross-connection 211 to couple the second ends 20 of the first semicircular conductive trace 202 and the second semicircular conductive trace 203.

[0025] Generally, since in the single-ended operation the signals with the same phase may pass through the adjacent conductive traces of the inductor, the parasitic capacitance between the adjacent conductive traces is lower and may be ignored. Accordingly, the trace line space between the winding portions may be designed to be as small as possible to enhance inductor performance. However, unlike the inductor in single-ended operation, the signals with phase difference of 180° may pass through the adjacent conductive traces of the inductor in differential operation. Thus, the parasitic capacitance between the adjacent conductive traces may be increased due to the signals with difference phase and cannot be ignored. In particular, the parasitic capacitance between the outmost conductive traces of the inductor is of concern. When the parasitic capacitance is increased, peak Q-factor frequency may be reduced and the inductance value deviation increased, so that the usable frequency range of the inductor is reduced.

[0026] Accordingly, in the invention, the adjacent semicircular conductive traces of each winding portion have a trace line space there between. And at least one relatively outer trace line space is wider than at least one relatively inner trace line space. For example, the trace line space S2 between the second semicircular conductive trace 203 and the third semicircular conductive trace 205 and the trace line space S2 between the second semicircular conductive trace 204 and the third semicircular conductive trace 206 can be wider than the trace line space Si between the second semicircular conductive trace 203 and the first semicircular conductive trace 201 and the trace line space SI between the second semicircular conductive trace 204 and the first semicircular conductive trace 202 (i.e. S2>S1). Since the outmost trace line space S2 is increased, the parasitic capacitance can be reduced when the symmetrical inductor is in the differential operation, thereby increasing the usable frequency range of the inductor.

[0027] FIG. 3 illustrates a four-turn symmetrical inductor of another embodiment of the invention. Elements in FIG. 3 the same as in FIG. 2 are labeled the same and are not described again. In FIG. 3, the first and second winding portions further comprise fourth semicircular conductive traces 207 and 208 located at outside of the third semicircular conductive traces 205 and 206, respectively. Also, the fourth semicircular conductive traces 207 and 208 have the same trace line width W. Moreover, the coupling portion further comprises a third pair of connecting layers. The third pair cross-connects the second ends 20 of the third semicircular conductive trace 205 and the fourth semicircular conductive trace 208 and also cross-connects the second ends 20 of the third semicircular conductive trace 206 and the third semicircular conductive trace 207. For example, the third pair of connection layers may comprise an upper cross-connection 219 to couple the second ends 20 of the third semicircular conductive trace 205 and the fourth semicircular conductive trace 208, and the third pair may also comprise a lower cross-connection 221 to couple the second ends 20 of the third semicircular conductive trace 206 and the fourth semicircular conductive trace 207. Moreover, the first ends 10 of the fourth semicircular conductive traces 207 and 208 of the first and second winding portions have lateral extending portions 30 and 40 as an input or an output for inputting differential signals.

[0028] In this embodiment, the trace line spaces are gradually increased from inside to outside. For example, the trace line space S3 between the third semicircular conductive traces 205 and 206 and the trace line space S3 between the fourth semicircular conductive traces 207 and 208 are wider than the trace line space S2 between the second semicircular conductive traces 203 and 204 and the trace line space S2 between the third semicircular conductive traces 205 and 206. Moreover, the trace line space S2 between the second semicircular conductive traces 203 and 204 and the trace line space S2 between the third semicircular conductive traces 205 and 206 are wider than the trace line space SI between the second semicircular conductive traces 203 and 204 and the trace line space Si between the first semicircular conductive traces 201 and 202 (i.e. S3>S2>S1).

[0029] In some embodiments, the trace line space S3 may be substantially equal to the trace line space S2 and wider than the trace line space S 1 (i.e. S3=S2>S1), as shown in FIG. 4. In some embodiments, the trace line space S2 may be substantially equal to the trace line space S1 and narrower than the trace line space S3 (i.e. S3>S2=S1), as shown in FIG. 5. Since the outmost adjacent conductive traces have the widest trace line space, the parasitic capacitance may be reduced when the symmetrical inductor is in differential operation, thereby increasing the usable frequency range of the inductor. Additionally, it is to be noted that the invention is not limited to a four-turn symmetrical inductor. More than four-turn traces may also be applied to provide the advantages as set forth.

[0030] While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.