Epitaxial wafer and method for manufacturing method

[0001] This is a U.S. national phase application under 35 U.S.C. § 371 of International Patent Application No. PCT/JP03/10390 filed Aug. 15, 2003, and claims the benefit of Japanese Patent Application No. 2002-252463 filed Aug. 30, 2002, which is incorporated by reference herein.

[0002] This invention relates to an epitaxial wafer with fewer pit defects in the epitaxial layer, and more particularly relates to the above-mentioned epitaxial wafer in which the number of pit defects has been reduced by using a wafer produced by slicing an ingot in a specific planar orientation, for a silicon monocrystalline wafer that has been doped with arsenic (As) and is prone to pitting when subjected to gas etching prior to epitaxial film formation, and to a method for manufacturing this epitaxial wafer.

[0003] In the past, the off-angle (that is, the tilt angle) of a (100) plane substrate in the manufacture of silicon epitaxial wafers has been specified in SEMI (Semiconductor Equipment and Materials International) standards to be no more than 2° (SEMI M2-87).

[0004] More recently, substrates with a tilt angle of 1° or less have come into mainstream use through increases in substrate machining precision.

[0005] For example, Japanese Patent Publication H3-61634 discloses a technique aimed at reducing microscopic defects (teardrops) during epitaxial growth, in which the angle θ in the [011] direction or [011] direction or the angle θ in the [011] direction or [011] direction with respect to the [100] axis was 5′≦θ≦2° and φ≦10′, or 5′≦φ≦2° and θ≦10′.

[0006] The underlines of the numbers indicating direction refer to the lines that ordinarily go over the numbers in crystallographic notation, but underlines will be used herein for the sake of convenience.

[0007] However, when a silicon (100) substrate wafer was epitaxially grown within these numerical ranges, the epitaxial wafer surface was sometimes rougher than the substrate wafer surface, which made it difficult to control the micro-roughness of the epitaxial wafer surface.

[0008] In view of this, Japanese Patent 3,081,706 discloses a method for improving the above-mentioned micro-roughness, in which the above-mentioned angle ranges for the slicing orientation are specified to be 30′≦θ≦2° and 30′≦φ≦2°.

[0009] The inventors discovered that the problem of pitting of the film layer after epitaxial growth is encountered when, in the manufacture of an epitaxial wafer, the surface of a standard silicon monocrystalline wafer that is n-type and has a low resistance of about 3 to 5 mΩ·cm is subjected to mirror polishing through a standard manufacturing procedure and further subjected to HCl gas etching prior to epitaxial growth for the sake of cleaning.

[0010] It is an object of the present invention to provide an epitaxial wafer with fewer pit defects in the epitaxial layer.

[0011] More particularly, it is an object of the present invention to provide an epitaxial wafer in which the above-mentioned pitting in a silicon monocrystalline wafer that has been doped with arsenic (As), which is prone to pitting when subjected to gas etching prior to epitaxial film formation, is suppressed when epitaxial film formation is performed, and a sound epitaxial layer is obtained, and to a method for manufacturing this epitaxial wafer.

[0012] As a result of diligent research into the tilt of the crystal axis and the planar orientation of a wafer in an effort to reduce the pitting of an epitaxial layer, the inventors perfected the present invention upon discovering that a sound epitaxial layer can be obtained by specifying a tilt angle of orientation that is different from the tilt angle specified in order to improve micro-roughness or tear-drop formation in the past as discussed above.

[0013] Specifically, the epitaxial wafer of the present invention is a wafer in which an epitaxial layer is grown on a wafer sliced from a silicon monocrystalline ingot that is doped with arsenic and has a resistivity of at least 2.5 mΩ·cm, wherein the planar orientation thereof is (100) and the slice is at an angle θ in the [001] direction or [001] direction and an angle φ in the [010] direction or [010] direction with respect to the [100] axis (0.2°≦θ and φ≦0.1°, or 0.2°≦φ and θ≦0.1°).

[0014] Also, the epitaxial wafer pertaining to the present invention is characterized in that an epitaxial film is formed on a wafer surface that has undergone gas etching for the sake of cleaning prior to epitaxial film formation, which reduces the number of pits seen after epitaxial film formation.

[0015] The method for manufacturing an epitaxial wafer pertaining to the present invention comprises the steps of:

[0016] slicing a silicon monocrystalline ingot such that the wafer has a crystal plane orientation of (100) and angles θ and φ are within specific ranges (0.2°≦θ and φ≦0.1°, or 0.2°≦φand θ≦0.1°);

[0017] gas etching the wafer surface prior to epitaxial film formation; and

[0018] epitaxially forming a film on the wafer surface,

[0019] wherein there is a reduction in the number of pits seen after epitaxial film formation.

[0020] With the present invention, as will be shown in the examples, an epitaxial wafer with a reduction in the number of pit defects in the epitaxial layer can be provided with no special step or additional work involved in the cutting of the silicon monocrystalline ingot, merely by specifying the orientation tilt angle during cutting.

[0021] In particular, with the present invention, the above-mentioned pitting is suppressed, and a sound epitaxial layer is obtained, even when epitaxial film formation is performed on a silicon monocrystalline wafer that has been doped with arsenic (As), which is prone to pitting when subjected to gas etching prior to epitaxial film formation.

[0023] In the present invention, because the silicon monocrystalline ingot and wafer are used in the manufacture of an epitaxial wafer, they must be doped with arsenic and have a resistivity of at least 2.5 mΩ·cm. There is no need to place an upper limit on resistivity here.

[0024] In the present invention, the crystal plane orientation of the wafer is (100), in the (100) plane of the wafer the crystal directions [001], [001], [010], and [010] pass through the wafer center, and the angular component in the [001] direction or [001] direction with respect to the [100] axis is termed the angle q, while the angular component in the [010] direction or [010] direction is termed the angle f, both of which are angles formed by the (100) plane normal and the planar normal of the wafer surface.

[0025] As shown in FIG. 1, the present invention is characterized in that the above-mentioned tilt angles θ and φ are kept within ranges of 0.2°≦θ and φ≦0.1°, or 0.2°≦φ and θ≦0.1°. If θ is 0.2° or greater, it should be greater than f, and the difference is preferably at least 0.1. Similarly, if φ is 0.2° or greater, it should be greater than q.

[0026] The inventors have surmised that pit defects in the epitaxial layer are caused by COP, and whether or not these pit defects are generated (remain) depends on the above-mentioned tilt angle. The inventors have also confirmed that if the tilt angles θ and φ are kept within the ranges given above, no pit defects will occur on the surface after epitaxial film formation.

[0027] In the present invention, the step of slicing wafers from the silicon monocrystalline ingot can be accomplished by any known slicing method that makes use of a wire saw, ID blade, etc.

[0028] The manufacturing steps after slicing the ingot into wafers can include any known steps and methods according to the intended use and the required properties, cleanliness, and so forth, such as various kinds of grinding steps, mirror polishing steps, chamfering steps, washing steps, and so forth. The types of steps selected, the order in which they are carried out, and so forth can be determined as appropriate.

[0029] In the present invention, there are no particular restrictions on the step of epitaxially forming a film on the wafer surface, and any known vapor phase film formation method and vapor phase growth apparatus can be used if they allow for the vapor phase growth of a silicon epitaxial layer required as a substrate in the manufacture of semiconductor devices. The source gas and film formation conditions should be determined according to the selected method and apparatus, etc. The treatment temperature should be between 1050 and 1150° C.

[0030] Also employed in the present invention is a step of gas etching the wafer surface before it undergoes epitaxial film formation. In specific terms, as will be shown in the examples, the preliminary steps to epitaxial film formation are carried out, namely, hydrogen gas replacement while the temperature is raised inside a chamber, and hydrogen baking at the required temperature, this is followed by HCl gas etching, after which a source gas is introduced at the temperature and in the atmosphere required for film formation, and vapor phase growth is performed so as to obtain the required film thickness, thereby forming a silicon epitaxial layer.

[0031] As for the hydrogen baking conditions, a temperature of 1050° C. to 1200° C. is preferable, and a chlorine compound gas can be used instead of HCl gas. The preferred amount of etching is to a depth of no more than 0.5 μm from the surface.

[0032] Using a wire saw apparatus (made by Nippei Toyama), silicon monocrystalline wafers were produced from a silicon monocrystalline ingot that had been doped with arsenic, had an outside diameter of 6 inches, and had been pulled up by the Czochralski method. The resulting wafers had a resistivity of 4 mΩ·cm, were n-type, and the tilt angles from the (100) plane were θ=0.24° and φ=0.02°.

[0033] These wafers were mirror polished and washed, after which they were subjected to hydrogen baking in which they were held for 1 minute in a 1150° C. hydrogen atmosphere, and then HCl gas was introduced to perform gas etching to a depth of about 0.1 μm. A source gas was then supplied and vapor phase growth was performed while the temperature was held at 1100° C., which formed an epitaxial layer with a thickness of 4 μm.

[0034] In the above steps, the condition of the wafer surface was observed by light scattering method (A) prior to placing the wafer in the vapor phase growth apparatus, (B) after gas etching, and (C) after epitaxial film formation, and the number of defects was examined. These results are given in Table 1.

[0035] An M0601 made by Mitsui Mining & Smelting was used to count the defects (COP) prior to placing the wafer in the vapor phase growth apparatus (A). A Surfscan 6220 made by KLA Tencor was used to count the defects (pits) after gas etching (B) and after epitaxial film formation (C).

[0036] Regarding the defect counts in Table 1, the COP count prior to placing the wafer in the vapor phase growth apparatus (A) was 26, 035, the number of pits after gas etching (B) was 2621, and the number of pits after epitaxial film formation (C) was 22.

[0037] Using a wire saw apparatus, silicon monocrystalline wafers were produced from a silicon monocrystalline ingot that had been doped with arsenic, had an outside diameter of 6 inches, and had been pulled up by the Czochralski method. The resulting wafers had a resistivity of 4.8 mΩ·cm, were n-type, and the tilt angles from the (100) plane were θ=0.20° and φ=0.10°.

[0038] An epitaxial layer with a thickness of 4 μm was formed under the same conditions as in Example 1, using the wafer obtained above. The product was observed and measured under the same conditions as in Example 1. Specifically, Table 1 shows the defect counts prior to placing the wafer in the vapor phase growth apparatus (A), after gas etching (B), and after epitaxial film formation (C).

[0039] Regarding the defect counts in Table 1, the COP count prior to placing the wafer in the vapor phase growth apparatus (A) was 25, 303, the number of pits after gas etching (B) was 2754, and the number of pits after epitaxial film formation (C) was 34.

[0040] Using a wire saw apparatus, silicon monocrystalline wafers were produced from a silicon monocrystalline ingot that had been doped with arsenic, had an outside diameter of 6 inches, and had been pulled up by the Czochralski method. The resulting wafers had a resistivity of 4.2 mΩ·cm, were n-type, and the tilt angles from the (100) plane were θ=0.18° and φ=0.13°.

[0041] An epitaxial layer with a thickness of 4 μm was formed under the same conditions as in Example 1, using the wafer obtained above. The product was observed and measured under the same conditions as in Example 1. Specifically, Table 1 shows the defect counts prior to placing the wafer in the vapor phase growth apparatus (A), after gas etching (B), and after epitaxial film formation (C).

[0042] Regarding the defect counts in Table 1, the COP count prior to placing the wafer in the vapor phase growth apparatus (A) was 28, 902, the number of pits after gas etching (B) was 15, 253, and the number of pits after epitaxial film formation (C) was 7546.

[0043] Using a wire saw apparatus, silicon monocrystalline wafers were produced from a silicon monocrystalline ingot that had been doped with arsenic, had an outside diameter of 6 inches, and had been pulled up by the Czochralski method. The resulting wafers had a resistivity of 3.6 mΩ·cm, were n-type, and the tilt angles from the (100) plane were θ=0.22° and φ=0.21°.

[0044] An epitaxial layer with a thickness of 4 μm was formed under the same conditions as in Example 1, using the wafer obtained above. The product was observed and measured under the same conditions as in Example 1. Specifically, Table 1 shows the defect counts prior to placing the wafer in the vapor phase growth apparatus (A), after gas etching (B), and after epitaxial film formation (C).

[0045] Regarding the defect counts in Table 1, the COP count prior to placing the wafer in the vapor phase growth apparatus (A) was 2822, the number of pits after gas etching (B) was 2125, and the number of pits after epitaxial film formation (C) was 252.

• [0046] A comparison of the examples and comparative examples above reveals that the number of defects after formation of the epitaxial layer can be reduced with the present invention even when the COP count of the substrate is high.

[0047]

	TABLE 1
	Detect count
	prior to
	placing the
	wafer in the		Defect count
	vapor phase	Defect count	after epitaxial
	growth	after gas	film formation
	apparatus (A)	etching (B)	(C)
	Example 1	26035	2621	22
	Example 2	25303	2754	34
	Comparative	28902	15253	7546
	Example 1
	Comparative	2822	2125	252
	Example 2

[0048] With the present invention, an epitaxial wafer with a reduction in the number of pit defects in the epitaxial layer can be provided with no special step or additional work involved, merely by cutting a silicon single crystal at a specific orientation and tilt angle in the manufacture of an epitaxial wafer. This greatly improves the manufacturing process.

[0049] Also, with the present invention, gas etching, which improves cleaning, can be performed prior to epitaxial film formation on a silicon monocrystalline wafer that has been doped with arsenic (As), the occurrence of pit defects after epitaxial film formation can be suppressed, and a sound epitaxial layer can be obtained.