System and method for testing write strobe timing margins in memory devices

[0001] This invention relates to testing integrated circuits such as memory devices, and, more particularly, to a system and method for testing the timing margins of data strobe preambles and postambles applied to memory devices.

[0002] During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.

[0003] While the above-described testing environment works well in many applications, it is not without its limitations and disadvantages. For example, it is very difficult to test various timing characteristics of the integrated circuits, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty in testing timing characteristics results primarily from the propagation delays in the cable coupling the tester to the test head. The cables that are typically used in such testing environments are often fairly long, thus making the delays of signals coupled to and from the integrated circuits correspondingly long and often difficult to predict.

[0004] Another problem with the above-described testing environment is that it may not accurately simulate the conditions in which the integrated circuits will be actually used. In actual use, integrated circuits, such as dynamic random access memory (“DRAM”) devices are typically mounted on a printed circuit board. Signals are applied to the integrated circuits by other integrated circuits mounted on the board, and signals generated by the integrated circuits are received by other integrated circuits mounted on the board. In most applications, signals are not coupled to and from the integrated circuits through long cables coupled to distant electronic devices. Therefore, the testing environment is normally quite different from the environment in which the integrated circuits will operate in normal use.

[0005] While techniques have been developed to deal with these difficulties, the use of these techniques results in testers that are highly complex and often very expensive. A large number of testers are normally required for a high capacity semiconductor fabrication plant, thus greatly increasing the cost of the plant and the expense of testing the integrated circuits.

[0006] One improved testing system that has been proposed is to fabricate an integrated test circuit that performs most if not all of the functions of conventional testers, and mount the integrated test circuit on the test head or load board to which the integrated circuits being tested are coupled. By placing the testing function on the test head or load board itself, the problems inherent in coupling test signals between a testing system and a test head are eliminated. As a result, the circuits can be tested in a more realistic environment. Furthermore, since even custom integrated circuits can be fabricated relatively inexpensively, the cost of testing systems can be greatly reduced.

[0007] One difficulty in using an integrated test circuit in this manner stems from the difficulty in accurately testing timing margins of memory devices. For example, synchronous memory devices normally receive a write data strobe signal, which is commonly abbreviated as “DQS.” A typical DQS signal 2 is shown in FIG. 1. The DQS signal 2 includes an active portion 4 containing several logic level transitions, which are synchronized to write data signals that are also applied to the memory devices. The active portion 4 of the DQS signal 2 is preceded by a preamble 6, and it is followed by a postamble 8. In the example shown in FIG. 1, the active portion 4 includes two falling edge transitions and three rising edge transitions, the first of which terminates the preamble 6 and the last of which initiates the postamble 8.

[0008] Specifications for synchronous memory devices normally specify a range of acceptable timing values for the DQS preamble 6 and postamble 8. It is important to ensure that a memory device being tested meets these specifications. The ability of a memory device to meet the preamble and postamble width specifications is normally tested by applying DQS signals to the memory device having preambles and postambles that span the range of acceptable values. The ability of the memory device to operate properly with all of the preambles and postambles in the specified range is then determined by reading data from the memory device that have been written using DQS signals with the various preamble and postamble values.

[0009] Unfortunately, with modern high-speed memory devices, it is difficult to generate test signals that have precise but very small time durations, such as preambles and postambles. Expensive high-speed testers of the type normally used to test memory devices are capable of precisely controlling the timing of each transition of the DQS signal, including the preambles and postambles. However, the lack of a good timing mechanism that can easily be fabricated in an integrated circuit threatens to preclude the use of an integrated test circuit mounted on a load board or test head from accurately testing whether a memory device meets preamble and postamble specifications.

[0010] There is therefore a need for a testing system and method that can be easily fabricated in an integrated circuit to allow an integrated test circuit mounted on a load board, test head or the like to generate DQS signals having preambles and postambles with very precisely controlled durations.

[0011] A system and method of testing memory devices is used to determine if the memory devices meet specifications for the duration of write data strobe preambles and postambles. The system includes a write strobe generator that generates a digital signal having a selectable number of transitions between first and second logic levels. The system also includes a phase interpolator that generates an enable clock signal by phase shifting an input clock signal by an amount that is controlled by a phase control signal. An enable circuit receives the enable clock signal from the phase interpolator and generates an active enable signal. When the enable circuit receives a DQS enable signal from a control circuit, it generates an active enable signal responsive to a subsequent transition of the enable clock signal. A transmitter receives the digital signal from the write strobe generator and the enable signal from the enable circuit. The transmitter transmits as a write strobe signal the digital signal during the period that the enable signal is active. In addition to applying the DQS enable signal to the enable circuit, the control circuit applies the phase control signal to the phase interpolator to control the timing and duration of the enable signal generated by enable circuit. As a result, the control circuit determines the durations of first and last portions of the digital signal that are used as write strobe preambles and postambles, respectively.

[0022] A DQS preamble/postamble test system 10 according to one example of the invention is illustrated in FIG. 2. The test system 10 includes three phase interpolators 20, 24, 28, all of which are driven by a first common clock signal CLK_IN and a second common clock signal CLK_IN2, which has a fixed phase off set from the CLK_IN signal. However, the clock signal driving the phase interpolators 20, 24, 28 need not be common to all of the phase interpolators. As is well-known in the art, a phase interpolator produces a delayed signal from one clock input signal by interpolating between the clock signals by a precisely controlled amount. The degree of precision of the delayed signal depends on the precision of the input signal frequency.

[0023] A CLK_EN signal at the output of the phase interpolator 20 is applied to the clock input of a flip-flop 34, which also receives an ENABLE signal at its data input. The output of the flip-flop 34 is applied to the data input of a second flip-flop 36 and to one input of an OR gate 38. The output of the OR gate 38 is therefore high whenever the ENABLE signal is active high at the rising edge of the CLK_EN signal.

[0024] The CLK_EN signal is also applied through an inverter 40 to the clock input of the flip-flop 36. Therefore, the flip-flop 34 is clocked on the rising edge of the CLK_EN signal, and the flip-flop 36 is clocked on the falling edge of the CLK_EN signal. The output of the flip-flop 36 is applied to the other input of the OR gate 38. As a result, a DQS_EN signal at the output of the OR gate 38 is high whenever the output of either flip-flop 34 or 36 is high. The output of the flip-flop 36 becomes high on the falling edge of CLK_EN after the output of the flip-flop 34 has transitioned high. Therefore, the DQS_EN will transition high on the rising edge of the CLK_EN signal after the ENABLE signal transitions high. The DQS_EN signal will transition low when the ENABLE signal transitions low followed by a rising edge of the CLK_EN signal and a falling edge of the CLK_EN signal. The DQS_EN signal is applied to both the EN_EVEN and the EN_ODD inputs of a transmitter 50, the operation of which will be explained below.

[0025] The transmitter 50 also has D_EVEN and D_ODD inputs that receive Data Even and Data Odd signals, respectively, from respective outputs of a test signal generator 54. As explained below in greater detail in connection with the timing diagram of FIG. 5, the logic levels of the Data Even and Data Odd signals generated by the test signal generator 54 will serve as the DQS signal logic levels output by the test system 10.

[0026] The transmitter 50 also has a T₀ input that receives a Tx0 signal from the output from the phase interpolator 24, and a T₁ input that receives a Tx1 signal from the output from the phase interpolator 28. The timing of the transitions of these signals Tx0, Tx1 can be individually controlled by controlling the phase shifts of the phase interpolators 24, 28, respectively.

[0027] The internal components of the transmitter 50 are shown in FIG. 3, and its operation will be explained with reference to the timing diagram of FIG. 4. The Tx0 signal is applied to a non-inverting input of an AND gate 60, and the Tx1 signal is applied to an inverting input of the AND 60. The Tx0 and Tx1 signals are shown in lines 1 and 2 of FIG. 4 as being the compliment of each other, although that relationship between the Tx0 and Tx1 signals is not required. In operation, the AND gate 60 outputs a high whenever the Tx0 signal is high and the Tx1 signal is low. Because the Tx0 and Tx1 signals are the compliments of each other in the example shown in FIG. 4, the output of the AND gate 60 is identical to the Tx0 signal.

[0028] As shown in lines 3 and 4 of FIG. 4, the Data Even and Data Odd signals are valid for one full period of the Tx0 and Tx1 signals. The Data Even signal is valid in synchronism with the Tx0 signal, and the Data Odd signal is valid in synchronism with the Tx1 signal. These signals are applied to respective inputs of a multiplexer 64, which is controlled by the output of the AND gate 60. When the output of the AND gate 60 is high, the Data Even signal is coupled to the output of the multiplexer 64, and when the output of the AND gate 60 is low, the Data Odd signal is coupled to the output of the multiplexer 64. A Serialized Data signal from the output of the AND gate 60 is shown in the seventh line of FIG. 4. The Serialized Data signal alternately corresponds to the data even signal and the data odd signal, and each signal is present for only one-half the period of the Tx0 and Tx1 signals. Each Data Even signal starts at the rising edge of the Tx0 signal, and the timing at which each Data Even signal starts is therefore controlled by the phase interpolator 24. Similarly, each Data Odd signal starts at the rising edge of the Tx1 signal, and the timing at which each Data Odd signal starts is therefore controlled by the phase interpolator 28.

[0029] The transmitter 50 also includes a second multiplexer 68 having two inputs that receives respective Enable Even and Enable Odd signals. In the test system, the Enable Even and Enable Odd signals are both identical to the DQS_EN signal. However, in the timing diagram example shown in FIG. 4, they are shown in lines 4 and 5 as being different from each other. The multiplexer 68 operates in the same manner as the multiplexer 64, and it therefore couples the Enable Even signal to its output when the Tx0 signal is high, and it couples the Enable Odd signal to its output when the Tx1 signal is high. A Serialized Enable signal output from the multiplexer 68 is shown eighth line of FIG. 4. However, in the test system the Serialized Enable signal will be identical to the DQS_EN signal since the DQS_EN signal is applied to both inputs of the multiplexer 68.

[0030] With further reference to FIG. 3, the Serialized Enable signal is applied to the enable input of a buffer 70, which receives the Serialized Data signal at its input. As shown in the last line of FIG. 4, the buffer 70 outputs the Serialized Data whenever the Serialized Enable signal is high.

[0031] Returning to FIG. 2, the operation of the test system 10 will now be explained with reference to the timing diagram shown in FIG. 5. In the example shown in FIG. 5, the phase interpolators 24, 28 are adjusted so that the Tx0 and Tx1 signals shown in lines 1 and 2 are again the compliments of each other. However, the phase interpolator 20 is adjusted so that the CLK_EN signal shown in line 3 of FIG. 5 lags the Tx0 signal by slightly more than 90 degrees. As shown in the fourth line, the ENABLE signal becomes active high coincident with the rising edge of the Tx1 signal at time t₀. The high ENABLE signal is clocked into the flip-flop 34 responsive to the subsequent rising edge of the CLK_EN signal from the phase interpolator 20 at time t₂, thereby transitioning the DQS_E0 signal high, as shown in line 5. As explained above, the high DQS_E0 signal at the output of the flip-flop 34 is coupled through the OR gate 38 to make the DQS_EN signal high, as shown in line 7. The timing of the phase interpolator 20 thus determines when the DQS_EN becomes active high. On the next falling edge of the CLK_IN signal, the high DQS_E0 signal is clocked into the flip-flop 36, thereby making DQS_E1 signal high at time t₄, as shown in line 6. However, this transition of the DQS_E1 signal has no effect on the DQS_EN signal since the OR gate 38 is already outputting the high from the flip-flop 34.

[0032] As shown in the example of FIG. 5, the test signal generator 54 outputs a Data Even signal that is initially high, but transitions low at time t₁, as shown in line 11. Similarly, the Data Odd signal from the test signal generator 54 shown in line 12 is also initially high, but transitions low at time t₃. As explained above, the multiplexer 64 (FIG. 3) produces a Serialized Data signal that is the same as the Data Even signal responsive to the rising edge of the Tx0 signal, and is the same as the Data Odd signal responsive to the rising edge of the Tx1 signal. Therefore, the Serialized Data signal is the same as the low Data Even signal starting at time t₁, the low Data Odd signal starting at time t₃, the high Data Even signal starting at time t₅, the low Data Odd signal starting at time t₆, the high Data Even signal starting at time t₇, and the low Data Odd signal starting at time t₈. The result is a Serialized Data signal shown in the line 13 that has a relatively long logic low level between times t₁ and t₅, a set of 4 signal transitions between t₅ and t₈, and a short logic low level between t₈ and t₉. As explained below, in testing a memory device, a portion of the logic low level between times t₁ and t₅ will serve as the preamble of the DQS signal, a portion of the short logic low level between times t₈ and t₉ will serve as the postamble of the DQS signal, and the 4 signal transitions between times t₅ and t₈ serve as the portion of the DQS signal that clocks write data into the memory device.

[0033] As mentioned above, the DQS_EN signal is coupled to both the Enable Even and the Enable Odd inputs of the transmitter 50. As explained above with reference to FIGS. 3 and 4, the high Enable Even and Enable Odd signals shown in lines 8 and 9, respectively, produce the Serialized Enable signal shown in line 10. The high Serialized Enable signal enables the buffer 70 (FIG. 3) so that the Serialized Data signal shown in line 13 is output from the test system 10 as the DQS signal shown in line 14. Insofar as the buffer 70 is not enabled until the Serialized Enable signal transitions high at time t₂, the logic low portion of the Serialized Data signal between times t₁ and t₂ is not output from the buffer 70. The timing of the Serialized Enable signal, which, as explained above, is controlled by the phase of the interpolator 20, thus determines the starting time of the preamble of the DQS signal.

[0034] With further reference to FIGS. 4 and 5, the DQS signal postamble terminates at time t₉ responsive to the Serialized Enable signal transitioning inactive low. Serialized Enable signal becomes logic low at time t₉ because DQS_E1 signal at the output of the flip-flop 36 (FIG. 2) goes low responsive to the falling edge of the CLK_IN signal since the ENABLE signal had previously transitioned low before to the previous rising edge of the CLK_IN signal, thereby making the DQS_E0 signal low. Therefore, by controlling the timing of the CLK_IN signal, the phase interpolator 20 also determined the timing of the end of the postamble.

[0035] Although only one example is shown in FIG. 5, it should be understood that the test system 10 can control the duration of the DQS preamble and postamble to any desired value. Furthermore, since the duration of the DQS preamble and postamble is controlled by the phase interpolator 20, which inherently can be made very precise, the duration of the DQS preamble and postamble can be precisely controlled. Also, by varying the timing of the phase interpolator 20, the duration of the DQS preamble and postamble can still be controlled if the phase interpolators 24, 28 are adjusted to vary the timing of the DQS transitions during the testing of a memory device.

[0036] A write strobe preamble/postamble test system 80 according to another example of the invention is shown in FIG. 6. The system 80 has the advantage of using fewer phase interpolations that are used on the system 10 of FIG. 2, and thus uses a smaller area of a semiconductor die and less power. The system 80 includes the test signal generator 54 as well as two phase interpolators 82, 84 receiving the CLK_IN signal. The test signal generator 54 outputs signals that will result in a DQS signal during normal testing of a memory device and during testing of the DQS preamble/postamble timing margins. The test system 80 also includes a mode controller 86, which receives an Output Enable (“OE₁”) signal and Dynamic Termination Pull-Up (“PU₁”) and Pull-Down (“PD₁”) Control signals from the test signal generator 54. The mode controller 86, in turn, applies an Output Enable (“OE₂”) signal and Dynamic Termination Pull-Up (“PU₂”) and Pull-Down (“PD₂”) Control signals to a buffer 88, which outputs a DQS signal to a memory device being tested. In normal operation, a DQS signal may also be applied to the buffer 88.

[0037] The phase shift provided by the phase interpolators 82, 84, as well as the operation of the mode controller 86, is controlled by a control unit 90. The phase interpolators interpolate between the phase of the rising edge of the CLK_IN signal and the phase of either the next falling edge (i.e., 180°) or the next rising edge (i.e., 360°) of the CLK_IN signal.

[0038] In the normal operating mode, the test signal generator 54 provides Normal Write Strobe (“DQS_NORMAL”) pattern, which bypasses the mode controller 86 and is applied directly to the buffer 88. The DQS_NORMAL signal is representative of a two-part, even and odd, datapath to be serialized having its logic levels output from the buffer 88 responsive to the rising edge of the Tx0 signal and the rising edge of the Tx1 signal. Also, in the normal mode, the OE₁ signal passes through the mode controller 86 to become the OE₂ signal, which selectively enables the buffer 88. Finally, the PU₁ or PD₁ signals are also effectively coupled through the mode controller 86 to become the PU₂ and PD₂ signals, respectively. As is well known in the art, the PU₂ or PD₂ signals cause the buffer 88 output terminal to be biased to either a high logic level or a low logic level, respectively, when the buffer 88 is not outputting a DQS signal and an incoming DQS signal may be applied to the output terminal of the buffer 88.

[0039] In the DQS preamble/postamble timing margin test mode, the PU₁ and PD₁ signals are output from the mode controller 86 and applied to the buffer 88 as the PU₂ and PD₂ signals, respectively, responsive to a high Tx0 signal. However, the PU₂ and PD₂ signals are output from the mode controller 86 only when the mode controller 86 has been enabled. Therefore, when the mode controller has been enabled, the timing of the Tx0 signal at the output of the phase interpolator 82 therefore controls the timing of the PU₂ or PD₂ signals being output from the mode controller 86.

[0040] The mode controller 86 is enabled responsive to receiving an active OE₁ upon the rising edge of the Tx1 signal. Therefore, the timing of the Tx1 signal at the output of the phase interpolator 84 controls the enabling of the mode controller 86 to allow the DQS signal corresponding to the PU₂ or PD₂ signals to be output from the buffer 88. The width of the DQS preamble and postamble is thus determined by the timing of the Tx1 signal relative to the timing of the Tx0 signal. The test system 80 is therefore very similar to the test system 10 of FIG. 2 in that the widths of the DQS preambles and postambles are controlled by the timing of an enable signal, which is, in turn, controlled by the timing of a signal generated by a phase interpolator 20 (FIG. 2) and 84 (FIG. 6).

[0041] A mode controller 100 that can be used as the mode controller 86 in the test system 80 of FIG. 6 is shown in FIG. 7, and some of the signals present in the mode controller 86 are shown in FIG. 8. The mode controller 100 receives the OE₁ signal at one input of multiplexer 102, and the other input of the multiplexer 102 is coupled to ground. The multiplexer 102 is controlled by a Mode Enable signal, which is generated by the control unit 90 (FIG. 6). In the normal operating mode, the multiplexer 102 couples the OE₁ signal to the output to become the OE₂ signal, as previously mentioned. In the DQS preamble/postamble timing margin test mode, the multiplexer 102 connects the output to ground to hold the OE₂ signal applied to the buffer 88 (FIG. 6) at an inactive low level.

[0042] The PU₁ signal from test signal generator 54 is applied to one input of an OR gate 110, and is conveyed directly to signal PU₂ for use in normal operating mode. In DQS preamble/postamble timing margin test mode, the second input of OR gate 110 receives a pull-up test pattern from the output of AND gate 112. The AND gate 112 generates a high output whenever a high Tx0 signal at the output of the phase interpolator 82 is coupled through a buffer 116 and the AND gate 112 is enabled by a high being applied to its other input. As shown in FIG. 8, this enabling high is coupled to the input of the AND gate 112 by an OR gate 120 after an active high OE₁ signal has been clocked into a flip-flop 122 responsive to the rising edge of the Tx1 signal. On the next falling edge of the Tx1 signal, the high at the output of the flip-flop 122 is clocked into a second flip-flop 126 so that both inputs of the OR gate 120 are high, as also shown in FIG. 8. The output of the OR gate 120 therefore remains high to enable the AND gate 112 after the OE, signal has transitioned low until a rising edge of the Tx1 signal followed by a falling edge of the Tx1 signal have occurred.

[0043] A second OR gate 130, AND gate 132 and inverter 136 produce the PD₂ signal operate in the same manner that the PU₂ signals was generated responsive to the PD₁ signal with a timing controlled by the timing of the Tx1 signal relative to the timing of the Tx0 signal.

[0044] It can therefore be seen from the signals shown in FIG. 8 that, the timing of the Tx0 signal output from the phase interpolator 82 controls the timing that the PU₂ and PD₂ signals that would be output from the mode controller 100. However, these signals cannot be output from the mode controller 100 until the AND gate 112 has been enabled. Yet the timing of the AND gate 112 becoming enabled by the OE₁ signal is controlled by the rising edge of the Tx1 signal output from the phase interpolator 84. Therefore, as shown in the bottom line of FIG. 8, the width of the DQS preamble corresponds to the lag of the Tx0 signal from the Tx1 signal. Such is the operation while the width of the DQS preamble is under test. Furthermore, the width of the DQS postamble can be placed under test instead of the DQS preamble by increasing the lead of the Tx1 signal relative to the Tx0 signal. In such case, it is the falling edge of signal Tx1 which ends the high output from AND gate 112. Controlling the output of phase interpolator 84 can delay the beginning of the DQS preamble or accelerate the ending of the DQS postamble, allowing either region to be tested.

[0045] A memory device test system 200 that can use the write strobe preamble/postamble test system of FIG. 2, the write strobe preamble/postamble test system of FIGS. 6 and 7 or a write strobe preamble/postamble test system according to another example of the invention is shown in FIG. 9. The memory device test system 200 includes a test head 212 on which several load boards 214a-d are placed. Each of the load boards 214a-d have a printed circuit substrate 216 on which several integrated circuit sockets 218a-h are mounted. Each of the integrated circuit sockets 218a-h received a respective memory device (not shown in FIG. 8). In the example shown in FIG. 9, the sockets 218a-h are adapted to receive dynamic random access memory (“DRAM”) devices. Prior to final testing of the memory devices, an integrated circuit handler loads a memory device into each of the sockets 218a-h, and then places each of the load boards 214a-d on the test head 212.

[0046] As explained in greater detail below, each of the load boards 214a-d includes an integrated test circuit (not shown in FIG. 9) mounted on the surface of the substrate 216 opposite the surface on which the sockets 218a-h are mounted. The sockets 218a-h are shown mounted on the upper surface of the substrate 216 in greater detail in FIG. 10A.

[0047] The lower surface of the substrate 216 is shown in FIG. 10B. The integrated test circuit 220 is mounted at the center of the substrate 216, and it is connected to the sockets 218a-h (FIG. 10A) through conventional printed circuit traces (not shown in FIG. 10B). Also mounted on the lower surface of the substrate 216 are a conventional JTAG connector 222 and a power supply connector 224. High-level test commands are applied to the test circuit 220 through the JTAG connector 222, and high-level results data are received from the test circuit 220 through the JTAG connector 222. Power is applied to the test circuit 220 as well as to memory devices mounted in the sockets 218a-h through the power supply connector 224.

[0048] In operation, the test circuit 220 applies a pattern of signals to the memory devices mounted in the sockets 218a-h, and receives signals from the memory devices indicative of the response of the memory devices to the pattern of signals. More particularly, the test circuit 220 writes data to the memory devices in the integrated circuit sockets 218a-h using DQS signals having a range of preamble and postamble durations. The test circuit 220 then reads the data from the memory devices in the sockets 218a-h to determine if data were successfully written to the memory devices using DQS signals having each preamble and postamble duration. The test circuit 220 is therefore able to determine whether the memory devices in the sockets meet the DQS preamble and postamble specifications. The test circuit 220 preferably also test other timing margins by varying the timing of other signals, such as write data signals, in order to completely test the memory devices. Insofar as the integrated test circuit 220 is mounted on the same substrate 216 as the memory devices, the timing at which the pattern of signals are applied to the memory devices can be more precisely controlled. Furthermore, the relatively short length of the conductors and extending from the integrated test circuit 220 to the integrated circuits in the sockets 218a-h allows the circuitry in the test circuit 220 to be less complex and therefore less expensive than with testers in which a pattern of test signals is applied through a long cable.

[0049] With further reference to FIG. 9, the test head 212 is mounted on the upper ends of several power supplies 226a-d, which generate DC supply voltages at respective magnitudes for use by the test head 212 and the load boards 214a-d. As mentioned above, the DC supply voltages are applied to the test head 212 through the power supply connector 224 (FIG. 10B). The test head 212 also includes fluid couplings 226a,b that receive and discharge a cooling fluid, respectively, for maintaining the temperature of the test circuit 220 at a stable acceptably cool temperature.

[0050] Although the present invention has been described with reference to the disclosed examples, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.