PFM control circuit for DC regulator

[0001] 1. Field of the Invention

[0002] The present invention relates to a pulse frequency modulation (PFM) control circuit and, more particularly, to a PFM control circuit for converting voltages with high efficiency over broad loading requirements.

[0003] 2. Description of the Related Art

[0004] For providing electronics devices with a stable power supply so as to ensure steady performance, voltage regulators are indispensable components. The voltage regulator supplies a required amount of current to a load at a regulated output voltage. Therefore, when the electronics devices are used as the loads with respect to the voltage regulators, the performance of the electronics devices is kept stable and prevented from being affected by fluctuations of the power supply. In addition to the regulation of the power supply, the lifetime of the power supply is also an important issue to be considered for a variety of portable electronics devices powered by isolated and finite sources such as batteries.

[0005] In terms of the efficiency of voltage conversion, linear voltage regulators due to power loss caused by passive regulating transistors are inferior to switching voltage regulators. The switching voltage regulator typically includes a control circuit for turning on and off a switching circuit. Through appropriately control the duty ratio of the switching circuit, i.e. a ratio of an ON-time of the switching circuit to a period of a switch cycle, the output voltage is regulated to a desired level for supplying current required by the load. In prior art are there many well-known control circuits and methods, such as a pulse width modulation (PWM) mode, a constant ON-time PFM mode, and a constant OFF-time PFM mode. However, the conventional control circuits and methods achieve a high efficiency of voltage conversion only within a limited range of loading requirements. For example, the PWM mode provides a preferred efficiency in a heavy loading operation, the constant ON-time PFM mode in a light loading operation, and the constant OFF-time PFM mode in a heavy loading operation. In order to convert voltages with high efficiency both in heavy and light loading operations, it has been suggested that an automatic selection be made between the PWM mode and the PFM mode depending on the magnitude of the loading requirement. However, such a solution must combine two different kinds of control circuits into the same integrated circuit chip as well as a specially-designed mode selection circuit, resulting in complicated circuitry and a higher cost.

[0006] Therefore, it is desirable to develop a control circuit and method of converting voltages with high efficiency over broad loading requirements.

[0007] In view of the above-mentioned problems, an object of the present invention is to provide a PFM control circuit capable of converting voltages with high efficiency over broad loading requirements.

[0008] According to one aspect of the present invention, a pulse frequency modulation control circuit is provided for controlling a switching regulator to convert an input voltage to an output voltage. The switching regulator has a switching circuit and an inductive device. The pulse frequency modulation control circuit includes a current sensing circuit, a voltage sensing circuit, and a pulse generating circuit. The current sensing circuit generates a current detection signal representative of a current flowing through the inductive device. The voltage sensing circuit generates a voltage detection signal representative of the output voltage. In response to the current detection signal and the voltage detection signal, the pulse generating circuit generates a pulse control signal. The pulse control signal has a plurality of switch cycles, each of which consists of an ON-time and an OFF-time. The ON-time is applied to turn on the switching circuit while the OFF-time is applied to turn off the switching circuit.

[0009] The ON-time is adjusted in accordance with the current detection signal such that the ON-time is prolonged in response to an increase of a maximum of the current detection signal. Therefore, the necessary number of the switch cycles is prevented from increasing in a heavy loading operation, resulting in an improvement of the efficiency in voltage conversion. The OFF-time is adjusted in accordance with the voltage detection signal such that the OFF-time is prolonged in response to a reduction of a falling rate of the voltage detection signal. Therefore, the necessary number of the switch cycles is prevented from increasing in a light loading operation, resulting in an improvement of the efficiency in voltage conversion.

[0010] According to another aspect of the present invention, a pulse frequency modulation method is provided for controlling a switching regulator to convert an input voltage to an output voltage. The switching regulator has a switching circuit and an inductive device. The pulse frequency modulation control method has a plurality of switch cycles. Each switch cycle includes: a step of providing an ON-time for being applied to turn on the switching circuit, and a step of providing an OFF-time for being applied to turn off the switching circuit. The ON-time during a present switch cycle is dynamically adjusted in accordance with a maximum of a current flowing through the inductive device during a previous switch cycle. The OFF-time during a present switch cycle is dynamically adjusted in accordance with a falling rate of the output voltage during the present switch cycle.

[0016] The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

[0017] FIG. 1 is a circuit block diagram showing a PFM control circuit according to the present invention. Referring to FIG. 1, under control of a PFM control circuit 10, a switching regulator 20 is able to convert a susceptible input voltage V_in into a regulated output voltage V_out and supply a current required by a load 30 through an output terminal A. It should be noted that although the switching regulator 20 shown in FIG. 1 has a boost topology, the present invention is not limited to this and may be applied to a buck topology or any other topologies. Moreover, although the switching regulator 20 shown in FIG. 1 has a non-synchronous switching circuit consisting of a switching transistor SW and a diode D, the present invention is not limited to this and may be applied to a synchronous switching circuit consisting of two switching transistors.

[0018] The PFM control circuit 10 includes a pulse generating circuit 11, a current sensing circuit 12, and a voltage sensing circuit 13. The pulse generating circuit 11 outputs a pulse control signal PC for controlling the switching transistor SW of the switching regulator 20. The pulse control signal PC is formed of a plurality of switch cycles, one by one consecutively associated with each other. Each of the switch cycles has a first level state and a second level state. The first level state is applied to turn on the switching transistor SW, which is hereinafter referred to as an ON-time, while the second level state is applied to turn off the switching transistor SW, which is hereinafter referred to as an OFF-time. The current sensing circuit 12 generates a current detection signal I_sen representative of an inductive current I_L flowing through an inductive device L. The voltage sensing circuit 13 generates a voltage detection signal V_sen representative of the output voltage V_out. In response to the current detection signal I_sen and the voltage detection signal V_sen, the pulse generating circuit 11 dynamically adjusts the ON-time and the OFF-time of the pulse control signal PC each switch cycle, thereby effectively converting voltages with high efficiency over broad loading requirements.

[0019] In one embodiment, the current sensing circuit 12 may be implemented by a series-connected resistor, across which a potential difference caused by the inductive current I_L serves as the current detection signal I_sen. In another embodiment, the current sensing circuit 12 may be implemented in accordance with U.S. Pat. No. 6,791,368, entitled “Current Sensing Circuit And Method Of A High-Speed Driving Stage,” issued to the assignee of the present application, which is fully incorporated herein by reference. In one embodiment, the voltage sensing circuit 13 may be implemented by a resistive voltage divider, coupled between the output terminal A of the switching regulator 20 and a ground potential, for providing a division of the output voltage V_out as the voltage detection signal V_sen. Further descriptions would be omitted since the current sensing circuit 12 and the voltage sensing circuit 13 are well known by one skilled in the art.

[0020] The pulse generating circuit 11 includes a reference ON-time setting circuit 15, an ON-time adjusting circuit 16, a reference OFF-time setting circuit 17, an OFF-time adjusting circuit 18, and a latch circuit 19. The reference ON-time setting circuit 15 provides a predetermined reference ON-time to serve as a lower limit of a practically-applied ON-time every switch cycle. Based on the current detection signal I_sen of the current sensing circuit 12, the ON-time adjusting circuit 16 dynamically adjusts the practically-applied ON-time every switch cycle. More specifically, the practically-applied ON-time is prolonged in response to an increase of a maximum of the current detection signal I_sen, thereby improving the voltage converting efficiency in the heavy loading operation. The reference OFF-time setting circuit 17 provides a predetermined reference OFF-time to serve as a lower limit of a practically-applied OFF-time every switch cycle. Based on the voltage detection signal V_sen of the voltage sensing circuit 13, the OFF-time adjusting circuit 18 dynamically adjusts the practically-applied OFF-time every switch cycle. More specifically, the practically-applied OFF-time is prolonged in response to a reduction of a falling rate of the voltage detection signal V_sen, thereby improving the voltage converting efficiency in the light loading operation. Under the triggers of the practically-applied ON-time and OFF-time, the latch circuit 19 generates the pulse control signal PC for controlling the switching transistor SW of the switching regulator 20.

[0021] FIG. 2 is a flow chart showing a PFM control method according to the present invention. Referring to FIG. 2, the PFM control method according to the present invention includes an ON-time operation period OP_on and an OFF-time operation period OP_off, both of which together form a switch cycle. During the ON-time operation period OP_on, the switching transistor SW of the switching regulator 20 is turned on such that energy from the input voltage V_in is supplied to the inductive device L, causing the inductive current I_L to flow and gradually rise. During the OFF-time operation period OP_off, the switching transistor SW of the switching regulator 20 is turned off such that the energy stored in the inductive device L is delivered to the load 30, causing the inductive current I_L to gradually fall.

[0022] In a step S1, the switching transistor SW is turned on to initiate a new ON-time operation period OP_on. In a step S2, the inductive current I_L is detected so as to obtain information about the loading requirement. The practically-applied ON-time is dynamically adjusted in accordance with the current detection signal I_sen indicative of the loading requirement. In a step S3, it is determined whether the switching transistor SW has been maintained at the conductive state for the practically-applied ON-time or not. If no, then the switching transistor SW is still maintained at the conductive state in a step S4. As soon as the switching transistor SW has been maintained at the conductive state for the practically-applied ON-time, the switching transistor SW is turned off in a step S5. In other words, the ON-time operation period OP_on is finished and an OFF-time operation period OP_off is initiated. In a step S6, it is determined whether the switching transistor SW has been maintained at the non-conductive state for the predetermined reference OFF-time or not. If no, then the switching transistor SW is still maintained at the non-conductive state in a step S7. As soon as the switching transistor SW has been maintained at the non-conductive state for the predetermined reference OFF-time, it is further determined whether the voltage detection signal V_sen representative of the output voltage V_out has fallen below a predetermined reference voltage V_ref or not in a step S8. If no, then the switching transistor SW is still maintained at the non-conductive state in a step S9. As soon as the voltage detection signal V_sen falls below the reference voltage V_ref, the switching transistor SW is turned on again, back to the step S1. In other words, the OFF-time operation period OP_off is finished and a new ON-time operation period OP_off of a next switch cycle is initiated.

[0023] FIG. 3 is a waveform timing chart showing operations of a PFM voltage regulator according to the present invention. A curve I_L-1 illustrates a waveform of an inductive current according to the present invention in a light loading operation, a medium loading operation, and a heavy loading operation. A curve PC-1 illustrates a waveform of a pulse control signal according to the present invention in a light loading operation, a medium loading operation, and a heavy loading operation. For appropriate appreciation of the high efficiency over broad loading requirements achieved according to the present invention, waveforms of a conventional PFM voltage regulator are also illustrated in FIG. 3 for the sake of comparison. A curve I_L-2 illustrates a waveform of a prior art inductive current in a light loading operation, a medium loading operation, and a heavy loading operation. A curve PC-2 illustrates a waveform of a prior art pulse control signal in a light loading operation, a medium loading operation, and a heavy loading operation.

[0024] In the heavy loading operation, an average of the inductive current I_L-1 should be elevated to a higher value so as to satisfy the requirement of a larger loading current. Since the practically-applied ON-time of the pulse control signal PC-1 is dynamically adjusted in accordance with the loading requirement, the practically-applied ON-time according to the present invention is prolonged in the heavy loading operation such that the inductive current I_L-1 is allowed to reach a higher value during a single switch cycle. As a result, the necessary number of the switch cycles of the pulse control signal PC-1 according to the present invention is effectively prevented from increasing in the heavy loading operation. To the contrary, the prior art constant ON-time PFM mode has a lower efficiency caused by a relatively large number of the switch cycles of the pulse control signal PC-2 since the prior art ON-time fails to be adjusted in accordance with the loading requirement.

[0025] In the light loading operation, the output voltage V_out falls with a relatively slow rate during the OFF-time due to a small requirement for the loading current. Since the practically-applied OFF-time is dynamically adjusted in accordance with the determination of the voltage detection signal V_sen falling below the reference voltage V_ref, the practically-applied OFF-time is prolonged from the reference OFF-time in the light loading operation. As a result, the necessary number of the switch cycles of the pulse control signal PC-1 according to the present invention is effectively prevented from increasing in the light loading operation. To the contrary, the prior art constant OFF-time PFM mode has a lower efficiency caused by a relatively large number of the switch cycles of the pulse control signal PC-2 since the prior art OFF-time fails to be adjusted in accordance with the loading requirement.

[0026] FIG. 4 is a detailed circuit diagram showing one example of a pulse generating circuit 11 according to the present invention. The latch circuit 19 has an output terminal Q for supplying the pulse control signal PC. Now assumed that the voltage detection signal V_sen is lower than the reference voltage V_ref, a new ON-time operation period OP_on is initiated. That is, a high voltage level is asserted at the output terminal Q of the latch circuit 19 for turning on the switching transistor SW of the switching regulator 20. On the other hand, the high voltage level at the output terminal Q of the latch circuit 19 is inverted to become a low voltage level for turning off a switch N1 of the reference ON-time setting circuit 15, thereby causing a reference current source I_on to start charging a capacitor C_on. At the same time, a voltage-controlled variable current source I_vc of the ON-time adjusting circuit 16 is used to discharge the capacitor C_on. Under such a circumstance, a rising rate of a potential difference across the capacitor C_on is slowed down because of the sinking from the variable current source I_vc. The larger the variable current source I_vc, the later in time the potential difference across the capacitor C_on reaches a predetermined reference voltage V_on. As a result, a comparator CP1 is triggered at a later time than that when otherwise only the reference current source I_on is allowed to charge. That is, an effect on prolonging the practically-applied ON-time is achieved by the ON-time adjusting circuit 16. When the potential difference across the capacitor C_on reaches the reference voltage V_on, the comparator CP1 is triggered such that the high voltage level asserted at the output terminal Q of the latch circuit 19 is changed to a low voltage level. To sum up, the practically-applied ON-time during which the high voltage level is asserted at the output terminal Q of the latch circuit 19 is dynamically adjusted by the ON-time adjusting circuit 16 in accordance with the current detection signal I_sen.

[0027] As clearly seen from careful observations, the current detection signal I_sen is such an oscillating waveform that increases during the ON-time operation period OP_on and decreases during the OFF-time operation period OP_off. Consequently, in the embodiment shown in FIG. 4, the ON-time adjusting circuit 16 employs a sample-and-hold circuit for sampling a maximum of the current detection signal I_sen during a previous switch cycle, and then holding it as a control voltage for the variable current source I_vc to dynamically adjust the practically-applied ON-time during the present switch cycle. More specifically, during the ON-time operation period OP_on, the high voltage level at the output terminal Q of the latch circuit 19 turns on a transmission gate G1 and turns off a transmission gate G2, thereby allowing a capacitor C1 to retrieve a maximum of the current detection signal I_sen immediately before the ON-time is finished. Subsequently during the OFF-time operation period OP_off of the same switch cycle, the low voltage level at the output terminal Q of the latch circuit 19 turns off the transmission gate G1 and turns on the transmission gate G2, thereby transferring the maximum sampled on the capacitor C1 to a capacitor C2 and holding it thereon. When an ON-time operation period OP_on of a next switch cycle is initiated, the maximum held on the capacitor C2 is utilized to control the variable current source I_vc for dynamically adjusting the practically-applied ON-time.

[0028] After the OFF-time operation period OP_off is initiated, a low voltage level at the output terminal Q of the latch circuit 19 turns off the switching transistor SW of the switching regulator 20 and also turns off a switch N2 of the reference OFF-time setting circuit 17, thereby causing a reference current source I_off to start charging a capacitor C_off. When a potential difference across the capacitor C_off reaches a predetermined reference voltage V_off, a comparator CP2 is triggered to notify the latch circuit 19 that a reference OFF-time has been past so far. However, the output terminal Q of the latch circuit 19 is not guaranteed to change from a low voltage level to a high voltage level simply because the comparator CP2 is triggered since the operation of the OFF-time adjusting circuit 18 should also be taken into consideration. More specifically, the OFF-time adjusting circuit 18 is implemented by a comparator CP3 for comparing the voltage detection signal V_sen and the reference voltage V_ref. When the voltage detection signal V_sen is lower than the reference voltage V_ref, the comparator CP3 is triggered such that the output terminal Q of the latch circuit 19 is changed to a high voltage level. To sum up, the practically-applied OFF-time during which the low voltage level is asserted at the output terminal Q of the latch circuit 19 is dynamically adjusted by the OFF-time adjusting circuit 18 in accordance with the voltage detection signal V_sen.

[0029] While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.