AM to FM correction system for a polar modulator

[0001] The present invention relates to controlling a power amplifier, and more particularly to controlling the power amplifier during polar modulation.

[0002] Transmitters form a significant portion of most communication circuits. As such, they assume a position of prominence in design concerns. With the proliferation of mobile terminals, transmitter design has progressed in leaps and bounds as designers try to minimize components and reduce size, power consumption, and the like. Likewise, modulation schemes are continuously updated to reflect new approaches to maximize information transfers within limited bandwidth constraints. Changes in standards or standards based on newly available spectrum may also cause designers to approach modulator designing with different techniques.

[0003] Many different standards and modulation schemes exist, but one of the most prevalently used in the world of mobile terminals is the Global System for Mobile Communications (GSM). GSM comes in many flavors, not the least of which is General Packet Radio Services (GPRS). GPRS is a new non-voice value-added service that allows information to be sent and received across a mobile telephone network. It supplements today's Circuit Switched Data and Short Message Service. GSM allows many different types of mobile terminals, such as cellular phones, pagers, wireless modem adapted laptops, and the like, to communicate wirelessly through the Public Land Mobile Network (PLMN) to the Public Switched Telephone Network (PSTN).

[0004] One relatively recent change has been the advent of the Enhanced Data for GSM Evolution (EDGE) scheme in GSM systems. This system contains amplitude modulation components, and, as a result, the power amplifier must be linear and should not operate in saturation when classical modulation techniques are employed. Such a linear system lacks the efficiency of one that operates the power amplifier in saturation.

[0005] If a polar modulation system is used instead of a classical modulation system, then the power amplifier may operate in saturation and efficiency is greatly improved. In addition, if the polar signals are generated by a digital method, such a system does not require the use of a quadrature modulator. Quadrature modulators are undesirable from a design standpoint in that they draw large amounts of current, and hence, drain batteries comparatively fast.

[0006] In a polar modulation system, the amplitude signal that controls the power amplifier will cause unwanted phase components to be created in the output of the power amplifier due to the non-linearities of the power amplifier. This is sometimes called amplitude to phase (AM to PM) distortion, and it degrades the spectral purity of the system and the Error Vector Magnitude. Thus, a need also exists to be able to compensate for the unwanted AM to PM distortion of the transmitted phase signal.

[0007] One solution used to compensate for AM to PM distortion is to measure the AM to PM distortion of the power amplifier, and then create a polynomial for phase predistortion that is used to distort a signal prior to amplification by the power amplifier. This predistortion offsets the AM to PM distortion of the power amplifier. However, the polynomial is often at least a third order polynomial and is costly to implement. Thus, there remains a need for a more cost effective system for correcting AM to PM distortion of a power amplifier.

[0008] The present provides a transmitter for a mobile terminal including a polar modulator that compensates for amplitude to frequency distortion (AM to FM distortion) of a power amplifier in the transmit chain. In doing so, a frequency component of an amplitude to phase distortion (AM to PM distortion) of the power amplifier is counteracted such that only a constant phase offset remains in an output of the power amplifier. This constant phase offset is easily compensated for in an associated receiver.

[0009] In general, the modulator includes a polar converter that converts an input signal into an amplitude signal and a phase signal. A phase to frequency converter converts the phase signal into a frequency signal. Based on the amplitude signal, compensation circuitry generates a frequency compensation signal that is combined with the frequency signal and essentially cancels that AM to FM distortion of the power amplifier. The pre-distorted signal is amplified by the power amplifier, and the frequency compensation signal essentially cancels the AM to FM distortion of the power amplifier.

[0010] The compensation circuitry generates the frequency compensation signal based on the amplitude signal and a polynomial defined by a set of coefficients. More particularly, in one embodiment, the compensation circuitry generates the frequency compensation signal based on a product of the polynomial and a derivative of the amplitude signal. The coefficients are such that the product of the polynomial and the derivative of the amplitude signal, and thus the frequency compensation signal, is essentially a derivative of a function that essentially cancels an AM to PM distortion of the power amplifier. Thus, the frequency compensation signal essentially cancels the AM to FM distortion of the power amplifier.

[0011] In another embodiment, the compensation circuitry generates the frequency compensation signal based on the amplitude signal and an output power level of the power amplifier. In this embodiment, the frequency compensation signal is generated based on a set of coefficients selected from numerous set of coefficients based on the output power level of the power amplifier. Each of the sets of coefficients defines a polynomial corresponding to one of the output power levels of the power amplifier. The sets of coefficients are provided based on different predistortion criteria for each output power level. In one embodiment, each of the sets of coefficients is provided such that a product of the polynomial defined by the set of coefficients and a derivative of the amplitude signal essentially the inverse of the AM to FM distortion of the power amplifier for the corresponding output power level.

[0012] Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] While the present invention is particularly well-suited for use in a mobile terminal, and particularly a mobile terminal that is operating in an Enhanced Data for GSM Evolution (EDGE) scheme in a GSM system, it should be appreciated that the present invention may be used in other transmitters, either wireless or wirebased, as needed or desired.

[0022] The present invention is preferably incorporated in a mobile terminal 10, such as a mobile telephone, personal digital assistant, or the like. The basic architecture of a mobile terminal 10 is represented in FIG. 1, and may include a receiver front end 12, a radio frequency transmitter section 14, an antenna 16, a duplexer or switch 18, a baseband processor 20, a control system 22, memory 24, a frequency synthesizer 26, and an interface 28. The receiver front end 12 receives information bearing radio frequency signals from one or more remote transmitters provided by a base station (not shown). A low noise amplifier 30 amplifies the signal. A filter circuit 32 minimizes broadband interference in the received signal, while a downconverter 34 downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams. The receiver front end 12 typically uses one or more mixing frequencies generated by the frequency synthesizer 26.

[0023] The baseband processor 20 processes the digitized, received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. As such, the baseband processor 20 is generally implemented in one or more digital signal processors (DSPs).

[0024] On the transmit side, the baseband processor 20 receives digitized data from the control system 22, which it encodes for transmission. The control system 22 may run software stored in the memory 24. Alternatively, the operation of the control system 22 may be a function of sequential logic structures as is well understood. After encoding the data from the control system 22, the baseband processor 20 outputs the encoded data to the radio frequency transmitter section 14. A modulator 36 receives the encoded data and operates according to a polar modulation scheme to provide a phase component (φ) at a desired transmit frequency and an amplitude component (r) for controlling an output power of the power amplifier circuitry 38 via the power control circuitry 40. As described below in detail, one or both of the phase component (φ) and the amplitude component (r) are pre-distorted by the modulator 36. The memory 42 may be used to store coefficients of multiple polynomials used by the modulator 36 for pre-distorting one or both of the phase component (φ) and the amplitude component (r).

[0025] The power amplifier circuitry 38 amplifies the phase component (φ) to a level appropriate for transmission from the antenna 16. A gain of the power amplifier circuitry 38 is controlled by the power control circuitry 40, which is controlled by the amplitude component (r) from the modulator 36. Thus, in essence, the power control circuitry 40 operates to control a supply voltage provided to the power amplifier circuitry 38 based on the amplitude component (r) from the modulator 36, thereby controlling an output power of the power amplifier 38 based on the amplitude component (r). It should be noted that, in this embodiment, the modulator 36 may also operate to adjust the amplitude component (r) based on an adjustable power control signal (V_RAMP) from the control system 22.

[0026] A user may interact with the mobile terminal 10 via the interface 28, which may include interface circuitry 44 associated with a microphone 46, a speaker 48, a keypad 50, and a display 52. The interface circuitry 44 typically includes analog-to-digital converters, digital-to-analog converters, amplifiers, and the like. Additionally, it may include a voice encoder/decoder, in which case it may communicate directly with the baseband processor 20.

[0027] The microphone 46 will typically convert audio input, such as the user's voice, into an electrical signal, which is then digitized and passed directly or indirectly to the baseband processor 20. Audio information encoded in the received signal is recovered by the baseband processor 20, and converted into an analog signal suitable for driving speaker 48 by the interface circuitry 44. The keypad 50 and display 52 enable the user to interact with the mobile terminal 10, input numbers to be dialed and address book information, or the like, as well as monitor call progress information.

[0028] While the present invention is well-suited for incorporation into a mobile terminal, such as the mobile terminal 10 just described, it should be noted that the present invention is well-suited for use in any wireless transmitter. Types of wireless transmitters include the transmitter section 14 of the mobile terminal 10, a wireless transmitter associated with a wireless LAN, and the like. As such, the present invention is not limited to a particular apparatus.

[0029] In the past, as illustrated in FIG. 2, the modulator 36 directed two signals to the power amplifier 38. In an exemplary prior art embodiment, a polar modulator 36 directed an amplitude signal (r) and a phase signal (φ) to the power amplifier 38. The amplitude signal (r) controlled the power supply voltage of the power amplifier 38, potentially replacing or including the power control circuitry 40, while the phase signal (φ) was amplified by the power amplifier 38 to create A_DESIRED φ_DESIRED. The output (A_o φ_o) of the power amplifier 38 was corrupted by AM to PM distortion within the non-linear power amplifier 38, represented by φ(r), and AM to AM distortion, represented by A(r), resulting in an output signal of A_DESIRED*A(r) φ_DESIRED + φ(r).

[0030] Before discussing the modulator 36 of the present invention, which is illustrated in FIG. 5, it is beneficial to discuss one embodiment of the modulator 36 that corrects both the AM to PM distortion and the AM to AM distortion illustrated in FIG. 3. This embodiment is essentially the same as that disclosed and described in commonly owned and assigned U.S. patent application Ser. No. 10/147,569 entitled AM TO PM CORRECTION SYSTEM FOR POLAR MODULATOR filed May 16, 2002, which is hereby incorporated by reference in it entirety. In general, the modulator 36 corrects the AM to PM distortion within the output by preliminarily distorting the phase signal (φ) such that when it is converted to a frequency signal and amplified by the power amplifier 38, the predistortion element cancels the AM to PM distortion element introduced by the amplitude signal (r). The modulator 36 corrects the AM to AM distortion within the output by preliminarily distorting the amplitude signal (r) such that the predistortion element cancels the AM to AM distortion element introduced by the amplitude signal (r).

[0031] More specifically, the radio frequency transmitter section 14, and particularly the modulator 36, includes several components, including a serial interface 54, a mapping module 56, first and second filters 58, 60, and a polar converter 62. Other components of the modulator 36 will be discussed below. The serial interface 54 receives Non-Return to Zero (NRZ) serial data from the baseband processor 20 at the bit rate of the system. For example, NRZ serial data may be a 1B1B code with one line bit for each associated binary bit. In an exemplary embodiment, the modulation scheme for the modulator 36 uses an EDGE modulation scheme, and thus, the bit rate is 812.5 kbps. This data is passed to the mapping module 56, where the data is grouped into symbols of three consecutive data bits, Grey coded, and rotated by 3π/8 on each symbol as per European Telecommunications Standards Institute (ETSI) specifications. The resulting symbol is mapped to one of sixteen points in an I, Q constellation.

[0032] Both the I and the Q components for each point are then filtered by the first and second filters 58, 60 respectively. In an exemplary embodiment, the first and second filters 58, 60 are EDGE finite impulse response (FIR) filters. This, as dictated by the ETSI specifications, shapes the response between symbol times.

[0033] After filtering, both the I and Q components are sent to the polar converter 62. The polar converter 62 uses a classical CORDIC (coordinate rotation digital computer) algorithm or like rectangular to polar conversion technique. Thus, the polar converter 62 generates phase (φ) and amplitude (r) equivalent signals. Further information about CORDIC algorithms may be found in Proceedings of the 1998 ACM/SIGDA Sixth International Symposium On Field Programmable Gate Arrays by Ray Andraka, Feb. 22-24, pp.191-200 and “The CORDIC Trigonometric Computing Technique” by Jack E. Volder IRE Trans on Elect. Computers, p.330, 1959, both of which are hereby incorporated by reference in their entirety.

[0034] The amplitude signal (r) is split and directed to AM to PM compensation circuitry 64. The AM to PM compensation circuitry 64 introduces a compensation term to the phase signal (φ) that, after further processing, counteracts the distortion introduced by the AM to PM distortion in the power amplifier 38.

[0035] The AM to PM compensation circuitry 64 acts to create a polynomial along the lines of the following equation:

[0036] ${\varphi }^{\prime }\left(r\right)=\sum _{i=0}^M{C_i\left(r\left(n\right)\right)}^i$

[0037] As an example, if M=3, the equation expands to the following:
φ′(r)=C₀+C₁r(n)+C₂(r(n))²+C₃(r(n))³
where φ′(r) is termed herein a phase compensation signal and r(n) is a digital representation of the amplitude signal (r) and may alternatively be replaced by a continuous-time representation r(t). It is readily apparent that φ′(r) has an offset term, a linear term, a quadratic term, and a cubic term selectable by the hardware implementation.

[0038] In an exemplary embodiment of the present invention, the coefficients C_i are associated with the control system 22, and particularly stored in non-volatile memory 24 associated therewith. Alternatively, the coefficients may be stored in the memory 42 if such is present. In an exemplary embodiment, the coefficients may be stored as a look up table. It is further possible that the coefficients are stored as a function of sequential steps performed by hardware. The coefficients are determined through a best fit analysis of a function that substantially matches the unamplified inverse of the AM to PM distortion φ(r). In another embodiment, a piecewise function is created with each piece being determined by a given power level. This is done to improve the fit between the functions. For example, if only one set of coefficients were used, φ′(r) might not fit well at the ends or perhaps in the middle of the relevant range of values. By implementing a piecewise function, a good fit between the equations may be achieved throughout the curve of relevant values. In an exemplary embodiment, a set of coefficients is created for each 2 dBm power step. This corresponds to the power steps defined in the ETSI standards. To calculate the coefficients, a program such as MATHCAD may be used to derive a match to an empirical power amplifier curve. The coefficients may be tested through an ADS simulation or the like.

[0039] The output of the AM to PM compensation circuitry 64 is subtracted from the phase signal (φ) by an adder 66 to create a pre-distorted signal. The adder 66 is also termed herein a combiner. The output of the adder 66 (the pre-distorted signal) is directed to a phase to frequency converter 68 where the output is converted to a frequency signal (f). More detail on the phase to frequency converter 68 is provided below with reference to FIG. 4.

[0040] Similarly, the amplitude component (r) is provided to AM to AM compensation circuitry 70. The AM to AM compensation circuitry 70 introduces a compensation term to the amplitude signal (r) that, after further processing, counteracts the distortion introduced by the AM to AM distortion in the power amplifier 38.

[0041] The AM to AM compensation circuitry 70 acts to create a polynomial along the lines of the following equation:

[0042] $A^{\prime }\left(r\right)=\sum _{i=0}^M{C_i\left(r\left(\right)\right)}^i$

[0043] As an example, if M=3, the equation expands to the following:
A′(r)=C₀+C₁r(n)+C₂(r(n))²+C₃(r(n))³
where A′(r) is termed herein an amplitude compensation signal. It is readily apparent that A′(r) has an offset term, a linear term, a quadratic term, and a cubic term selectable by the hardware implementation. In an exemplary embodiment, the offset term C₀ and the coefficient for the linear term C₁ are zero. An offset term would act the same as increasing or decreasing the output power level. Since the adjustable power control signal (V_RAMP) addresses this, it is not necessary to repeat the control here. Likewise, a linear term would only change the fundamental amplitude and not change the shape of the curve, so a linear term for this compensation signal makes little sense.

[0044] When the exemplary embodiment A′(r) is combined with r(n) in the adder 72, the pre-distorted signal is:
r′(n)=r(n)+C₂(r(n))²+C₃(r(n))³
which converts to the following:
r′(n)=r(n)*[1+C₂(r(n))+C₃(r(n))^2]
Thus, even though the adder 72 is an adder, the effect is to multiply the term r(n) by a correction factor that deviates from unity by A′(r). This signal then passes through the power amplifier 38 with AM to AM distortion. This distortion, as previously noted, is A(r). The goal is thus to make the term [1+C₂(r(n))+C₃(r(n))²] the inverse of the AM to AM distortion such that A(r)*[1+C₂(r(n))+C₃(r(n))²]=1. When this condition is true, the AM to AM distortion has been canceled.

[0045] Alternatively, if the adder 72 were instead a multiplier, then the correction terms could have a linear term and an offset term. From a design standpoint, this removes a multiplier from the AM to AM compensation circuitry 70 and inserts a multiplier in place of the adder 72. The concept of canceling the AM to AM distortion with its inverse remains the same.

[0046] In an exemplary embodiment, the coefficients Ci for the polynomial defining A′(r) are associated with control system 22, and particularly in non-volatile memory 24 associated therewith. Alternatively, the coefficients may be stored in the memory 42, if such is present. In another exemplary embodiment, the coefficients may be stored in a look up table or the like. It is further possible that the coefficients are created as a function of hardware. The coefficients are determined through a best fit analysis of a function that matches the expected AM to AM distortion A(r). In a more preferred embodiment, a piecewise function is created with each piece being determined by a given power level. This is done to improve the fit between the functions. For example, if only one set of coefficients were used, A′(r) might not fit well at the ends or perhaps in the middle of the relevant range of values. By implementing a piecewise function, a good fit between the equations may be achieved throughout the curve of relevant values. In an exemplary embodiment, a set of coefficients is created for each 2 dBm power step. This corresponds to the power steps defined in the ETSI standards.

[0047] To calculate the coefficients, a program such as MATHCAD may be used to derive a match to an empirical power amplifier curve. The coefficients may be tested through an ADS simulation or the like.

[0048] After compensation of the amplitude signal (r) and conversion of the compensated phase signal (φ) to the frequency signal (f), magnitude adjusters 74, 76 adjust the magnitude of the amplitude signal (r) and the frequency signal (f) to a level expected by the time aligner 78, such that they comply with the appropriate standard. Next, a relative time delay is applied as necessary to the signals for best Error Vector Magnitude (EVM) and spectrum by the time aligner 78. Because these are preferably digital components, concerns about variations in analog components and the corresponding variation in time delays downstream are minimized.

[0049] At this point, the amplitude signal (r) and the frequency signal (f) separate and proceed by different paths, an amplitude signal processing path and a frequency signal processing path, to the power amplifier 38. With respect to the amplitude signal processing path, the amplitude signal is converted to an analog signal by D/A converter 80. While not shown, a ramping function may be combined with the amplitude signal prior to digital-to-analog conversion. The output of the D/A converter 80 is used to by the power control circuitry 40 to set the collector voltage on the power amplifier 38. As the amplitude signal changes, the voltage at the collector of the power amplifier 38 changes, and the output power will vary as V²/R_out (R_out is not shown, but is effectively the load on the power amplifier 40). This is sometimes known as “plate modulation”.

[0050] The frequency signal is directed to a digital filter 82, a digital predistortion filter 84, and a phase locked loop (PLL) 86, as is described in commonly owned and assigned U.S. patent application Ser. No. 10/139,560, filed 06 May 2002, entitled DIRECT DIGITAL POLAR MODULATOR, which is hereby incorporated by reference in its entirety. The PLL 86 generates an output at the desired radio frequency. In an exemplary embodiment, the frequency signal is applied to a single port on a fractional N divider within the PLL 86.

[0051] In general, the PLL 86 operates to convert the frequency signal (f), which is a digital signal, into an analog frequency signal. The PLL 86 comprises a reference source that is fed to a phase comparator. The phase comparator compares the edges of the reference source to the output of the fractional N divider and produces a correction signal. The correction signal is low pass filtered and input to a voltage controlled oscillator (VCO). The VCO outputs a frequency modulated signal at the RF carrier, which in turn is fed back to the fractional N divider. The divisor of the fractional N divider is modulated by the frequency signal. Further information on fractional N PLLs, how to modulate a signal by varying the fractional N divider, and the like may be found in U.S. Pat. Nos. 6,359,950; 6,236,703; 6,211,747; 5,079,522; 5,055,802; and 4,609,881 which are hereby incorporated by reference in their entireties.

[0052] The phase to frequency converter 68 is explicated with reference to FIG. 5. The phase signal (φ) arrives and is split into a delay path and a normal path. A clock 88 controls a delay element 90 in the delay path. The output of the delay element 90 is subtracted from the normal path by adder 92. The output of the adder 92 is multiplied by 2π in a multiplier 94, and a frequency signal (f) is output. This structure takes advantage of the relationship

[0053] $f=2\pi \frac{d\varphi }{dt}$
in a digital sense. The delay and the subtraction approximates the derivative as (φ(n)−φ(n−1))/T, where T is the period for the clock 88. Other phase to frequency conversions could also be used if needed or desired.

[0054] Since the adder 66 sums the phase signal (φ) and the phase compensation signal (φ′), the phase to frequency converter 68 effectively approximates a derivative of both the phase signal (φ) and the phase compensation signal (φ′). However, the approximation of the derivative of the phase compensation signal (φ′) creates a small error. More specifically, the approximate derivative of the phase compensation signal (φ′) produced by the phase to frequency converter 68 is:

[0055] $\frac{d\left({\varphi }^{\prime }\right)}{dt}\cong f_{\mathrm{SAMP}}*\left[{\varphi }^{\prime }\left(n\right)-{\varphi }^{\prime }\left(n-1\right)\right],$
where f_SAMP is a sampling frequency and defines a time between the n and n−1 samples. Since in an exemplary embodiment the phase compensation signal (φ′) may be defined as:
φ′+(n)=C₁*r(n)+C₂ *r²(n)+C₃*r³(n),
the equation expands to:

[0056] $\frac{d\left({\varphi }^{\prime }\right)}{dt}\cong f_{\mathrm{SAMP}}*\left\{C_1*\left[r\left(n\right)-r\left(n-1\right)\right]+C_2*\left[r^2\left(n\right)-r^2\left(n-1\right)\right]+C_3*\left[r^3\left(n\right)-r^3\left(n-1\right)\right]\right\}$ $\frac{d\left({\varphi }^{\prime }\right)}{dt}\cong f_{\mathrm{SAMP}}*\left[r\left(n\right)-r\left(n-1\right)\right]*\left\{C_1+C_2\left[r\left(n\right)+r\left(n-1\right)\right]+C_3\left[r^2\left(n\right)+r^2\left(n-1\right)+r\left(n\right)*r\left(n-1\right)\right]\right\}$
and if
Δr(n)=r(n)−r(n−1),
then

[0057] $\frac{d\left({\varphi }^{\prime }\right)}{dt}\cong f_{\mathrm{SAMP}}*\Delta r\left(n\right)*\left\{C_1+C_2\left[r\left(n\right)+r\left(n-1\right)\right]+C_3\left[r^2\left(n\right)+r^2\left(n-1\right)+r\left(n\right)*r\left(n-1\right)\right]\right\},$
where, for the C₂ term,
r(n)+r(n−1)=2r(n)−Δr(n).
However, ideally

[0058] $\frac{d\left({\varphi }^{\prime }\right)}{dt}\cong \frac{d\left(r\right)}{dt}*\left\{C_1+C_2*2*r\left(n\right)+C_3*3*r^2\left(n\right)\right\},\mathrm{where}$ $\frac{d\left(r\right)}{dt}\cong f_{\mathrm{SAMP}}*\Delta r\left(n\right).$
Thus, ideally, the C₂ term is C₂*2*r(n). However, the approximation of the derivative of the phase compensation signal (φ′) produces the C₂ term as C₂*[2*r(n)−Δr(n)]. Accordingly, the approximation of the derivative of the phase compensation signal (φ′) produces an error of −Δr(n) in the C₂ term. Similarly, an error is produced for the C₃ term.

[0059] FIG. 5 illustrates the modulator 36 according to one embodiment of the present invention. In general, the modulator 36 operates to provide AM to FM compensation rather than AM to PM compensation. In doing so, the phase to frequency conversion occurs prior to compensation, thereby eliminating the errors created by the phase to frequency conversion after compensation described above. In addition, the polynomial used for AM to FM compensation is one order less than the polynomial used for the AM to PM compensation described above.

[0060] More specifically, the modulator 36 includes the data interface 54, the mapping module 56, the filters 58, 60, and the polar converter 62, as described above. The modulator 36 also includes the AM to AM compensation circuitry 70 and the adder 72 for compensating the amplitude signal (r) to essentially cancel the AM to AM distortion of the power amplifier 38. Since these components operate as described above, they are not described again for conciseness. However, it should be noted that the AM to AM compensation circuitry 70 and the adder 72 are optional components and are not necessary for the present invention.

[0061] According to the present invention, the phase signal (φ) is first passed to the phase to frequency converter 68. AM to FM compensation circuitry 96 acts to create a frequency compensation signal (f′) defined as:

[0062] $f\left(r\right)=\frac{d\left({\varphi }^{\prime }\left(r\right)\right)}{dt}.$
As an example, if N=3 and
φ′(r)=C₀+C₁r(n)+C₂(r(n))²+C₃(r(n))³
then

[0063] $f\left(r\right)=\frac{d\left({\varphi }^{\prime }\left(r\right)\right)}{dt}=\left[C_1+2C_2\left(r\left(n\right)\right)+3{C_3\left(r\left(n\right)\right)}^2\right]*\Delta r\left(n\right)*f_{\mathrm{SAMP}}.$
Thus, the frequency compensation signal (f′) includes a polynomial term, which in this example is C₁₊2C₂(r(n))+3C₃(r(n))² multiplied by the derivative of the amplitude signal (r), which is approximated by Δr(n)*f_SAMP. Further, the polynomial in the equation for the frequency compensation signal (f′) is one order less than the polynomial defining the phase compensation signal (φ′). In this example, the polynomial defining the frequency compensation signal (f′) is second order while the polynomial defining the phase compensation signal (φ′) is third order. Thus, the complexity of the modulator 36 is reduced and the size of the memory 24 or 42 that stores the coefficients for the polynomials for various power levels is further reduced. Further, since the phase signal (φ) is converted to the frequency signal (f) before compensation, the errors caused by the approximation of the derivative of the phase compensation signal (φ′) described with respect to FIGS. 3 and 4 are eliminated.

[0064] In an exemplary embodiment of the present invention, the coefficients C_i in the equation for the frequency compensation signal (f′) are associated with the control system 22, and particularly stored in non-volatile memory 24 associated therewith. Alternatively, the coefficients may be stored in the memory 42 if such is present. In an exemplary embodiment, the coefficients may be stored as a look up table. It is further possible that the coefficients are stored as a function of sequential steps performed by hardware. The coefficients are determined through a best fit analysis of a function that substantially matches the unamplified inverse of an AM to FM distortion of the power amplifier circuitry 38, which is the derivative of the AM to PM distortion φ(r). In a more preferred embodiment, a piecewise function is created with each piece being determined by a given power level. This is done to improve the fit between the functions. For example, if only one set of coefficients were used, f′(r) might not fit well at the ends or perhaps in the middle of the relevant range of values. By implementing a piecewise function, a good fit between the equations may be achieved throughout the curve of relevant values. In an exemplary embodiment, a set of coefficients is created for each 2 dBm power step. This corresponds to the power steps defined in the ETSI standards. To calculate the coefficients, a program such as MATHCAD may be used to derive a match to an empirical power amplifier curve. The coefficients may be tested through an ADS simulation or the like.

[0065] The output of the AM to FM compensation circuitry 96 is subtracted from the frequency signal (f) by the adder 66 to create a pre-distorted signal. The adder 66 is also termed herein a combiner. After compensation of the amplitude signal (r) and the frequency signal (f), the magnitude adjusters 74, 76 adjust the magnitude of the amplitude signal (r) and the frequency signal (f) to a level expected by the time aligner 78, such that they comply with the appropriate standard. Next, a relative time delay is applied as necessary to the signals for best Error Vector Magnitude (EVM) and spectrum by the time aligner 78. Because these are preferably digital components, concerns about variations in analog components and the corresponding variation in time delays downstream are minimized.

[0066] At this point, the amplitude signal (r) and the frequency signal (f) separate and proceed by different paths, the amplitude signal processing path and the frequency signal processing path, to the power amplifier 38. With respect to the amplitude signal processing path, the adjustable power control signal (V_RAMP), or a ramping function, is combined with the amplitude signal by multiplication circuitry 98 prior to digital-to-analog conversion by the D/A converter 80. It should be noted that in one embodiment, the modulator 36 generates the adjustable power control signal (V_RAMP) based on a stored ramping table and a transmit power control signal from the control system 22. In this alternative embodiment, the transmit power control signal determines a gain to be applied to the ramping function stored in the ramping table.

[0067] The output of the D/A converter 80 is used by the power control circuitry 40 to set the collector voltage on the power amplifier 38. As the amplitude signal (r) changes, the voltage at the collector of the power amplifier 38 changes, and the output power will vary as V²/R_out (R_out is not shown, but is effectively the load on the power amplifier 40).

[0068] As described above, the frequency signal (f) is directed to the digital filter 82, the digital predistortion filter 84, and the phase locked loop (PLL) 86. The PLL 86 generates an output at the desired radio frequency. In an exemplary embodiment, the frequency signal is applied to a single port on a fractional N divider within the PLL 86. The output of the PLL is provided to the power amplifier circuitry 38 where it is amplified to an appropriate level based on the supply voltage from the power control circuitry 40 and passed to the antenna 16 (FIG. 1) for transmission.

[0069] It should be noted that the AM to FM compensation scheme of FIG. 5 compensates for the change in the AM to PM distortion of the power amplifier circuitry 38 with respect to time. In other words, since the frequency compensation signal is essentially the derivative of the phase compensation signal, the coefficient C₀ of the equation for the phase compensation signal (φ′) is not included in the polynomial defining the frequency compensation signal (f′). Accordingly, the AM to FM compensation scheme produces a constant phase offset in the output of the power amplifier circuitry 38. Since the constant phase offset does not change over time due to changes in the amplitude signal (r), the constant phase offset is easily compensated for in an associated receiver.

[0070] FIG. 6 illustrates one embodiment of the AM to FM compensation circuitry 96. In general, the AM to FM compensation circuitry 96 is a hardware implementation of the equation for the frequency compensation signal (f′) given above. In this exemplary embodiment, the AM to FM compensation circuitry 96 includes polynomial signal generation circuitry 100 which generates a polynomial signal corresponding to the polynomial in the equation for the frequency compensation signal (f′). Differentiation circuitry 102 operates to produce a signal corresponding to the derivative of the amplitude signal (r). In one embodiment, the differentiation circuitry 102 is essentially the same as the phase to frequency converter 68 of FIG. 4 without the multiplier 94. Multiplication circuitry 104 operates to multiply the polynomial signal and the signal from the differentiation circuitry 102 to provide the frequency compensation signal.

[0071] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.