Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces

[0001] The present invention is directed to microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces.

[0002] Conventional die-level packaged microelectronic devices include a microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame and serve as external electrical contacts on the die through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to the terminals, the interposer substrate also includes ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.

[0003] One process for packaging a die with a ball-grid array at the die level includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding the bond-pads of the dies to the terminals of the interposer substrate, and (e) encapsulating the dies with a suitable molding compound. Mounting individual dies to interposer substrates or lead frames in the foregoing manner can be a time-consuming and expensive process. In addition, forming robust wire-bonds that can withstand the forces involved in molding processes becomes more difficult as the demand for higher pin counts and smaller packages increases. Moreover, the process of attaching individual dies to interposer substrates or lead frames may damage the bare dies. These difficulties have made the packaging process a significant factor in the production of microelectronic devices.

[0004] Another process for packaging microelectronic devices is wafer-level packaging. In this process, a plurality of microelectronic dies are formed on a wafer, and then a redistribution layer is formed over the dies. The redistribution layer can include a dielectric layer and a plurality of exposed pads formed in arrays on the dielectric layer. Each pad array is typically arranged over a corresponding die, and the pads in each array are coupled to corresponding bond-pads of the die by conductive traces extending through the dielectric layer. After forming the redistribution layer on the wafer, discrete masses of solder paste can be deposited onto the individual pads. The solder paste is then reflowed to form small solder balls or “solder bumps” on the pads. After forming the solder balls, the wafer is singulated to separate the individual microelectronic devices from each other.

[0005] Wafer-level packaging is a promising development for increasing efficiency and reducing the cost of microelectronic devices. By “pre-packaging” individual dies with a redistribution layer before cutting the wafers to singulate the dies, sophisticated semiconductor processing techniques can be used to form smaller arrays of solder balls. Additionally, wafer-level packaging is an efficient process that simultaneously packages a plurality of dies, thereby reducing costs and increasing throughput.

[0006] Conventional processes of forming a redistribution layer on a wafer include (a) depositing first and second dielectric layers on the wafer, (b) patterning and developing the second dielectric layer to form holes over the bond-pads on the dies, (c) reaction ion etching the first dielectric layer to expose the bond-pads, (d) depositing a conductive layer across the wafer, (e) forming a resist on the conductive layer, (f) patterning and developing the resist, (g) etching the exposed sections of the conductive layer to form the pads, and (h) removing the resist from the wafer. One concern with forming a redistribution layer on a wafer is that conventional processes are relatively expensive because patterning the second dielectric layer requires a first mask and patterning the resist requires a second mask. Masks are expensive and time-consuming to construct because they require very expensive photolithography equipment to achieve the tolerances required in semiconductor devices. Accordingly, there is a need to reduce the cost of forming redistribution layers.

A. Overview

[0018] The following disclosure describes several embodiments of methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer. The microfeature workpieces typically have a substrate and a terminal carried by the substrate. An embodiment of one such method includes constructing a dielectric structure on a microfeature workpiece, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

[0019] In another embodiment, a method includes (a) providing a microfeature workpiece having a substrate, a terminal carried by the substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer, and (b) selectively removing a first portion of the second dielectric layer to expose a section of the first dielectric layer over the terminal and selectively removing a second portion of the second dielectric layer adjacent to the first portion to form a recess with an intermediate depth in the second dielectric layer. The first and second portions are removed in a single process. For example, the second dielectric layer can be a photoactive layer, and the first and second portions can be removed by patterning and developing the photoactive second dielectric layer.

[0020] Another aspect of the invention is directed to microfeature workpieces. In one embodiment, a microfeature workpiece includes a substrate, a microelectronic die formed in and/or on the substrate, and a dielectric structure on the substrate. The die includes an integrated circuit and a terminal electrically coupled to the integrated circuit. The dielectric structure includes (a) a first surface facing the substrate, (b) a second surface opposite the first surface, and (c) an opening having a first portion aligned with the terminal and extending between the first and second surfaces and a second portion adjacent to the first portion and extending from the second surface to an intermediate depth. The workpiece further includes a conductive layer in the first and second portions of the opening and electrically coupled to the terminal.

[0021] Specific details of several embodiments of the invention are described below with reference to methods of forming a redistribution layer on a workpiece. Several details describing well-known structures or processes often associated with fabricating redistribution layers and/or microelectronic dies are not set forth in the following description for purposes of clarity. Also, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the elements shown and described below with reference to FIGS. 1-8. The term “microfeature workpiece” is used throughout to include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, and other features are fabricated. For example, microfeature workpieces can be semiconductor wafers, glass substrates, dielectric substrates, or many other types of substrates. Many features on such microfeature workpieces have critical dimensions less than or equal to 1 μm, and in many applications the critical dimensions of the smaller features are less than 0.25 μm or even less than 0.1 μm. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from other items in reference to a list of at least two items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or types of other features and components are not precluded.

B. Embodiments of Methods for Forming a Redistribution Layer on Microfeature Workpieces

[0022] FIGS. 1-5 illustrate stages of a method for forming a redistribution layer on a microfeature workpiece 100 in accordance with one embodiment of the invention. FIG. 1, for example, is a schematic side cross-sectional view of a portion of the workpiece 100 including a substrate 110, a plurality of microelectronic dies 120 formed in and/or on the substrate 110, and a dielectric structure 130 on the substrate 110. The substrate 110 has a first side 112 and a second side 114 opposite the first side 112. The substrate 110 is generally a semiconductor wafer, and the dies 120 are arranged in a die pattern on the wafer. The individual dies 120 include integrated circuitry 122 (shown schematically) and a plurality of terminals 124 (e.g., bond-pads) electrically coupled to the integrated circuitry 122. Although the illustrated dies 120 have the same structure, in other embodiments, the dies 120 can have different features to perform different functions.

[0023] The illustrated dielectric structure 130 includes a first dielectric layer 132 applied over the first side 112 of the substrate 110, a second dielectric layer 136 applied over the first dielectric layer 132, and a third dielectric layer 140 applied over the second dielectric layer 136. In several applications, the first dielectric layer 132 can be an oxide passivation layer, and the second dielectric layer 136 can be a nitride passivation layer. For example, the first and second dielectric layers 132 and 136 can be parylene, a low-temperature chemical vapor deposition (low-temperature CVD) material such as silicon nitride (Si₃N₄), silicon oxide (SiO₂), and/or other suitable materials. The foregoing list of dielectric materials is not exhaustive. The first and second dielectric layers 132 and 136 are generally not composed of the same material as each other, but these layers may be composed of the same material. In addition, one or both of the first and second dielectric layers 132 and 136 may be omitted and/or additional layers may be included. The first and second dielectric layers 132 and 136 can have a combined thickness of approximately 0.5 microns to 4 microns, and these layers typically have a total thickness of approximately 1 micron to 1.5 microns. The third dielectric layer 140 can be a polymer or other suitable dielectric material for forming a permanent mask on the second dielectric layer 136. The third dielectric layer 140, for example, can be a 3-micron-thick layer of polyimide. In other embodiments, the third dielectric layer 140 can have a thickness greater than or less than 3 microns and/or be composed of a different photoactive material.

[0024] FIG. 2A is a schematic side cross-sectional view of the area 2A shown in FIG. 1 after patterning and developing the third dielectric layer 140 to form a plurality of openings 150 (only one shown) at corresponding terminals 124. FIG. 2B is a top plan view of the portion of the workpiece 100 illustrated in FIG. 2A. Referring to both FIGS. 2A and 2B, the illustrated opening 150 includes a first portion 152 generally aligned with the terminal 124, a second portion 154 spaced apart laterally from the first portion 152, and a third portion 156 extending between the first and second portions 152 and 154. The first portion 152 is defined by a sidewall 142 and extends completely through the third dielectric layer 140 from a first surface 141a of the third dielectric layer 140 to a first surface 137 of the second dielectric layer 136. The first portion 152 accordingly has a first depth D₁ (FIG. 2A) and exposes a section of the second dielectric layer 136. The second portion 154 of the opening 150 is defined by a sidewall 147 and extends from the first surface 141a to a recessed surface 146a of the third dielectric layer 140 at an intermediate depth D₂ (FIG. 2A) less than the first depth D₁. The third portion 156 of the opening 150 also extends from the first surface 141a to the recessed surface 146a and is defined by sidewalls 149. Although the illustrated recessed surface 146a is generally planar and is oriented generally parallel to the first surface 141a, in other embodiments, the recessed surface may have a slope and/or be nonplanar. In the illustrated opening 150, the first portion 152 has a first lateral dimension X₁ (FIG. 2B), the second portion 154 has a second lateral dimension X₂ (FIG. 2B) greater than the first lateral dimension X₁, and the third portion 156 has a third lateral dimension X₃ (FIG. 2B) less than the first lateral dimension X₁. In additional embodiments, the opening 150 may not have the third portion 156, and/or the opening 150 can have a different configuration.

[0025] The first, second, and third portions 152, 154, and 156 of the opening 150 can be formed in a single development process. For example, in one embodiment, a phase-shift reticle or other suitable device can be used to pattern the third dielectric layer 140 and form exposed, underexposed, and unexposed portions. The exposed portion can be irradiated with a sufficient dose to activate all the material between the first and second surfaces 141a and 143 of the third dielectric layer 140. The underexposed portion can be irradiated with a dose selected so that only an upper section of the material in the third dielectric layer 140 is activated. During development, the exposed portion of the third dielectric layer 140 is removed to form the first portion 152 of the opening 150, and the underexposed portion of the third dielectric layer 140 is removed to form the second and third portions 154 and 156 of the opening 150.

[0026] In other embodiments, two or more masks can be used to pattern the third dielectric layer 140. For example, a first reticle can be used to expose a first section of the third dielectric layer 140 corresponding to the first portion 152 of the opening 150, and a second reticle can be used to expose a second section of the third dielectric layer 140 corresponding to the second and third portions 154 and 156 of the opening 150. The first section of the third dielectric layer 140 can be irradiated with a first dose to activate all the material between the first and second surfaces 141a and 143 of the third dielectric layer 140, and the second section of the third dielectric layer 140 can be irradiated with a second dose less than the first dose to activate only an upper portion of the material in the third dielectric layer 140. After exposing the first and second sections, the third dielectric layer 140 can be developed to remove the exposed material and form the opening 150. In additional embodiments, the third dielectric layer 140 can be patterned using optical proximity correction (OPC) techniques, or other suitable methods, to form the opening 150.

[0027] FIG. 3 is a schematic side cross-sectional view of the portion of the workpiece 100 illustrated in FIG. 2A after removing additional material from the dielectric structure 130. After patterning and developing the third dielectric layer 140, the workpiece 100 can be heated to at least partially cure the third dielectric layer 140. For example, in several embodiments, the workpiece 100 can be heated at 300° C. to 375° C. for 30 minutes to 30 hours. In other embodiments, however, the workpiece 100 can be heated to a different temperature and/or for a different period of time. Alternatively, the workpiece 100 may not be heated after patterning and developing the third dielectric layer 140.

[0028] In the illustrated embodiment, after heating the workpiece 100, additional material is removed from the dielectric structure 130 by reaction ion etching (RIE) or other suitable processes to extend the first, second, and third portions 152, 154, and 156 of the opening 150 toward the substrate 110. Specifically, a section of the first and second dielectric layers 132 and 136 is removed to expose the terminal 124 and extend the first portion 152 of the opening 150 from a first surface 141b of the third dielectric layer 140 to a surface 125 of the terminal 124. Moreover, a different section of the dielectric structure 130 is removed to extend the second and third portions 154 and 156 of the opening 150 from the first surface 141b to a recessed surface 146b. The illustrated recessed surface 146b is generally planar and is oriented generally parallel to the first surface 141b. Although the illustrated recessed surface 146b is formed partially in the second dielectric layer 136 and partially in the third dielectric layer 140, in other embodiments, the recessed surface 146b can be formed in the first, second, and/or third dielectric layers 132, 136, and/or 140 depending on the volume of material removed from the dielectric structure 130. In either case, the first portion 152 of the opening 150 has a third depth D₃, and the second and third portions 154 and 156 of the opening 150 have a fourth, intermediate depth D₄ less than the third depth D₃. In several applications, the third depth D₃ can be approximately 5 microns, and the fourth, intermediate depth D₄ can be approximately 3.5 microns. In other embodiments, the first, second, and/or third portions 152, 154, and/or 156 can have different depths.

[0029] FIG. 4 is a schematic side cross-sectional view of the portion of the workpiece 100 illustrated in FIG. 3 after depositing a barrier layer 160 onto the workpiece 100 and forming a conductive layer 170 on the barrier layer 160. The barrier layer 160 generally covers the exposed surface of the workpiece 100 including the exposed sections of the first, second, and third dielectric layers 132, 136, and 140 and the exposed surface 125 of the terminal 124. In one embodiment, for example, the barrier layer 160 is a layer of Ta that is deposited onto the workpiece 100 using physical vapor deposition (PVD). The thickness of the barrier layer 160 can be about 150 Å. In other embodiments, the barrier layer 160 may be deposited onto the workpiece 100 using other vapor deposition processes, such as CVD, and/or may have a different thickness. The barrier layer 160 is not limited to Ta, but rather may be composed of TaN, TiN, WNx, or other suitable materials to help contain the conductive layer 170 subsequently deposited onto the workpiece 100.

[0030] After forming the barrier layer 160, the conductive layer 170 is deposited onto the barrier layer 160 across the workpiece 100. In one embodiment, the conductive layer 170 is a layer of Al having a thickness of between 1 micron and 1.5 microns. In other embodiments, such as the embodiment described below with reference to FIGS. 6 and 8, the conductive layer 170 can have a different thickness and/or be comprised of a different material such as Cu.

[0031] FIG. 5 is a schematic side cross-sectional view of the portion of the workpiece 100 illustrated in FIG. 4 after planarizing the workpiece 100. After forming the conductive layer 170, a first side 102 of the workpiece 100 is planarized to remove the barrier layer 160 and the conductive layer 170 from the first surface 141b of the third dielectric layer 140, and leave only the sections of the conductive layer 170 disposed in the openings 150. Because the portion of the conductive layer 170 between the openings 150 is removed, the sections of the conductive layer 170 in each opening 150 are electrically isolated from each other.

[0032] The dielectric structure 130 and the sections of the conductive layer 170 disposed in the openings 150 form a redistribution layer 190 on the workpiece 100. Specifically, the section of the conductive layer 170 disposed in the second portion 154 of the opening 150 forms a pad 192, and the section of the conductive layer 170 disposed in the first and third portions 152 and 156 of the opening 150 forms a trace 194 electrically coupling the pad 192 to the terminal 124. The illustrated pad 192 has a generally planar surface 193 configured to receive a bump, conductive coupler (e.g., solder ball), and/or end of a wire-bond. Moreover, although the illustrated pad 192 is recessed from a surface 104 of the workpiece 100, in other embodiments, such as the embodiment described below with reference to FIG. 6, the pad is not recessed from the surface 104.

[0033] One feature of the method illustrated in FIGS. 1-5 is that the redistribution layer 190 can be formed on the workpiece 100 with a single patterning process and a single developing process. An advantage of this feature is that the illustrated method reduces the number of expensive and time-consuming patterning and developing processes performed while constructing a redistribution layer on a workpiece. By contrast, conventional methods of forming redistribution layers require multiple patterning processes and multiple development processes. Moreover, another advantage of the method illustrated in FIGS. 1-5 is that the process can be easily adapted to accommodate dies with different sizes. For example, the size of the openings 150 can be easily changed to form the pads 192 of the redistribution layer 190 closer to or further away from the corresponding terminals 124.

C. Additional Embodiments of Methods for Forming a Redistribution Layer on Microfeature Workpieces

[0034] FIG. 6 is a schematic side cross-sectional view of a portion of a workpiece 200 in accordance with another embodiment of the invention. The illustrated workpiece 200 is generally similar to the workpiece 100 described above with reference to FIGS. 1-5. The illustrated workpiece 200, however, includes a thicker conductive layer 270 that fills the second and third portions 154 and 156 of the opening 150. The thicker conductive layer 270 can be formed by depositing Al, Cu, or other suitable conductive materials onto the workpiece 200. Because of the thickness of the conductive layer 270, the workpiece 200 includes a redistribution layer 290 having a plurality of pads 292 with a surface 293 that is generally coplanar with a surface 204 of the workpiece 200.

[0035] FIGS. 7 and 8 illustrate stages in a method for forming a redistribution layer on a microfeature workpiece in accordance with another embodiment of the invention. FIG. 7, for example, is a schematic side cross-sectional view of a portion of a workpiece 300 generally similar to the workpiece 100 described above with reference to FIG. 4. For example, the illustrated workpiece 300 includes an opening 150 having a first portion 152, a second portion 154 spaced apart laterally from the first portion 152, and a third portion 156 extending between the first and second portions 152 and 154. The illustrated workpiece 300, however, includes a seed layer 365 on the barrier layer 160. The seed layer 365 can be deposited using vapor deposition techniques, such as PVD, CVD, and/or atomic layer deposition (ALD). The seed layer 365 can be composed of Cu or other suitable materials. The thickness of the seed layer 365 may be about 2000 Å, but can be more or less depending on the depth of the opening 150. After forming the barrier layer 160 and the seed layer 365 on the workpiece 300, a first side 302 of the workpiece 300 is planarized to remove the barrier layer 160 and the seed layer 365 from the first surface 141b of the third dielectric layer 140 and leave only the sections of the seed layer 365 disposed in the openings 150.

[0036] FIG. 8 is a schematic side cross-sectional view of the workpiece 300 after forming a conductive layer 370 on the seed layer 365 by electroless plating, electroplating, or another suitable methods. The conductive layer 370 can be comprised of Ni/Au or other suitable conductive materials. One feature of the method illustrated in FIGS. 7 and 8 is that the workpiece 300 is planarized to remove the portion of the seed layer 365 between the openings 150 before plating the conductive layer 370 onto the workpiece 300. An advantage of this feature is that the conductive material plates only onto the seed layer 365 in the openings 150 and not across the entire surface of the workpiece 300, which reduces the material costs.

[0037] From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, many of the elements of one embodiment can be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims.