US 7,256,089 B2Grant
Top electrode barrier for on-chip die de-coupling capacitor and method of making same
Issue Date:2007-08-14
•7 Claims
•4 Drawing Sheets
Abstract
An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
Metadata
Assignee
- Intel Corporation
Inventors
- Richard Scott List
- Bruce A. Block
- Ruitao Zhang
Application Information
Application Number:US 09/962,786
Filing Date:2001-09-24
Priority Date:2001-09-24
Art Unit:2811
Classifications
IPC:
H01L21/8242H01L21/20
Patent Drawings (4 sheets)
Description
Background
[0001] 1. Field
[0002] The invention relates to integrated circuit decoupling capacitors.
[0003] 2. Background
[0004] The operation of high power, high speed integrated circuits can be affected by the electrical noise generated by the instantaneous switching of the transistors located in the circuit. It is well known that the inductive noise of an integrated circuit can be reduced by connecting decoupling capacitors to the circuit. Decoupling capacitors placed on power grids with current surges are able to smooth out voltage variations with current supplied from the stored charge on the decoupling capacitor.
[0005] Typically, a decoupling capacitor is placed on the opposite side of the package from the chip. Unfortunately, this arrangement is costly to manufacture, and the long lead lines from the power-consuming circuit to the capacitor electrodes contribute to an unacceptably high inductance. Such off-chip decoupling capacitors, however, are not sufficient for very high speed microprocessor applications. Since the decoupling capacitors are located at a relatively long distance from the switching circuits, the voltage drop caused by the high inductance path makes the off-chip capacitors unusable with gigahertz switching circuits. The voltage drop across an inductor is equal to L di/dt, where L is inductance and di/dt represents the change in current through a circuit over a period of time. Implicit in the di/dt is a frequency term omega, so as frequency goes up, inductive voltage drop becomes a larger part of the equation for power distribution. At very low frequencies, the only contributing impedance is the resistive voltage drop equal to iR, which is independent of frequency. At very low frequencies, power distribution is dominated by resistance.
[0006] Efforts have been made to integrate decoupling capacitors as part of the gate dielectric processing step. A portion of the chip is used to deposit the gate dielectric for use at the decoupling capacitor. An advantage to this is that there are no additional processing steps involved with fabricating the decoupling capacitor while using the gate dielectric. The disadvantages include the decoupling capacitor takes up high-value real estate on the chip as the capacitors compete for valuable die area that could be used for building additional circuits. Also when the capacitor is made with the gate oxide designed for very high transistor performance, there is a great deal of leakage. Although it is possible to integrate chip capacitors within the chip's circuit elements, due to limited area in which to build these capacitors, the overall capacitive decoupling that they provide is also limited.
[0007] Another approach to decoupling capacitor fabrication is illustrated in
[0008] FIG. 1 . FIG. 1 illustrates a decoupling capacitor that may be fabricated on top of a metal line in an integrated circuit. In one embodiment, the metal layer comprises Vcc 35 and Vss 30. On top of Vcc line 35 is a decoupling capacitor stack comprising lower electrode 18, capacitor material 16 of a generally high dielectric constant, and top electrode 14, the whole of which is passivated by a global layer of silicon nitride 20. Surrounding all metal lines in these metal layers is interlayer dielectric (ILD) 10 that is usually a Plasma Tetra Ethyl Ortho Silicate (PTEOS) oxide. FIG. 1 shows a Vss 30 coupled through an opening in passivation layer 20 through a decoupling capacitor stack 18, 16, and 14 to metal Vcc 35. This figure forms a decoupling capacitor between Vcc line 35 and Vss line 30. The advantages to this embodiment are that no additional real estate on the chip is taken up for fabrication of the decoupling capacitor, and the decoupling capacitor is no more than 70 microns from the integrated circuit element it is supporting. An off-chip decoupling capacitor is typically a millimeter in distance from the circuit element it is supporting.
[0009] A disadvantage of stacking the decoupling capacitors over the metal lines is illustrated in FIG. 2 . Ideally, on chip decoupling capacitors are strapped off less than every 10 microns. However, due to structural limitations inherent in the layout of the chip and package bumps, the area of copper line 35, which in this example is a Vcc line, covered by the capacitor stack and particularly electrode 14 of the capacitor stack, can be much greater than metal contact 30 through the passivating layer to top electrode 14. In one embodiment, this long capacitor stack may create wings of top electrode that extend 75 microns from the strapping contact.
[0010] In one embodiment, both Vss contact 30 and Vcc metal line 35 are made of copper, a highly conductive material. Top capacitor electrode 14 may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN). These typical top electrode materials generally have a much higher resistivity than copper. In one embodiment, where the top electrode is tantalum nitride, the resistivity of the top electrode is typically about 250 micro-ohm per centimeter (μohm cm.). Copper typically has a resistivity of 2 μohm cm. This change in resistivity can lead to an RC time constant loss as distant areas of the capacitor stack, say for example at point B of FIG. 2 , require longer time to charge and discharge than areas of the capacitor stack near a conductive material, say for example point A.
[0011] The distance between points A and B in the top electrode shown in FIG. 2 is the distance over which a current has to travel to extract the charge at point B. This distance is called the strapping distance, W. This distance can be, in some instances, as much as 75 microns. The capacitance built up at point B then has to travel to point A in the relatively high resistivity top electrode 14 to contribute its charge. A time constant τ, is equivalent to RC (resistance times capacitance) in a RC circuit. RC is a rough measure of the time it would take to charge a capacitor through the distance from a constant voltage supply. R in this circuit is proportional to the distance between point A and point B or W, as is C. Thus τ is proportional to the square of the strapping distance, W. In the embodiment where the strapping distance is increased from about 10 microns to about 75 microns, the time constant increases by the square of the increase in distance of 7.5 to about 56, this would roughly translate to a delay of 10 nanosecond (nsec) or a maximum response frequency of 100 MHz. This increase in the time constant necessitates a reduction in the frequency of operation the decoupling capacitors may support.
Brief Description of the Drawings
[0012] The claims are illustrated by way of example, and not limitation in the figures of the accompanying drawings, in which:
[0013] FIG. 1 is a cross-sectional schematic illustration of a decoupling capacitor stack placed on top of the metal line;
[0014] FIG. 2 is a cross-sectional schematic illustration the decoupling capacitor placed on the metal line of FIG. 1 seen through line A-A′;
[0015] FIG. 3 is a schematic cross-sectional illustration of a decoupling capacitor with a top electrode barrier;
[0016] FIG. 4 is the decoupling capacitor stack on the metal line 35 with the top electrode barrier of FIG. 1 seen through line B-B′; and
[0017] FIG. 5 is a flow diagram representing one method of fabricating one embodiment of the top electrode barrier.
Detailed Description
[0018] An apparatus and method for fabricating a top electrode barrier for an off-die decoupling capacitor is disclosed. Reference will now be made to drawings wherein like structures will be provided with like reference designations. In order to show the structures of the claims more clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating essential structures of the claims. Moreover, the drawings show only the structures necessary to understand the claims. Additional structures known in the art have not been included to maintain the clarity of the drawings.
[0019] FIG. 3 is an illustration of one embodiment of a substrate such as a semiconductor (silicon) substrate having a decoupling capacitor stack on a metal layer the capacitor stack having a top electrode barrier 12 on top electrode 14 of the decoupling capacitor stack. Vcc metal line 35 is planarized and a blanket bottom electrode deposition 18 is laid on a surface thereof. The blanket bottom electrode deposition 18 has a high k material 16 deposited on top of it. Examples include silicon nitride (SiN), k=8; tantalum pentoxide (Ta2O5) k=25 or boron strontium titanate (BST) k=300. Finally, on top of high k material 16, a top electrode material 14 is deposited. Bottom electrode 18, high k material 16, and top electrode 14, form a decoupling capacitor that allows Vcc metal line 35 to be decoupled. Typically, bottom electrode 18 and top electrode 14 may be fabricated from a metal nitride compound.
[0020] Typical compounds for use as the metal nitride for the top and bottom electrodes of the decoupling capacitor include, but are not limited to, tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN). Top electrode barrier 12 will generally be, for ease of fabrication purposes, the metal from the metal nitride compound mentioned above. So, for example, if the top and bottom electrodes were made of tantalum nitride, the top electrode barrier would be made of tantalum. This use of a metal nitride metal system to place the top electrode barrier on the surface of the top electrode (as viewed) allows the deposition to be done in a single chamber. Top electrode 14 and top electrode barrier 12 form a highly adhesive interface, and typically the two materials will have similar etch characteristics. Typically, the transition from depositing a metal nitride to a metal can be accomplished by either a reduction in the radio frequency (RF) power of the deposition tool or a reduction in the partial pressure of the nitrogen in the chamber.
[0021] FIG. 4 illustrates the embodiment from FIG. 3 as seen from a 90° angle to better show the strapping length involved. In one embodiment, where the metal line is made out of copper and the metal nitride metal system is tantalum nitride, the resistivity of copper is typically 2 μohm cm., the resistivity of tantalum is typically 13 μohm cm., and the resistivity of tantalum nitride is typically 250 μohm cm. Thus, the top electrode barrier provides approximately a factor of 20 reduction in resistivity reducing the RC capacitor time constant. Hence, the use of top barrier electrode 12 effectively increases the maximum response frequency from 100 MHz to 2 GHz.
[0022] FIG. 5 is a flow diagram representation of one method of fabricating an embodiment of the top electrode barrier. An integrated circuit is provided in block 510. In one embodiment, the integrated circuit has a top layer metal including an interlayer dielectric (ILD). The metal layer may be made of, but is not limited to, copper. The ILD may be formed from, but is not limited to, Plasma Tetra Ethyl Ortho Silicate (PTEOS). This metal layer is planarized to give the copper and ILD a smooth single surface.
[0023] An on chip decoupling capacitor stack is formed on the top metal layer at block 520 of FIG. 5 . In one embodiment, the on chip decoupling capacitor stack comprises a bottom electrode, a high k dielectric layer and a top electrode with a top electrode barrier.
[0024] In one embodiment, the capacitor is formed by depositing a blanket layer of bottom electrode on the planarized top metal layer. The bottom electrode may be, but is not limited to TaN, TiN and WN. The bottom electrode may comprise a conductive barrier metal, which prevents oxidation and diffusion of copper during the deposition of a high k material, as well as subsequent process steps. Then a bottom electrode material may be deposited on the conductive barrier layer. The bottom electrode material will not oxidize during the deposition of the high k dielectric material. Deposition of the bottom conductive barrier material and the bottom electrode may be combined into one film, or if there is no degradation involved with direct high k deposition onto Cu, this bottom barrier/electrode component can be omitted.
[0025] After depositing the bottom electrode, a high k dielectric material is blanket deposited over the bottom electrode layer. The high k dielectric material may be but is not limited to tantalum pentoxide (Ta2O5).
[0026] The top electrode is deposited over the high k dielectric layer. The top electrode may be, but is not limited to TaN, TiN and WN. Deposition of this metal nitride material will inhibit oxidation during later process steps. Deposition of the top electrode may be followed by same chamber deposition of Tantalum (Ta), Titanium (Ti) and Tungsten (W). The metal deposition over the metal nitride layer forms the conductive top electrode barrier. This barrier will reduce the resistance of the top electrode and the strapping distance as discussed above. The deposition of one of these metal nitride materials may transition to the deposition of just the metal by either a reduction in the RF power applied to the deposition, or a reduction in the back pressure of nitrogen in the deposition chamber. The transition forms a metal nitride/metal interface between the top electrode and top electrode barrier layer. Deposition of the top electrode barrier is shown in block 530 of FIG. 5 .
[0027] Processing the decoupling capacitor continues by applying and patterning a layer of photoresist. The photoresist is patterned to cover those areas of the metal layer where it is desired to retain the decoupling capacitor stacks. The capacitor stack is etched through, and the etch stops on the copper ILD layer. The photoresist mask is removed with a copper neutral photoresist stripper. A thin passivating layer is deposited over the capacitor stack, which includes a top electrode conductive barrier, and the exposed copper and ILD. The passivating layer may be made of, but is not limited to, silicon nitride (Si3N4). The passivating layer is patterned and etched to open contact openings to the top electrode barriers and copper vias.
[0028] Fabrication of the top electrode barrier as described above allows a reduction in the time constant for recharging the decoupling capacitor stack as shown in block 540 of FIG. 5 . Inclusion of the top electrode barrier on the top electrode of the capacitor stack greatly reduces the time constant RC and enhances the ability of the capacitor stack to decouple and reduce the highest possible frequency noise.
[0029] In one embodiment, where the high k material will not react with the metal layer, the high k material, in one example a silicon nitride material, may be blanket deposited on the metal layer. A top electrode may then be deposited on the high k material layer. Not only does this eliminate the bottom electrode deposition step, but the top electrode/high k etch can stop anywhere in the high k layer without causing shorting between copper metal layer lines, since there is no blanket bottom electrode to remove. This has benefits of simplified processing in that there is greater etch control for the high k material etch, and an oxidizing photoresist ash step may be preformed after the high k etch because the copper will be covered by the blanket high k material deposition.
[0030] In the preceding detailed description, the invention is described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims
What is claimed is:
1. A method comprising:
providing an integrated circuit having a layer of metal;
forming an on-chip decoupling capacitor stack, the on-chip decoupling capacitor stack including,
a bottom electrode on the layer of metal;
a dielectric layer;
a top electrode separated from the bottom electrode by the dielectric layer; and
a conductive top electrode barrier contacting the top electrode,
wherein the top electrode barrier comprises a material that is more electrically conductive than a material for the top electrode, and
wherein the top capacitor electrode is formed on the dielectric layer and the top electrode barrier is formed on the top electrode in a single deposition chamber without removing the on-chip decoupling capacitor stack from the single deposition chamber.
2. The method of claim 1, wherein forming the conductive electrode barrier comprises depositing one less element than forming the top capacitor electrode.
3. The method of claim 2, wherein forming the top electrode and conductive electrode barrier comprises the formation of a metal nitride/metal interface.
4. A method comprising:
providing an integrated circuit with a layer of metal;
planarizing the layer of metal;
depositing a blanket bottom electrode material over the layer of metal;
depositing a dielectric material having a dielectric constant of greater than about 7;
depositing a blanket top electrode material separated from the bottom electrode material by the dielectric material;
depositing a blanket top electrode barrier;
patterning the dielectric material, top electrode material and top electrode barrier into a capacitor stack;
depositing a blanket passivation layer; and
wherein depositing the top electrode barrier comprises depositing a material that is more electrically conductive than a material for the top electrode, and
wherein the top electrode is deposited on the dielectric layer and the top electrode barrier is deposited on the top electrode in a single deposition chamber without removing the on-chip decoupling capacitor stack from the single deposition chamber.
5. The method of claim 4, wherein forming the top electrode and conductive electrode barrier comprises forming a metal nitride/metal interface.
6. The method of claim 4, wherein the dielectric material has a dielectric constant of greater than about 10.
7. The method of claim 6, wherein the layer of metal comprises a material that is more conductive than the material for the electrode.
Patent Citations (6)
Non-Patent Literature (6)
- Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey, (1993), p. 42.Examiner
- Hiroyuki Shimada, Ichiro Ohshima, Shin-Ichi Nakao, Munekatsu Nakagawa, Kei Kanemoto, Masaki Hirayama, Shigetoshi Sugawa, and Tadahiro Ohmi, “Low Resistivity bcc-Ta/TaNx Metal Gate MNSFETs Having Plane Gate Structure Featuring Fully Low-Temperature Processing Below 450 C,” Digest of Technical Papers- Symposium on VLSI Technology, (2001), pp. 67-68.Examiner
- S.C. Sun, M.H. Tsai, C.E. Tsai, and H.T. Chiu, “Properties of Metalorganic Chemical Vapor Deposited Tantalum Nitride Thin Films,” Proc. 4th Int'l Conf. on Solid State and Integrated Circuit Tech. (1995), pp. 547-549.Examiner
- Hiroyuki Shimada, Ishiro Oshima, Takeo Ushiki, Shigetoshi Sugawa and Tadahiro, “Tantalum Nitride Metal Gate FD-SOI CMOS FETs Using Low Resistivity Self-Grown bcc-Tantalum Layer,” IEEE Trans. on Electron Devices, vol. 48 (Aug. 2001) pp. 1619-1627.Examiner
- S.M. Sze, “Physics of Semiconductor Devices,” John Wiley & Sons, New York (1981), Appendix I.Examiner
- S. Wolf, “Silicon Processing for the VLSI Era, vol. 4—Deep Submicron Process Technology,” Lattice Press, Sunset Beach, CA (2002) p. 720.Examiner