Method for producing gate stack sidewall spacers

[0001] 1. Field of the Invention

[0002] Embodiments of the present invention generally relate to a method for producing sidewall spacers for gate stacks on semiconductor substrates.

[0003] 2. Description of the Related Art

[0004] Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and which cooperate to perform various functions within an electronic device. Such transistors may include complementary metal-oxide-semiconductor (CMOS) field effect transistors.

[0005] A CMOS transistor includes a gate structure that is disposed between a source region and a drain region defined in the semiconductor substrate. The gate structure (stack) generally comprises a gate electrode formed on a gate dielectric material. The gate electrode controls a flow of charge carriers, beneath the gate dielectric, in a channel region that is formed between the drain region and the source region, so as to turn the transistor on or off. Typically disposed proximate the gate stack is a spacer layer, which forms a sidewall on either side thereof. Sidewall spacers serve several functions, including, electrically isolating the gate electrode from source and drain contacts or interconnects, protecting the gate stack from physical degradation during subsequent processing steps, and providing an oxygen and moisture barrier to protect the gate metal. One example of such a sidewall spacer arrangement is disclosed in U.S. patent application Ser. No. 10/397,776, filed Mar. 25, 2003.

[0006] A conventional gate stack is formed from materials having dielectric constants of less than about 5 (k<5) and is typically protected by a silicon nitride spacer. Further reduction in transistor sizes will likely require gate layers having dielectric constants of greater than 10 (k>10). If the sidewall spacer is then fabricated from a relatively high k (k>7) material, such as silicon nitride, excessive signal crosstalk between adjacent interconnection lines can occur during use of the device containing the completed gate electrode. While ultra-low k materials (k<3) may be employed as a spacer layer, these materials often lack the necessary structural integrity to survive subsequent processing steps and/or requisite oxygen and moisture imperviousness to protect the gate metal from corrosion.

[0007] In addition, conventional thermal chemical vapor deposition (CVD) process used to prepare silicon nitride spacer requires high deposition temperature, which is typically greater than 600° C. The nitride spacer deposited at high temperature has very good conformality (e.g. ≧95%); however, the high deposition temperature results in large thermal cycle for the gate device and is not compatible with advanced device manufacturing for 0.09 micron technology and beyond.

[0008] Therefore, there is a need for low temperature, and low k sidewall spacers for low k gate stacks, wherein the sidewall spacer possesses the desired physical properties of structural stability and hermeticity.

[0009] The present invention provides a method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using plasma enhanced chemical vapor deposition (PECVD) process(es) on a gate stack to produce a spacer having an overall dielectric constant of about 3.0 to about 5.0 at a temperature equaling to or below 450° C.

[0010] In one embodiment, a method for forming a sidewall spacer for a gate electrode comprises placing a substrate having a gate structure in a plasma process chamber, flowing process gas(es) into the plasma process chamber, creating a plasma in the plasma process chamber, and depositing one or more layers of silicon containing materials on the gate structure at a temperature equaling to or less than 450° C., wherein the one or more layers of silicon containing materials have an overall k value of about 3.0 to about 5.0.

[0011] In another embodiment, a method for forming a sidewall spacer for a gate electrode comprises placing a substrate having a gate structure in a plasma process chamber, flowing process gas(es) into the plasma process chamber, creating a plasma in the plasma process chamber, and depositing one or more layers of silicon containing materials on the gate structure, wherein the one or more layers of silicon containing materials have an overall k value of about 3.0 to about 5.0, and the one or more layers of silicon containing materials are selected from the group consisting of silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, and combinations thereof.

[0012] In yet another embodiment, a method for forming a sidewall spacer for a gate electrode comprises placing a substrate having a gate structure in a plasma process chamber, flowing process gas(es) into the plasma process chamber, creating a plasma in the plasma process chamber, and depositing one or more layers of silicon containing materials on the gate structure at a temperature equaling to or below 450° C., wherein the one or more layers of silicon containing materials have an overall k value of about 3.0 to about 5.0, and the one or more layers of silicon containing materials are selected from the group consisting of silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, and combinations thereof.

[0016] The present invention encompasses forming sidewall spacers for gate stacks by applying a silicon-based film to a gate structure. In some embodiments, a spacer layer is formed by deposition of silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, or carbon doped silicon nitride adjacent a gate dielectric. In another embodiment, the spacer layer is formed by deposition of carbon doped silicon oxynitride.

[0017] FIG. 1 illustrates a transistor having a gate structure formed according to one embodiment of the invention. Referring to FIG. 1, a plurality of field isolation regions 102 are formed in a substrate 100 (e.g., a silicon wafer). The plurality of field isolation regions 102 isolate a well 103 of one type conductivity (e.g., p-type) from adjacent wells (not shown) of other type conductivity (e.g., n-type). Then, a gate dielectric layer 104 is formed on the substrate 100 and on isolation regions 102. Typically, gate dielectric layer 104 may be formed by depositing or growing a layer of a material such as silicon oxide (SiO_n) and/or silicon oxynitride, which form layers having a dielectric constant less than about 5.0. Recent advances in gate dielectric technology indicate that higher dielectric constant materials (K>10) are desirable for forming gate dielectric layer 104. Examples of suitable materials to be employed therefor include, but are not limited to, metal oxides (Al₂O₃, ZrO₂, HfO₂, TiO₂, Y₂O₃, and La₂O₃), ferroelectrics (lead zirconate titanate (PZT) and barium strontium titanate (BST)), amorphous metal silicates (HfSi_xO_y and ZrSi_xO_y), amorphous silicate oxides (HfO₂, and ZrO₂), and paralectrics (Ba_xSr_1-xTiO₃ and PbZr_xTi_1-xO₃). High k layers containing these materials may be formed by various deposition processes.

[0018] Further, an electrically conductive gate electrode layer 106 is blanket deposited over gate dielectric layer 104. Generally, the gate electrode layer 106 may comprise a material such as, but not limited to, doped polysilicon, undoped polysilicon, silicon carbide, or silicon-germanium compounds. However, contemplated embodiments may encompass a gate electrode layer 106 containing a metal, metal alloy, metal oxide, single crystalline silicon, amorphous silicon, silicide, or other material well known in the art for forming gate electrodes.

[0019] A hard-mask layer (not shown), such as a nitride layer, is deposited via a CVD process over electrically conductive layer 106. A photolithography process is then carried out including the steps of masking, exposing, and developing a photoresist layer to form a photoresist mask (not shown). The pattern of the photoresist mask is transferred to the hard-mask layer by etching the hard-mask layer to the top of the gate electrode layer 106, using the photoresist mask to align the etch, thus producing a hard-mask (not shown) over the gate electrode layer 106.

[0020] The structure is further modified by removing the photoresist mask and etching the gate electrode layer 106 down to the top of the dielectric layer 104, using the hard-mask to align the etch, thus creating a conductive structure including the remaining material of gate electrode layer 106 underneath the hard-mask. This structure results from etching the gate electrode layer 106, but not the hard-mask or gate dielectric layer 104. Continuing the processing sequence, gate dielectric layer 104 is etched to the top of the substrate 100 and to the tops of the isolation regions 102. The gate electrode 106 and the gate dielectric 104 together define a composite structure 124, sometimes known as a gate stack, or gate, of an integrated device, such as a transistor.

[0021] In further processing of the transistor, tips, or shallow source/drain extensions, 140, are formed by utilizing a tip implant process. The gate electrode 106 protects the substrate region beneath the gate dielectric 104 from being implanted with ions. A rapid thermal process (RTP) anneal may then be performed to drive the tips 140 partially underneath the gate dielectric 104.

[0022] Next, a conformal thin oxide layer 125 is deposited over the entire substrate surface. This oxide layer is used to protect the silicon surface from the spacer layer, which is a silicon nitride layer for conventional process. The conformal thin oxide layer is typically deposited with TEOS source gas in a low pressure chemical vapor deposition chamber at high temperature (>600° C.). It relaxes the stress between silicon substrate and nitride spacer and it also protect the gate corners from the silicon nitride spacer. If low k and non-silicon-nitride material is used as sidewall spacer, this conformal thin oxide layer 125 can possibly be eliminated or be replaced by other low k material.

[0023] Afterwards, in one embodiment of the invention, a spacer layer 126, with thickness in the range between about 200 Å to about 1000 Å, preferably between about 400 Å to about 800 Å, is blanket deposited over the top of the gate stack 124 and along the entire length of the sides of the composite structure_124, including the entire length of the sidewalls of the gate electrode 106 and the gate dielectric 104. At the same time, the spacer layer 126 is deposited on top of any exposed portion of the substrate 100 or isolation regions 102. Conventional spacer layer is a silicon nitride layer deposited by thermal CVD. For advanced device manufacturing, the dielectric constant (k value) of silicon nitride (k value about 7) is too high that could result in excessive signal crosstalk. In addition, a thermal CVD process used to deposit silicon nitride requires high deposition temperature (>600° C.). The high deposition temperature results in high thermal cycle and could change the dopant profile of tip 140. Therefore, it is desirable to have a spacer layer deposition process with lower deposition temperature. Plasma Enhanced Chemical Vapor Deposition (PECVD) process typically has lower deposition temperature. For a silicon nitride layer deposited by a plasma process, the deposition temperature can be lowered to 450° C. or less. The process of depositing a thin film in a plasma process chamber is shown in FIG. 2. The process starts at step 201 by placing a substrate in a plasma process chamber. Next at step 202, flow process gas(es) into the plasma process chamber. Then at step 203, create a plasma in the plasma process chamber. At step 204, deposit a thin film on the substrate in the plasma process chamber. The conformality of the spacer layer deposited by plasma process is not as good as the thermal CVD process. Using silicon nitride as an example, silicon nitride by thermal CVD has conformality close to 100%, while silicon nitride by PECVD has conformality at about 75%. Although spacer layer by PECVD process has lower conformality than thermal CVD process, the benefit of lower thermal cycle (or thermal budget) could out weigh the shortcoming of lower conformality. Therefore, it is desirable to have a low k spacer layer deposited by PECVD.

[0024] The spacer layer 126 and thin oxide layer 125 are then etched to remove the spacer layer 126 and thin oxide layer 125 from the top of the gate electrode 106 as well as from the top surface of the isolation regions 102 and from most of the top surface of the substrate 100 except immediately to either side of the gate stack 124. The anisotropic etch, however, leaves a portion of the spacer layer 126 and thin oxide layer 125 along the entire length of the sidewalls of both the gate electrode 106 and the gate dielectric 104, thus forming a sidewall spacer 126. Alternatively, the sidewall spacers 126 may be deposited as a single layer or as two or more sequentially deposited layers.

[0025] Next, the substrate 100 is subjected to a deep, high dose implant process to form deep junction source/drain regions 148 in the well region 103. The deep implant includes implanting ions with the same conductivity type impurities used to form the tips 140. At the same time, if the electrically conductive gate electrode comprises polysilicon, the deep implant process can be used to dope the polysilicon in the gate electrode 106 if not previously doped. An activation anneal may be performed to activate the tips 140 and deep implants 148. The anneal may be performed with a rapid thermal process (RTP).

[0026] The foregoing embodiment of a transistor structure and method of its formation are merely illustrative. Additional embodiments of gate electrodes and alternative methods for their formation may be employed to practice the invention. Further details concerning exemplary methods and apparatuses for forming gate stacks are disclosed in commonly assigned U.S. patent application Ser. No. 10/612,642, filed Jul. 1, 2003, which claims priority to U.S. provisional patent application Ser. No. 60/393,393, filed Jul. 2, 2002, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0027] In various embodiments of the present invention, spacer film (layer) 126 may be formed of silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. In these embodiments, the resulting spacer layer 126 has a k value of about 3.0 to about 5.0. In addition, the deposition is performed by PECVD process at temperature less than 450° C.

[0028] In one embodiment, the spacer layer 126 is formed from silicon carbide by reacting a gas mixture including a silicon source, a carbon source, and an inert gas under plasma conditions in a PECVD chamber, such as DxZ™ chamber. DxZ™ chamber is commercially available from Applied Materials Inc., located in Santa Clara, Calif. In one embodiment, the process temperature is between about 200° C. to about 400° C. The silicon source and the carbon source may be a single source, such as an organosilane compound having the general formula Si_xC_yH_z. For example, methylsilane (SiH₃CH₃), dimethylsilane (SiH₂(CH₃)₂), trimethylsilane (SiH(CH₃)₃), tetramethylsilane (Si(CH₃)₄), diethylsilane (SiH₂(C₂H₅)₂), and Bis(trimethylsilyl)ethylene (C(Si(CH₃)₃)₂), and combinations thereof, among others may be used to provide silicon and carbon. Alternatively, compounds including, but not limited to, silane (SiH₄), disilane (Si₂H₆), and combinations thereof may be used as the silicon source, and compounds having the general formula C_xH_2x+2, including but not limited to, methane (CH₄), compounds having the general formula C_xH_2x, including but not limited to, ethylene (C₂H₄), and combinations thereof, may be employed as the carbon source. Helium (He), argon (Ar), nitrogen (N₂), or combinations thereof, among others, may be used for the inert gas. Further details of the methods for depositing silicon carbide layers and the physical properties thereof are disclosed in commonly assigned U.S. Pat. No. 6,465,366, which is incorporated herein by reference to the extent not inconsistent herewith.

[0029] An as-deposited silicon carbide layer has a dielectric constant of about 3.0 to about 5.0. The dielectric constant of the silicon carbide layer is tunable, in that it can be varied as a function of the ratio of the mixed frequency RF powers. In particular, as the ratio of the low frequency RF power to the total mixed RF power decreases the dielectric constant of the as-deposited silicon carbide layer also decreases. The dielectric constant of the silicon carbide layer can also be tuned as a function of the composition of the gas mixture during layer formation. As the carbon concentration in the gas mixture increases, the carbon content of the as-deposited silicon carbide layer increases, decreasing its dielectric constant. Also, as the carbon content of the as-deposited silicon carbide layer increases the hydrophobic properties thereof increase.

[0030] In another embodiment, the spacer layer 126 is formed from an oxygen doped silicon carbide by reacting a processing gas including one or more oxygen-containing organosilicon compounds and one or more oxygen-free organosilicon compounds to form a dielectric layer comprising carbon-silicon bonds and having a dielectric constant of about 3.5 to about 5.0. The oxygen-containing organosilicon compounds have a general structure of Si_wC_xH_yO_z. The oxygen-free organosilicon compounds have a general structure of Si_xC_yH_z. Suitable organosilicon compounds for the processes described herein include aliphatic organosilicon compounds, cyclic organosilicon compounds, or combinations thereof. Aliphatic organosilicon compounds have linear or branched structures. Commercially available aliphatic organosilicon compounds include oxygen-free organosilicon compounds, such as alkylsilanes and oxygen-containing organosilicon compounds, such as alkylsiloxanes.

[0031] The processes described herein are preferably performed in a plasma processing chamber adapted to deposit organosilicon material while applying RF power, such as a DxZ™ plasma enhanced chemical vapor deposition chamber. In one embodiment, the deposition temperature is between about 250° C. to about 450° C. Generally, the organosilicon compounds are reacted in a plasma comprising a noble gas, such as helium (He) or argon (Ar), or an inert gas, such as nitrogen (N₂). Further details of the methods for depositing oxygen doped silicon carbide layers and the physical properties thereof are disclosed in commonly assigned U.S. Pat. No. 6,890,850, filed Jul. 15, 2002, which claims priority to U.S. provisional patent application Ser. No. 60/340,615, filed Dec. 14, 2001, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0032] In another embodiment, the oxygen doped silicon carbide layer is formed by depositing a silicon carbide layer and then introducing oxygen to that layer by supplying an oxygen containing gas under plasma conditions. The plasma treatment with an oxygen containing gas could be performed in a PECVD chamber, such as DxZ™ chamber. In one embodiment, the plasma treatment temperature is maintained in the range between about 0° C. to about 500° C., and preferably between about 100° C. to about 450° C. The oxygen doped silicon carbide film has about 1 to about 30 atomic percent oxygen content and a dielectric constant of about 3.5 to about 5.0. In one embodiment, the oxygen-free organosilicon compound(s) and an oxygen-containing organosilicon compound(s) react to deposit an oxygen doped silicon carbide film having about 1 to about 30 atomic percent oxygen content and a dielectric constant of about 3.5 to about 5.0. In one embodiment, the deposition is performed in a PECVD chamber and the temperature is maintained at between about −20° C. to about 500° C., and preferably between about 170° C. to about 180° C. The dielectric constant of the oxygen doped silicon carbide layer is tunable, in that it can be varied as a function of the reactants employed, reactant and inert gas flow rates, chamber temperature, and applied RF frequencies. Further details of the methods for producing an oxygen doped silicon carbide layer by oxygen doping of a silicon carbide layer are disclosed in commonly assigned U.S. Pat. No. 6,821,571, filed Jun. 18, 1999, and U.S. Pat. No. 6,913,992, filed Mar. 7, 2003, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0033] In another embodiment, the spacer layer 126 is formed from a nitrogen doped silicon carbide by reacting a gas mixture including a silicon source, a carbon source, and a nitrogen source. Herein the term “nitrogen doped silicon carbide” designates materials containing silicon, nitrogen, carbon, and optionally hydrogen, wherein the nitrogen content is less than the carbon content. In one embodiment, the as-deposited nitrogen doped silicon carbide layer contains about 1 to about 30 atomic percent nitrogen and has a dielectric constant of about 4.0 to about 5.0. The deposition could be performed in a PECVD chamber, such as DxZ™ chamber. In one embodiment, the substrate temperature is maintained in the range between about 150° C. to about 450° C. The dielectric constant of the nitrogen doped silicon carbide layer is tunable, in that it can be varied as a function of the RF power applied during the deposition process. In particular, as the RF power increases the dielectric constant of the as-deposited nitrogen doped silicon carbide layer_also increases. Additionally, the dielectric constant can be varied as a function of the nitrogen source and/or concentration thereof in the gas mixture. In particular, as the nitrogen dopant content increases, the dielectric constant of the deposited nitrogen doped silicon carbide layer decreases. Further details of the methods for depositing nitrogen doped silicon carbide layers and the physical properties thereof are disclosed in commonly assigned U.S. Pat. No. 6,764,958, filed Jul. 28, 2000, and U.S. Pat. No. 6,537,733, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0034] In another embodiment, the nitrogen doped silicon carbide layer is formed by nitridation of a silicon carbide layer. Therein, a silicon carbide layer, prepared by a plasma process, is exposed to a plasma of a nitrating gas to form a nitrogen rich surface on the silicon carbide layer. The plasma treatment with an oxygen containing gas could be performed in a PECVD chamber, such as DxZ™ chamber or a Producer™ PECVD chamber, both of which are available from Applied Materials, Inc. of Santa Clara, Calif. In one embodiment, the substrate temperature is maintained in the range between about 100° C. to about 450° C. The nitrogen rich surface of the silicon carbide layer may include silicon nitride or silicon carbon nitride and is referred to herein as a nitrided surface. The nitrating gas is selected from the group including, but not limited to, ammonia (NH₃), nitrogen (N₂), nitrous oxide (N₂O), and combinations thereof. In addition, the nitridation process may include an inert gas such as argon (Ar) or helium (He). The as-deposited nitrogen doped silicon carbide layer contains about 1 to about 30 atomic percent nitrogen and has a dielectric constant of about 4.0 to about 5.0. Further details of the methods for depositing nitrogen doped silicon carbide layers by nitridation of silicon carbide layers are disclosed in commonly assigned U.S. Pat. No. 6,794,311, filed Jul. 10, 2001, which is incorporated herein by reference to the extent not inconsistent herewith.

[0035] In another embodiment, the spacer layer 126 is formed from carbon doped silicon nitride by reacting a gas mixture including a silicon source, a carbon source, and a nitrogen source. Herein the term “carbon doped silicon nitride” designates materials containing silicon, nitrogen, carbon, and optionally hydrogen, wherein the carbon content is less than the nitrogen content. Such a layer may be formed, for example, by reacting one or more nitrogen containing compounds with one or more organosilicon compounds. The deposition can be conducted in a PECVD chamber, such as Producer™ chamber. In one embodiment, the deposition temperature is between about 100° C. to about 500° C., and preferably between about 250° C. to about 450° C. The as-deposited carbon doped silicon nitride layer contains about 1 to about 30 atomic percent carbon and has a dielectric constant of about 4.0 to about 5.0. The dielectric constant of the carbon doped silicon nitride layer is tunable, in that it can be varied as a function of reaction pressure and the nitrogen source and/or concentration thereof in the gas mixture. Further details of the methods and apparatus for depositing carbon doped silicon nitride layers are disclosed in commonly assigned U.S. patent application Ser. No. 10/828,023, filed Apr. 19, 2004, and U.S. provisional patent application Ser. No. 60/525,241, filed Nov. 25, 2003, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0036] In another embodiment, the spacer layer 126 is formed from nitrogen doped silicon oxycarbide. Herein, the term “nitrogen doped silicon oxycarbide” is used to refer to compounds containing silicon, carbon, oxygen, and nitrogen. In one embodiment, the nitrogen doped silicon oxycarbide of the present invention is formed by reacting one or more organosilicon source gases with one or more oxygen source gases and one or more nitrogen source gases. The dielectric constant of the nitrogen doped silicon oxycarbide is between about 3.0 to about 5.0. In one embodiment, the deposition process can be conducted in a PECVD chamber and the deposition temperature is between about −20° C. to about 500° C., and preferably between about 170° C. to about 180° C. In one embodiment, after deposition, the deposited material is annealed at a temperature between about 100° C. to about 400° C. to reduce moisture content and to increase the solidity and hardness of the deposited material. In one embodiment, the deposited material is plasma treated at a temperature between about 300° C. to about 450° C. to reduce the surface's reactivity to subsequently deposited materials. The dielectric constant of the nitrogen doped silicon oxycarbide layer is tunable, in that it can be varied as a function of the reactants employed and the reactor temperature. Further details of the methods for depositing nitrogen doped silicon oxycarbide layers are disclosed in commonly assigned U.S. Pat. No. 6,656,837 and U.S. Pat. No. 6,627,532, both of which are incorporated herein by reference to the extent not inconsistent herewith.

[0037] While the abovementioned materials may be deposited as a single layer to form a sidewall spacer, the present invention is not so limited. One or more layers of material may be deposited sequentially or simultaneously under plasma conditions in plasma enhanced chemical vapor deposition reactors at temperature equaling to or less than 450° C. to produce a composite spacer layer having an overall k value of about 3.0 to about 5.0. This may be accomplished by applying one or more layers of material, each having a k value of about 3.0 to about 5.0. Alternatively, this may be accomplished by applying one or more layers of material, any of which may have a k value greater than or less than about 3.0 to about 5.0, such that the composite spacer layer has a k value of about 3.0 to about 5.0.

[0038] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.