Majority voter circuit design

[0001] 1. Field of the Invention

[0002] The present invention relates generally to the field of priority control, and more specifically to determining priority based on voting.

[0003] 2. Description of the Related Art

[0004] In digital computations, multiple input values may be received at a circuit with the requirement to a single resultant value based on the inputs received. The resultant value may be determined in various ways, one such way being the majority of values received, a technique called “voting.” For example, a series of 1s and 0s may be received as input, with the resultant value being either 1 or 0 depending on the quantity of each operand received. If more 0s are received than is, the result will be 0, and vice versa. The difficulty is quickly and efficiently determining the resultant value.

[0005] Circuits designed to employ majority voting have typically included a counting section and an operation section. The counting section determines the quantity of each available value received as input, such as two 0s, three is, seven 2s, and so forth, while the operation section adds and/or subtracts values received from the counting section. For eight distinct inputs, approximately seven separate circuit elements may be required to assess voting. If additional inputs are received, more circuit elements are typically required. If the number of input values or bits is N, the needed number of circuit elements or logic gates is proportional to N².

[0006] Such circuitry may consume significant amounts of static power, and may require a reference voltage or threshold to form a baseline. The hardware required to generate a reference voltage is frequently complex and consumes significant power.

[0007] While voting circuitry is simple, straightforward, and relatively well known, it would be desirable to offer a simple, straightforward mechanism or method that offers reduced complexity and power consumption and may provide for fewer circuits or components than existing designs.

[0013] FIG. 1 illustrates a previous 8-bit majority voter digital circuit. From FIG. 1, the first stage of the circuit, or counting stage 101, counts the number of is received as input bits using full adder (FA) circuits. Full adder circuit 103 adds inputs D0, D1, and D2, while full adder circuit 104 adds inputs D3, D4, and D5, and full adder circuit 105 adds inputs D6, D7, and “1,” or a value of 1. The result of each full adder circuit is a carry and a sum. The full adder circuits add the received bits according to the truth table shown in Table 1.

[0014]

	TABLE 1
	Input	Output
	C	A	B	S	C
	0	0	0	0	0
	1	0	0	1	0
	0	1	0	1	0
	1	1	0	0	1
	0	0	1	1	0
	1	0	1	0	1
	0	1	1	0	1
	1	1	1	1	1

[0015] The values of full adders 103, 104, and 105 feed into full adders 106 and 107, which operate according to Table 1 above. The output of full adders 106 and 107 feed to addition/subtraction element 102, which includes OR gate 108 and AND gate 109 in this configuration. OR gate 108 ORs the Carry value from full adder 106 with the Sum value of full adder 107, and AND gate 109 ANDs the value from OR gate 108 with the Carry value from full adder 107. The result from addition/subtraction element 102 is a four out of eight value, or majority voted value, from AND gate 109.

[0016] An alternate representation of the eight bit digital majority voter is illustrated in FIG. 2. FIG. 2 is an analog representation of a majority voter, with inputs D0 through D7 and resistors 201a–h summing into amplifier 202 and having a threshold value subtracted. The result is the four out of eight vote similar to that illustrated in FIG. 1. In FIG. 2, all values of current received become voltages, and if the sum of all voltages exceeds a threshold, defined as the 50 percent level of all values being high, the voted value is “1.” If the sum of all voltages does not exceed the 50 percent threshold, the voted value is “0.” A reference or threshold value is needed to implement the design.

[0017] FIG. 3 presents one embodiment of the present design. From FIG. 3, N bit inputs or input values are provided, with N/2 inputs on the right side in the embodiment shown and N/2 inputs on the left side. Switches 301 and 302 form two cross coupled PMOS transistors 303, also called a cross coupling arrangement, each connecting to NMON transistors 310, 311, and 312 in this embodiment, where more such devices may be included, and AND gates 313, 314, and 315, each having two inputs. On the right side, the two cross coupled PMOS transistors 303 connect to NMON transistors 320, 321, and 322, as well as NOR gates 323, 324, and 325, again each having two inputs, where the two inputs are identical to those to the AND gates on the left side of FIG. 3. As reflected by the ellipses in FIG. 3, additional NMON transistors and AND/NOR gates may be provided depending on the number of inputs received. The final element is summation unit 350 that collects the right side signals and subtracts the left side signals to provide a final value.

[0018] In operation, for the AND gates, the output is “1” only when both values received are “1.” The same two values passed to the NOR gate on the right side produce an output of “1” only when both inputs are “0.” The output of each gate connects to a pull down NMON transistor. Thus the number of ON transistors on the left side in the embodiment shown, employing the AND gates, equals the number of groups for which both inputs are “1,” and the number of ON transistors on the right on the right the number for which both inputs are “0.” For groups of two inputs where one value is “1” and the other “0,” neither transistor on the left or right side is ON. The result produced on the left side is the number of “11” groups while the number produced on the right side is the number of “00” groups. Since an “01” or a “10” pairing provide an equal number of “1” and “0” values, the majority can be determined by assessing whether more “11” groups exist than “00” groups. Thus if the number of ON transistors on the left side of the embodiment shown in FIG. 3 exceeds the number of ON transistors on the right side, more “1s” exist. If the number of ON transistors on the right side of the embodiment shown in FIG. 3 exceeds the number of ON transistors on the left side, more “0s” exist.

[0019] With the structure of the two cross coupled PMOS transistors 303, the voltage develops due to the different number of ON transistors on the two sides. The voltage difference may be sensed by a regular sense amplifier, shown as summation unit 350 in FIG. 3. No reference voltage is necessary in this embodiment.

[0020] Transistors on both sides may be well matched to achieve better results. Longer channel devices may be employed to reduce the mismatch. The implementation may provide a not-insignificant quantity of current flowing from switch 301 and switch 302 to the NMOS transistors presented.

[0021] Static current can be decreased by adding another PMOS transistor and employing an enabling signal. FIG. 4 illustrates such an implementation. From FIG. 4, switches 401 and 402 form two cross coupled PMOS transistors 403, each connected to enable element 475 and single voltage source Vcc. The two cross coupled PMOS transistors 403 are connected to NMON transistors 410, 411, and 412 and AND gates 413, 414, and 415, each having two inputs. On the right side, the two cross coupled PMOS transistors 403 connect to NMON transistors 420, 421, and 422 and then to NOR gates 423, 424, and 425, again each having two inputs, where the two inputs are identical to those to the AND gates on the left side of FIG. 4. Additional NMON transistors and AND/NOR gates may be provided depending on the number of inputs received. Summation unit 450 collects the right side signals and subtracts the left side signals to provide a final value. This enable signal and single Vcc input allow for enabling the top PMOS transistor 475 before the sense amplifier or summation unit 450 initiates operation, and this architecture permits turning off the top PMOS transistor after disabling the summation unit, reducing the likelihood of static current buildup.

[0022] It will be appreciated to those of skill in the art that the present design may be applied to other systems that perform voting, and is not restricted to the arbitration structures and processes described herein. Further, while specific circuits, inputs, and structures have been discussed herein, it is to be understood that more or less or different types of each may be employed while still within the scope of the present invention. Accordingly, any and all modifications, variations, or equivalent arrangements which may occur to those skilled in the art, should be considered to be within the scope of the present invention as defined in the appended claims.