US 7,224,182 B1Grant
Hybrid configurable circuit for a configurable IC
Issue Date:2007-05-29
•27 Claims
•37 Drawing Sheets
Abstract
Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.
Metadata
Inventors
- Brad Hutchings
- Herman Schmit
- Steven Teig
Application Information
Application Number:US 11/082,221
Filing Date:2005-03-15
Priority Date:2005-03-15
Art Unit:2819
Classifications
IPC:
G06F7/38H03K19/173
Patent Drawings (37 sheets)
Description
Cross Reference to Related Applications
[0001] This Application is related to the following applications: U.S. patent application Ser. No. 11/081,883, filed Mar. 15, 2005; U.S. patent application Ser. No. 11/269,141, filed Nov. 7, 2005; U.S. patent application Ser. No. 11/082,199, filed Mar. 15, 2005; U.S. patent application Ser. No. 11/081,850, filed Mar. 15, 2005; and U.S. patent application Ser. No. 11/269,168, filed Nov. 7, 2005.
Field of the Invention
[0002] The present invention is directed towards hybrid configurable circuit for a configurable IC.
Background of the Invention
[0003] The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks). These logic circuits are connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are surrounded by input/output blocks.
[0004] Like some other configurable IC's, the logic circuits and interconnect circuits of an FPGA are configurable. A configurable logic circuit can be configured to perform a number of different functions. Such a logic circuit typically receives input and configuration data. From the set of functions that the logic circuit can perform, the configuration data specifies a particular function that the logic circuit has to perform on the input data. A configurable interconnect circuit connects a set of input data to a set of output data. Such a circuit receives configuration data that specify how the interconnect circuit should connect its input data to its output data.
[0005] FPGA's have become popular as their configurable logic and interconnect circuits allow the FPGA's to be adaptively configured by system manufacturers for their particular applications. However, existing FPGA's as well as other existing configurable IC's do not provide robust multiplexer functionality. Specifically, the select lines of multiplexers in existing IC's are typically tied to memory cells that store configuration data. Hence, these multiplexers cannot be controlled by signals internally computed by the logic circuits of the IC's. This, in turn, limits the use of multiplexers in configurable IC's to applications that do not need to make the multiplexing choices based on internally computed IC signals.
[0006] Therefore, there is a need in the art for configurable IC's that use novel multiplexer circuits that can be controlled by signals internally computed by the IC's. There is also a need in the art for configurable IC's that have novel architectures that use such multiplexer circuits. There is further a need for configurable IC's that have devices that can take advantage of such novel multiplexer circuits.
Summary of the Invention
[0007] Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.
Brief Description of the Drawings
[0008] The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
[0009] FIG. 1 illustrates a block diagram of an interconnect circuit.
[0010] FIG. 2 illustrates an example of a multiplexer.
[0011] FIG. 3 illustrates an example of a configurable four-to-one multiplexer that receives configuration data from a set of storage elements.
[0012] FIG. 4 illustrates a configurable logic circuit.
[0013] FIG. 5 illustrates an example of a configurable node array that includes configurable nodes that are arranged in rows and columns.
[0014] FIG. 6 illustrates an example of a connection between two circuits.
[0015] FIG. 7 illustrates an example of another connection between two circuits.
[0016] FIG. 8 illustrates a full UMUX.
[0017] FIG. 9 illustrates a hybrid UMUX.
[0018] FIG. 10 illustrates that some embodiments place the UMUX's between the circuits of a circuit arrangement according to no particular pattern.
[0019] FIG. 11 illustrates that some embodiments place UMUX's between the circuits according to a particular pattern that repeats across the entire circuit arrangement or a portion of the arrangement.
[0020] FIG. 12 illustrates an example where a number of UMUX's that are dispersed between the circuits of a circuit arrangement, form an arrangement of their own.
[0021] FIG. 13 illustrates an example of arranging UMUX's in two arrays that are dispersed between the circuits of a circuit arrangement.
[0022] FIG. 14 illustrates an example of a UMUX that is positioned in an arrangement of circuit elements.
[0023] FIG. 15 illustrates a circuit arrangement having logic circuits, interconnect circuits, and UMUX's.
[0024] FIG. 16 illustrates an example of a circuit in a configurable IC's circuit arrangement that includes complex logic circuits that are formed by multiple logic and interconnect circuits.
[0025] FIG. 17 illustrates an example of “supering” multiple logic circuits that use of UMUX's.
[0026] FIG. 18 illustrates one such prior configurable circuit arrangement.
[0027] FIG. 19 illustrates a configurable circuit arrangement that includes numerous configurable interconnect circuits, UMUX's, and logic circuits.
[0028] FIG. 20 illustrates an example of using UMUX's to write data to a non-configurable memory array in a configurable circuit arrangement.
[0029] FIG. 21 illustrates the use of UMUX's to implement circuit arrangements with configurable shift operations.
[0030] FIG. 22 illustrates an example of a circuit arrangement that includes numerous logic circuits, interconnect circuits, and HUMUX's.
[0031] FIG. 23 illustrates an example of a circuit arrangement with numerous logic circuits and routing interconnect circuits.
[0032] FIG. 24 illustrates a circuit arrangement that has numerous logic circuits and interconnect circuits arranged in numerous rows and columns.
[0033] FIG. 25 illustrates a two-input multiplexer that receives variables “b” and “c” on its input lines and variable “a” on its select line.
[0034] FIG. 26 illustrates that the multiplexer can perform the AND function by routing a binary 0 to its second input.
[0035] FIG. 27 illustrates that routing a binary 1 to the multiplexer's first input, allows the multiplexer to perform the OR function, which is one of the NPN equivalent functions of the AND function.
[0036] FIG. 28 illustrates a two-input multiplexer that implements an XOR function.
[0037] FIG. 29 illustrates an example of an HUMUX that has a core multiplexer that operates like the multiplexer of FIGS. 25–27 as it receives the user signal “a” through the select multiplexer
[0038] FIG. 30 illustrates another example of an HUMUX that has a core multiplexer that operates like the multiplexer of FIG. 28 as it receives the user signal “a” through the select multiplexer.
[0039] FIG. 31 illustrates a recursive process that a synthesizer can perform to decompose a function.
[0040] FIG. 32 illustrates an eight-to-one HUMUX that is formed by four multiplexers.
[0041] FIG. 33 illustrates a multiplexer that is used as the multiplexer in FIG. 32 .
[0042] FIG. 34 illustrates a CPL implementation of a two-tier multiplexer structure for generating the second signal S1 and its complement.
[0043] FIG. 35 illustrates an example of the signals CLK, ST0, and ST1.
[0044] FIG. 36 illustrates a circuit implementation of the combined multiplexer structure.
[0045] FIG. 37 illustrates another implementation of an HUMUX, which can operate based on a configuration-derived select signal S0, a first user signal US0, or a second user signal US1.
[0046] FIG. 38 illustrates a circuit implementation of the combined multiplexer structure of FIG. 37 .
[0047] FIG. 39 illustrates another alternative circuit structure for one set of multiplexers in a two-tiered multiplexer structure of some embodiments.
[0048] FIG. 40 illustrates an architecture that is formed by numerous configurable tiles that are arranged in an arrangement with multiple rows and columns.
[0049] FIGS. 41–45 illustrate the connection scheme used to connect the multiplexers of one tile with the LUT's and multiplexers of other tiles.
[0050] FIG. 46 illustrates a possible physical architecture of the configurable IC illustrated in FIG. 40 .
[0051] FIG. 47 illustrates a portion of a configurable IC of some embodiments of the invention.
[0052] FIG. 48 illustrates a detailed example of configuration data that configure the circuits to perform particular operations.
[0053] FIG. 49 illustrates a system on chip (“SoC”) implementation of a configurable IC.
[0054] FIG. 50 illustrates a system in package (“SiP”) implementation for a configurable IC.
[0055] FIG. 51 conceptually illustrates a more detailed example of a computing system that has an IC, which includes one of the invention's configurable circuit arrangements that were described above.
Detailed Description of the Invention
[0056] In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. For instance, not all embodiments of the invention need to be practiced with the specific number of bits and/or specific devices (e.g., multiplexers) referred to below. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.
I. Terms and Concepts
[0057] A configurable IC is an IC that has configurable circuits. In some embodiments, a configurable IC includes configurable computational units (e.g., configurable logic circuits) and configurable routing circuits for routing the signals to and from the configurable computation units. In addition to configurable circuits, a configurable IC also typically includes non-configurable circuits (e.g., non-configurable logic circuits, interconnect circuits, memories, etc.).
[0058] A configurable circuit is a circuit that can “configurably” perform a set of operations. Specifically, a configurable circuit receives “configuration data” that specifies the operation that the configurable circuit has to perform in the set of operations that it can perform. In some embodiments, configuration data is generated outside of the configurable IC. In these embodiments, a set of software tools typically converts a high-level IC design (e.g., a circuit representation or a hardware description language design) into a set of configuration data that can configure the configurable IC (or more accurately, the configurable IC's configurable circuits) to implement the IC design.
[0059] Examples of configurable circuits include configurable interconnect circuits and configurable logic circuits. An interconnect circuit is a circuit that can connect an input set to an output set in a variety of manners. FIG. 1 presents a block diagram of a controllable interconnect circuit. This circuit 100 has a set of input terminals 105, a set of output terminals 110, and a set of control terminals 115. The interconnect circuit 100 receives control data along its control terminals 115 that causes the interconnect circuit to connect its input terminal set 105 to its output terminal set 110 in a particular manner.
[0060] An interconnect circuit can connect two terminals or pass a signal from one terminal to another by establishing an electrical path between the terminals. Alternatively, an interconnect circuit can establish a connection or pass a signal between two terminals by having the value of a signal that appears at one terminal appear at the other terminal. In connecting two terminals or passing a signal between two terminals, an interconnect circuit in some embodiments might invert the signal (i.e., might have the signal appearing at one terminal inverted by the time it appears at the other terminal). In other words, the interconnect circuit of some embodiments implements a logic inversion operation in conjunction to its connection operation. Other embodiments, however, do not build such an inversion operation in some or all of their interconnect circuits.
[0061] A multiplexer is one example of an interconnect circuit. A multiplexer is a device that has k inputs, n outputs, and s select lines. The select lines typically direct the multiplexer to output n of its k inputs along its n outputs. FIG. 2 illustrates an example of a multiplexer. This example is a four-to-one multiplexer 200 that connects one of its four input lines 105 to its output line 205 based on the control signals 115 that it receives along its two select lines.
[0062] A configurable interconnect circuit is an interconnect circuit that can configurably perform a set of connection operations. In some embodiments, a configurable interconnect circuit only receives configuration data along its set of control lines. Also, in some embodiments, all of the configurable interconnect circuit's control lines are permanently tied to configuration data. Specifically, in these embodiments, the configurable interconnect circuit's control lines receive configuration data either directly from the storage elements that store the configuration data, or through an indirect connection to these storage elements via one or more interconnect circuits that do not receive configuration data along their control terminals.
[0063] FIG. 3 illustrates an example of a configurable four-to-one multiplexer 300 that receives configuration data from a set of storage elements 320 (e.g., a set of memory cells, such as SRAM cells). This multiplexer 300 connects one of its four input terminals 105 to its output terminal 205 based on the configuration data 115 that is output from the storage elements 320. In other words, the configuration data specify how the interconnect circuit 300 should connect the input terminal set 105 to the output terminal 205.
[0064] The multiplexer 300 is said to be configurable, as the configuration data set “configures” this multiplexer to use a particular connection scheme that connects its input and output terminal sets in a desired manner. Examples of configurable interconnect circuits can be found in Architecture and CAD for Deep-Submicron FPGAs, Betz, et al., ISBN 0792384601, 1999; and Design of Interconnection Networks for Programmable Logic, Lemieux, et al., ISBN 1-4020-7700-9, 2003. Other examples of configurable interconnect circuits can be found in U.S. patent application Ser. No. 10/882,583, entitled “Configurable Circuits, IC's, and Systems,” filed on Jun. 30, 2004. This application is incorporated in the present application by reference.
[0065] A logic circuit is a circuit that can perform a function on a set of input data that it receives. A configurable logic circuit is a logic circuit that can configurably perform a set of functions. In some embodiments, a configurable logic circuit only receives configuration data along its set of control lines. In some embodiments, all of the configurable logic circuit's control lines are permanently tied to configuration data. Specifically, in these embodiments, the configurable logic circuit's control lines receive configuration data either directly from the storage elements that store the configuration data, or through an indirect connection to these storage elements via one or more interconnect circuits that do not receive configuration data along their control lines.
[0066] FIG. 4 illustrates a configurable logic circuit. As shown in this figure, a configurable logic circuit 400 is a logic circuit that receives configuration data along its set of control lines 410. In this example, the configurable logic circuit receives configuration data from a set of storage elements (e.g., SRAM's) 415. The logic circuit 400 is said to be configurable, as the configuration data set “configures” the logic circuit to perform a particular function (from its set of functions) on the input data received along its input terminals 405 to produce its output data (that is provided along its output terminal set 420). The logic circuit 400 can be reconfigured by writing new data in the storage elements 415.
[0067] Some examples of logic circuits include look-up tables (LUT's), universal logic modules (ULM's), sub-ULM's, multiplexers, and PAL's/PLA's. In addition, logic circuits can be complex logic circuits formed by multiple logic and interconnect circuits. Examples of simple and complex logic circuits can be found in Architecture and CAD for Deep-Submicron FPGAs, Betz, et al., ISBN 0792384601, 1999; and Design of Interconnection Networks for Programmable Logic, Lemieux, et al., ISBN 1-4020-7700-9, 2003. Other examples of configurable logic circuits are provided in the above-incorporated U.S. patent application Ser. No. 10/882,583.
[0068] As further described below, multiplexers can be used as the logic circuits of some embodiments of the invention. Also, some embodiments use non-configurable logic circuits (i.e., logic circuits that do not receive configuration data or any other control signals). These logic circuits are simple computation circuits that perform a particular computation on an input data set.
[0069] A volatile configurable circuit is a configurable circuit that directly or indirectly receives its configuration data from a volatile memory storage. The volatile storage is typically part of the configurable circuit or it is placed adjacent to the configurable circuit within a circuit array that contains the configurable circuit. For instance, the multiplexer 300 is a volatile configurable multiplexer as its configuration data is stored in two volatile storage elements 320 of the multiplexer. Similarly, the logic circuit 400 is a volatile circuit as its configuration data is stored in its four storage elements 415. However, the volatile storage does not need to be part of or adjacent to the configurable circuit.
[0070] A user-design signal within a configurable IC is a signal that is generated by a circuit (e.g., logic circuit) of the configurable IC. The word “user” in the term “user-design signal” connotes that the signal is a signal that the configurable IC generates for a particular application that a user has configured the IC to perform. User-design signal is abbreviated to user signal in some of the discussion below.
[0071] In some embodiments, a user signal is not a configuration or clock signal that is generated by or supplied to the configurable IC. In some embodiments, a user signal is a signal that is a function of at least a portion of the configuration data received by the configurable IC and at least a portion of the inputs to the configurable IC. In these embodiments, the user signal can also be dependent on (i.e., can also be a function of) the state of the configurable IC. The initial state of a configurable IC is a function of the configuration data received by the configurable IC and the inputs to the configurable IC. Subsequent states of the configurable IC are functions of the configuration data received by the configurable IC, the inputs to the configurable IC, and the prior states of the configurable IC.
[0072] A circuit array is an array with several circuit elements that are arranged in several rows and columns. One example of a circuit array is a configurable node array, which is an array formed by several configurable circuits (e.g., configurable logic and/or interconnect circuits) arranged in rows and columns. In some cases, all the circuit elements in a configurable node array are configurable circuit elements. For instance, FIG. 5 illustrates an example of a configurable node array 500 that includes 208 configurable nodes 505 that are arranged in 13 rows and 16 columns. Each configurable node in such a configurable node array is a configurable circuit that includes one or more configurable sub-circuits. In other cases, the circuit elements in a configurable node array also include non-configurable circuit elements.
[0073] In some embodiments, each configurable node in a configurable node array is a simple or complex configurable logic circuit. In some embodiments, each configurable node in a configurable node array is a configurable interconnect circuit. In such an array, a configurable node (i.e., a configurable interconnect circuit) can connect to one or more logic circuits. In turn, such logic circuits in some embodiments might be arranged in terms of another configurable logic-circuit array that is interspersed among the configurable interconnect-circuit array.
[0074] Some embodiments might organize the configurable circuits in an arrangement that does not have all the circuits organized in an array with several aligned rows and columns. Accordingly, instead of referring to configurable circuit arrays, the discussion below refers to configurable circuit arrangements. Some arrangements may have configurable circuits arranged in one or more arrays, while other arrangements may not have the configurable circuits arranged in an array.
[0075] In some embodiments, some or all configurable circuits in a circuit arrangement have the same or similar circuit structure. For instance, in some embodiments, some or all the circuits have the exact same circuit elements (e.g., have the same set of logic gates and circuit blocks and/or same interconnect circuits), where one or more of these identical elements are configurable elements. One such example would be a set of circuits positioned in an arrangement, where each circuit is formed by a particular set of logic and interconnect circuits. Having circuits with the same circuit elements simplifies the process for designing and fabricating the IC, as it allows the same circuit designs and mask patterns to be repetitively used to design and fabricate the IC.
[0076] In some embodiments, the similar configurable circuits not only have the same circuit elements but also have the same exact internal wiring between their circuit elements. For instance, in some embodiments, a particular set of logic and interconnect circuits that are wired in a particular manner forms each circuit in a set of configurable circuits that are in a configurable circuit arrangement. Having such circuits further simplifies the design and fabrication processes as it further simplifies the design and mask making processes.
[0077] Also, some embodiments use a circuit arrangement that includes numerous configurable and non-configurable circuits that are placed in multiple rows and columns. In addition, within the above described circuit arrangements (e.g., arrays), some embodiments disperse other circuits (e.g., memory blocks, macro blocks, etc.).
[0078] Several figures below illustrate several direct connections between circuits in a circuit arrangement. A direct connection between two circuits in an circuit arrangement is an electrical connection between the two circuits that is achieved by (1) a set of wire segments that traverse through a set of the wiring layers of the IC, and (2) a set of vias when two or more wiring layers are involved.
[0079] In some embodiments, a connection between two circuits in a circuit arrangement might also include a set of buffer circuits in some cases. In other words, two circuits are connected in some embodiments by a set of wire segments that possibly traverse through a set of buffer circuits and a set of vias. Buffer circuits are not interconnect circuits or configurable logic circuits. In some embodiments, buffer circuits are part of some or all connections. Buffer circuits might be used to achieve one or more objectives (e.g., maintain the signal strength, reduce noise, alter signal delay, etc.) along the wire segments that establish the direct connections. Inverting buffer circuits may also allow an IC design to reconfigure logic circuits less frequently and/or use fewer types of logic circuits. In some embodiments, buffer circuits are formed by one or more inverters (e.g., two or more inverters that are connected in series).
[0080] FIGS. 6 and 7 illustrate examples of two connections, each between two circuits in an arrangement. Each of these connections has one or more intervening buffer circuits. Specifically, FIG. 6 illustrates an example of a connection 615 between two circuits 605 and 610. As shown in this figure, this connection has an intervening buffer circuit 620. In some embodiments, the buffer circuit 620 is an inverter. Accordingly, in these embodiments, the connection 615 inverts a signal supplied by one circuit 605 to the other circuit 610.
[0081] FIG. 7 illustrates an example of a connection 715 between two circuits 705 and 710. As shown in this figure, this connection 715 has two intervening buffer circuits 720 and 725. In some embodiments, the buffer circuits 720 and 725 are inverters. Hence, in these embodiments, the connection 715 does not invert a signal supplied by circuit 705 to the other circuit 710.
[0082] Alternatively, the intermediate buffer circuits between the logic and/or interconnect circuits can be viewed as a part of the devices illustrated in these figures. For instance, the inverters that can be placed after the devices 705 and 710 can be viewed as being part of these devices. Some embodiments use such inverters in order to allow an IC design to reconfigure logic circuits less frequently and/or use fewer types of logic circuits
[0083] Several figures below “topologically” illustrate several direct connections between circuits in an arrangement. A topological illustration is an illustration that is only meant to show a direct connection between two circuits without specifying a particular geometric layout for the wire segments that establish the direct connection.
II. UMUX
[0084] Some embodiments are configurable IC's that have “UMUX's”. A UMUX is a multiplexer that receives user-design signals for at least one of its data inputs and one of its select inputs. A UMUX might receive a user-design signal directly from a configurable logic circuit or indirectly through one or more intermediate configurable interconnect circuits.
[0085] Two kinds of UMUX's are full UMUX's and hybrid UMUX's. A full UMUX (or FUMUX) is a UMUX that receives user-design signals for all of its select signals. FIG. 8 illustrates a full UMUX 800. This UMUX has a set of input terminals 805, an output terminal 810, and a set of select terminals 815. The UMUX 800 is a four-to-one multiplexer that connects one of its four data inputs 805 to its data output 810 based on the value of the two user-signals that it receives along its select terminals 815.
[0086] A hybrid UMUX (or HUMUX) is a UMUX that can receive user-design signals, configuration data, or both user-design signals and configuration data for its select signals. FIG. 9 illustrates an HUMUX 900. This HUMUX includes two two-to-one multiplexers 920, a four-to-one multiplexer 925, a set of input terminals 905, an output terminal 910, and a set of select terminals 915. From the outside, the HUMUX looks like a four-to-one multiplexer that has four data inputs 905, one data output 910, and four select terminals 915. Also, from the outside, the HUMUX looks like it passes one of its four data inputs 905 to its one data output 910 based on the value of two of the four signals that it receives along its four select lines 915.
[0087] Internally, the two two-to-one multiplexers 920 pass two of the signals from the four select lines 915 to the two select terminals 940 of the four-to-one multiplexer 925. As shown in FIG. 9 , each two-to-one multiplexer 920 receives two input signals, which include one user-design signal and one stored configuration signal stored in a storage element 945. Each of the two-to-one multiplexers 920 outputs one of the two input signals that it receives based on the configuration bit that it receives along its select line 950. Although FIG. 9 illustrates two configuration bits stored in two storage elements, other embodiments might drive both multiplexers 920 off one configuration bit that is stored in one storage element.
[0088] The two signals output by the two multiplexers 920 then serve as the select signals of the multiplexer 925, and thereby direct this multiplexer to output on line 910 one of the four input signals that it receives on lines 905. The two multiplexers 920 can output on lines 940 either two user-design signals, two configuration signals, or one user-design signal and one configuration signal. Accordingly, through the two multiplexers 920, the operation of the multiplexer 925 can be controlled by two user-design signals, two configuration signals, or a mix of user/configuration signals.
[0089] References to UMUX's in the description below should be construed to cover either a FUMUX or an HUMUX.
III. UMUX Architectures
[0090] Different embodiments of the invention use UMUX's differently in different configurable IC architectures. Some embodiments have a number of UMUX's dispersed between the circuits of a circuit arrangement. FIGS. 10 and 11 illustrate two such embodiments. FIG. 10 illustrates that some embodiments place the UMUX's 1005 between the circuits 1010 of a circuit arrangement 1000 according to no particular pattern. FIG. 11 , on the other hand, illustrates that some embodiments place UMUX's 1105 between the circuits 1110 according to a particular pattern that repeats across the entire circuit arrangement 1100 or a portion of the arrangement. In FIG. 11 , the pattern that is repeated is one that is formed by five UMUX's 1105a–1105e.
[0091] The circuits (e.g., 1110 or 1010) in such circuit arrangements are all logic circuits in some embodiments, while they are interconnect circuits in other embodiments. In yet other embodiments, the circuits (e.g., 1110 or 1010) in the circuit arrangement are both logic and interconnect circuits. Also, in some embodiments, the circuit arrangement is a configurable circuit arrangement. Thus, in these embodiments, all the circuits in the circuit arrangement are configurable circuits (i.e., all the circuits are configurable logic circuits, configurable interconnect circuits, or a mixture of configurable logic and interconnect circuits). In some of these embodiments, all or some of the configurable circuits are configurable volatile circuits (i.e., they are configurable volatile logic and/or interconnect circuits).
[0092] In the embodiments that disperse UMUX's between the circuits of a circuit arrangement, the UMUX's can be arranged in one or more arrangements. FIG. 12 illustrates an example where a number of UMUX's 1205, that are dispersed between the circuits 1210 of a circuit arrangement, form an arrangement of their own. FIG. 13 illustrates an example of arranging UMUX's 1305 and 1315 in two arrays that are dispersed between the circuits 1310 of a circuit arrangement. Specifically, the UMUX's 1305 form one array, while the UMUX's 1315 form another array.
[0093] Some embodiments position the UMUX's in a circuit arrangement with other types of circuits. FIG. 14 illustrates an example of a UMUX 1405 that is positioned in an arrangement of circuit elements 1410. This UMUX receives input signals from two circuit elements 1410a and 1410b, and receives select signals from two circuits elements 1410c and 1410d. The UMUX 1405 then outputs a signal to circuit element 1410e. All the circuit elements 1410 are configurable circuits (e.g., configurable logic and/or interconnect circuits) in some embodiments. Also, in some embodiments, all these configurable elements are volatile elements. In other embodiments, only some of the circuit elements 1410 are volatile configurable circuit elements, while other circuit elements are non-volatile configurable circuit elements or non-configurable circuit elements.
[0094] UMUX's can receive user-design signals directly from logic circuits, or indirectly from logic circuits through intervening interconnect circuits. FIG. 15 illustrates a circuit arrangement having logic circuits 1510, interconnect circuits 1505, and UMUX's 1515. In this example, a UMUX 1515a receives a user-design signal, as a select signal, directly from logic circuit 1510a, and receives a user-design signal, as an input signal, directly from the logic circuit 1510b. This figure also illustrates a UMUX 1515b that receives a user-design signal as an input signal from logic circuit 1510d through intervening interconnect circuits 1505b and 1505c. It also illustrates this UMUX 1515b receiving a user-design signal as a select signal from logic circuit 1510c through interconnect circuit 1505a. Finally, this figure illustrates a UMUX 1515c that receives a first user-design signal directly from a logic circuit 1510d, and a second user-design signal indirectly from the logic circuit 1510b through the interconnect circuit 1505d. In some embodiments, the intervening interconnect circuits 1505a, 1505b, 1505c, and 1505d are volatile configurable interconnect circuits.
[0095] In the examples illustrated in FIGS. 10–15 , UMUX's are part of or are dispersed within a large circuit arrangement that has numerous circuits (e.g., tens, hundreds, thousands, etc. of circuits). In other words, these examples illustrate the use of UMUX's at a macrolevel in configurable IC's. However, in some embodiments, UMUX's are used at the microlevel in a circuit arrangement (e.g., within a circuit or circuits of a large circuit or circuit arrangement) of a configurable IC. For instance, in some embodiments, the circuits in a configurable IC's circuit arrangement include complex logic circuits that are formed by multiple logic and interconnect circuits. In such embodiments, complex logic circuits can be formed by one or more UMUX's.
[0096] FIG. 16 illustrates an example of such an embodiment. Specifically, this figure illustrates a circuit arrangement 1600 that includes a number of logic circuits 1605 arranged in a number of rows and columns. This figure further illustrates an exploded view 1610 of one of the logic circuits 1605a. As shown in this view, the logic circuit 1605a is formed by four UMUX's 1615 and one interconnect circuit 1620. Each of the UMUX's receives input signals and user-design signals, which direct the UMUX to output one of its input signals. The UMUX output signals are provided to the configurable interconnect circuit 1620, which then outputs one or more of these output signals as the output of the logic circuit 1605a.
[0097] In some embodiments, all the logic circuits 1605 in the array 1600 have the structure of the logic circuit 1605a. In other embodiments, only some of the logic circuits 1605 have this structure, while other logic circuits have a different structure. For instance, some embodiments use configurable logic circuits in combination with the UMUX-based logic circuits (i.e., with logic circuits that are similar to the circuit 1605a). Other embodiments use non-configurable logic circuits with the UMUX-based logic circuits. Yet other embodiments use a combination of configurable logic circuits, non-configurable logic circuits, and UMUX-based logic circuits.
IV. Applications
[0098] A. Supering
[0099] Some embodiments use UMUX's for “supering” multiple logic circuits. Supering refers to combining the outputs of multiple logic circuits to form a more complex logic circuit. FIG. 17 illustrates one such embodiment. This figure illustrates a macro-level view of a configurable circuit arrangement 1700 with numerous (e.g., hundreds, thousands, etc.) circuits arranged in rows and columns. This array includes numerous configurable volatile logic circuits 1705, configurable volatile interconnect circuits 1710, and UMUX's 1715.
[0100] As shown in FIG. 17 , one UMUX 1715a receives as input signals the outputs of two logic circuits 1705a and 1705b through two intervening configurable interconnect circuits 1710a and 1710b. This UMUX 1715a also receives as a select signal the output of a logic circuit 1705c through an intervening configurable interconnect circuit 1710c, which is a volatile configurable circuit in some embodiments. Based on the received select signal, the UMUX 1715a performs a function on its received input signals. The UMUX performs this function by outputting one of its input signals along its output line based on the value of the received select signal.
[0101] The circuit structure illustrated in FIG. 17 can be used to implement a four-input LUT with two three-input LUT's and a UMUX. In other words, if the logic circuits 1705a and 1705b are three-input LUT's, the UMUX 1715a can be used to create a “super” four-input LUT by combining the outputs of three-input LUT's 1705a and 1705b based on the output of the logic circuit 1705c. In this case, the supered four-input LUT is the circuit formed by LUT's 1705a and 1705b, the interconnect circuit 1710a, and the UMUX 1715a.
[0102] B. Memory
[0103] Some embodiments of the invention use UMUX's to implement configurable circuit arrangements with configurable memory read and write operations. Some configurable IC's today have configurable circuit arrangements with configurable memory structures. FIG. 18 illustrates one such prior configurable circuit arrangement 1800. This circuit arrangement includes numerous configurable circuits 1805 that are arranged in rows and columns. It also includes two configurable memories 1810. Each of these two memories includes a memory array 1820, i/o circuitry 1825, and configuration-storing storage elements 1830.
[0104] The configuration-storing storage elements 1830 store configuration data. This data configures each memory to input and/or output a certain number of bits. Specifically, the memory array 1820 receives an address along its address line 1835. During a write operation, the address identifies a location in the memory to which the i/o circuitry needs to write a fixed number of bits. Alternatively, during a read operation, this address identifies a location in the memory from which the i/o circuitry needs to read a fixed number of bits (e.g., 8 bits).
[0105] The i/o circuitry 1825 receives configuration data from the storage elements 1830. Based on the received configuration data, the i/o circuitry then outputs a sub-set of the data bits (e.g., outputs 4 bits) that it receives from the memory array 1820 during a read operation. In other words, the number of bits that the i/o circuitry might output from a location in the memory array depends on the configuration data stored in the configuration-storing storage elements 1830.
[0106] Requiring the memories 1810 to have configuration storage elements 1830 and/or circuitry responsive to these storage elements complicates the structure of these memories, and thereby increases their size. Accordingly, to use simpler memory structures in a configurable circuit arrangement of a configurable IC, some embodiments use UMUX's to implement configurable circuit arrangements with configurable memory read operations.
[0107] FIG. 19 illustrates one such embodiment. This figure illustrates a configurable circuit arrangement 1900 that includes numerous configurable interconnect circuits 1905, UMUX's 1910, and logic circuits 1920. The interconnect circuits 1905 are arranged in an arrangement with several rows and columns. Dispersed within this arrangement of interconnect circuits are the logic circuits, which are also arranged in an arrangement with multiple rows and columns. The UMUX's are dispersed within these arrangements. Several memories 1915 are also dispersed within these arrangements. In some embodiments, these memories all have the same width. For instance, in some cases, these memories are 256 byte memories that output eight-bit words.
[0108] FIG. 19 illustrates two examples for reading out data from a non-configurable memory 1915a. The output of each of these memories is always eight-bits wide. To read out a byte of data (i.e., to read out eight bits of data), each memory (e.g., 1915a) receives an eight-bit address that identifies one of 256 locations in the memory.
[0109] As shown in FIG. 19 , the eight-bit wide output of the memory 1915a can be supplied directly to a logic circuit 1920a through an interconnect circuit 1905a. Alternatively, as shown in this figure, a four-bit wide output of the memory 1915a can be supplied to the logic circuit 1920b through a UMUX 1910a. Specifically, through the interconnect circuit 1905a, the eight-bit wide output can be supplied to the UMUX 1910a. The UMUX 1910a is an 8×4 multiplexer that outputs either its bottom four input signals or its top four input signals to a logic circuit 1920b. Specifically, the UMUX 1910a receives a signal 1925 on its select line. Based on the value of this signal, the UMUX then selects its bottom four input signals or its top four input signals to output.
[0110] The bit 1925 that the UMUX 1910a receives can be viewed as a ninth address bit that helps identify and output a 4-bit word from the memory 1915a. In other words, the UMUX 1910a allows the 256×8 memory, which is accessed with an eight-bit address, to be treated as a 512×4 memory that is accessible with a nine-bit address.
[0111] FIG. 20 illustrates an example of using UMUX's to write data to a non-configurable memory array 2015 in a configurable circuit arrangement 2000. In this figure, the memory array has a set 2005 of four UMUX's to the right of the memory array. In the example illustrated in FIG. 20 , the UMUX set 2005 is used for writing data to the memory array. The output of the UMUX set 2005 connects to the memory array through a set of configurable interconnects 2025, while the input of the UMUX set 2005 connects to the memory array through a set of configurable interconnects 2020.
[0112] During a write operation, an address is supplied to the memory array 2015 that identifies a four-bit location in this array. This four-bit location is a location to which the memory array will write four bits that are supplied through the UMUX set 2005 via the interconnect set 2025. Each UMUX in the UMUX set 2005 receives two bits. During a write operation, one bit comes from the user design, while the other bit comes from the memory. Specifically, during a write operation, the memory array 2015 provides the four bits currently stored in the location identified by the received address to the UMUX set 2005 through the interconnect set 2020.
[0113] During the write operation, each of the UMUX's 2005 receives a user signal on its select line that specifies, which of its two inputs (the user design input or the feedback, memory input) it should output. Through configurable interconnect set 2025, the outputs of the UMUX's are then provided to the memory array 2015 as data to write to the identified four-bit location.
[0114] The advantage of the UMUX-driven approach for accessing memories is that it allows all the memories in a configurable circuit arrangement to have the adjustable widths without requiring the use of configuration data. For instance, in the example illustrated in FIG. 20 , the UMUX set 2005 allows two bits to be written in a memory that always reads and writes on a four-bit basis. Specifically, by providing one additional address bit that is decoded to provide two UMUX select signals, two UMUX provide two new bits to the memory while the other two UMUX write back to the memory two bits that it currently stores.
[0115] The UMUX-driven approach also allows the memories to have a relatively simple structure as these memories no longer need to store configuration data or circuitry responsive to configuration data. Moreover, the UMUX-driven approach allows the user to effectively have different memory operations with simpler memory structures simply through the programmable operation of the IC.
[0116] C. Shifter
[0117] Some embodiments of the invention use UMUX's to implement circuit arrangements with configurable shift operations. FIG. 21 illustrates one such embodiment. Specifically, this figure illustrates a circuit arrangement 2100 that has numerous circuits arranged in numerous rows and columns. These circuits include volatile configurable interconnect circuits 2105, 2110, and 2115, and logic circuits 2120, 2125 and 2130.
[0118] The logic circuit 2120 includes four four-to-one UMUX's 2135. Each of these UMUX's serves as a shifter. These UMUX's can be used to seamlessly perform a variable shift operation whenever the output of a logic circuit in the arrangement 2100 needs to be shifted by a certain number of bits that is to be determined by the output of another logic circuit. All that needs to be done is to supply to the UMUX's through configurable interconnect circuits (1) the bits that need to be shifted, and (2) the bits that need to specify the amount of the shift.
[0119] FIG. 21 illustrates one example of configurably connecting the UMUX's 2135 to logic circuits in the circuit arrangement 2100. Specifically, this figure illustrates the supplying of the output of logic circuit 2125 to the UMUX's 2135 through the configurable interconnect circuit 2105. In this example, the output of the logic circuit 2125 is four bits wide. Also, in this example, each UMUX 2135 receives the four-bit output of the logic circuit 2125 in a different order, as shown in FIG. 21 .
[0120] FIG. 21 also illustrates the supplying of the output of the logic circuit 2130 to the UMUX's 2135 through the configurable interconnect circuit 2110. In this example, the output of the logic circuit 2130 is two-bits wide. The value of these two bits cause each of the UMUX's 2135 to output a particular one of their four input bits. This output operation of the UMUX's 2135 can result in a shift of the output of the logic circuit 2125. For instance, lets assume that the logic circuit 2130 output is a binary value of 10. For the order of the inputs of the UMUX's 2135 illustrated in FIG. 21 , this output from logic circuit 2130 causes the UMUX's 2135 to output 2301 (where 0, 1, 2, 3 refer to bits in the four bit output from the logic circuit 2125 and the order of that these bits are received is 0123).
[0121] D. Interconnect Circuits
[0122] An HUMUX blurs the line between a communication circuit and a computation circuit. In a configurable IC that can be reconfigured in real time (i.e., in a reconfigurable IC), an HUMUX can serve as a logic circuit during some clock cycles, while serving as an interconnect circuit during other clock cycles. This ability is advantageous in a variety of contexts.
[0123] 1. Hybrid Routing Mux and Logic Circuit
[0124] An HUMUX can be used as a hybrid routing multiplexer and logic circuit in a circuit arrangement of a configurable IC. In a circuit arrangement, a routing multiplexer is an interconnect circuit that connects other logic and/or interconnect circuits in the arrangement. In some embodiments, a routing multiplexer either provides its output to several logic and/or interconnect circuits (i.e., has a fan out greater than 1), or provides its output to other interconnect circuits. An HUMUX acts as a routing mux (i.e., does not perform any computation and only serves to relay signals from other circuits) when its operation is completely controlled by configuration data. On the other hand, an HUMUX serves as a logic circuit when its operation is not completely controlled by configuration data.
[0125] FIG. 22 illustrates an example of a circuit arrangement 2200 that includes numerous logic circuits 2205, interconnect circuits 2210, and HUMUX's 2215. In some embodiments, some or all of the logic circuits and/or interconnect circuits are configurable circuits. The above-described HUMUX 900 of FIG. 9 is an example of an HUMUX that can be used as the HUMUX's 2215. The HUMUX 900 acts as a four-to-one multiplexer that passes one of its four data inputs 905 to its one data output 910 based on the value of two of the four signals that it receives along its four select lines 915. The HUMUX 900 receives two user-design signals and two configuration data bits on its four select lines. The four-to-two multiplexer 920 of this HUMUX passes two of these four signals to the two select terminals 940 of the four-to-one multiplexer 925 of the HUMUX, which, in turn, identify one of the four input signals 905 for the multiplexer 925 to output.
[0126] Accordingly, the HUMUX's operation (1) is completely controlled by the configuration data bits when the two signals supplied to the select terminals 940 are the configuration data bits, (2) is completely controlled by the user-design signals when the two signals supplied to the select terminals 940 are users signals, and (3) is partially controlled by the user-design signals when the two signals supplied to the select terminals 940 include one user-design signal and one configuration data bit.
[0127] As mentioned above, an HUMUX acts as a routing multiplexer when its operation is completely controlled by configuration data; otherwise, the HUMUX serves as a logic circuit. Hence, when the HUMUX 900 is used as an HUMUX 2215, the HUMUX 2215/900 acts as a routing multiplexer when the two signals supplied to the select terminals 940 are the configuration data bits stored in the configuration data elements 945. Otherwise, when at least one of the two signals supplied to the select terminals 940 is a user-design signal, the HUMUX 900 acts as a logic circuit.
[0128] It is advantageous to use HUMUX's in a circuit arrangement of a configurable IC, because they can be used to augment the routing resources in some cycles, while augmenting the computational resources in other cycles. Having such dual-use devices not only increases the flexibility of the design of the configurable IC, but also reduces the size of the IC by requiring fewer overall number of logic and interconnect circuits.
[0129] 2. Hybrid Input-Select Multiplexer and Logic Circuit
[0130] An HUMUX can also be used as a hybrid input-select multiplexer and logic circuit in a circuit arrangement of a configurable IC. In a circuit arrangement, an input-select multiplexer is an interconnect circuit associated with a particular logic circuit in the arrangement. This interconnect circuit receives several input signals and passes a sub-set (e.g., one) of these input signals to its corresponding logic circuit. Accordingly, in some embodiments, an input-select multiplexer provides its output to only one logic circuit (i.e., has a fan out of 1), although this is not the case in all embodiments, as further discussed below.
[0131] One example of input-select multiplexers is presented in FIG. 23 . This figure illustrates an example of a circuit arrangement 2300 with numerous logic circuits 2305 and routing interconnect circuits 2310. The interconnect circuits 2310 are responsible for relaying signals between logic circuits and/or other interconnect circuits. The logic circuits, on the other hand, are responsible for performing computations on their respective input signals. In some embodiments, some or all the interconnect and/or logic are configurable circuits.
[0132] As shown in FIG. 23 , a logic circuit 2305a includes three input-select multiplexers 2315 and a core logic circuit 2320. The three input-select multiplexers 2315 receive input signals for the core logic circuit 2320. When operating as input-select multiplexers, these multiplexers pass a sub-set of the received input signals to the core logic circuit 2320, which performs a function on these input signals.
[0133] HUMUX's can be used for one or more of the input-select multiplexers 2315. Some embodiments have an HUMUX for only one of the input-select multiplexers 2315. An HUMUX acts as an input-select multiplexer (i.e., does not perform any computation and only serves to relay a signal to its associated logic circuit) when its operation is completely controlled by configuration data. For instance, when the HUMUX 900 of FIG. 9 is used as the HUMUX 2315a, the HUMUX 900 acts as an input-select multiplexer when the two signals supplied to the select terminals 940 are the configuration data bits stored in the configuration storage elements 945.
[0134] Otherwise, when the operation of the HUMUX is not completely controlled by configuration data, the HUMUX 2315a acts as a logic circuit. For instance, when the HUMUX 900 is used as an HUMUX 2315a, the HUMUX 900 acts as a logic circuit when at least one of the two signals supplied to the select terminals 940 is a user-design signal.
[0135] When such an HUMUX (i.e., an HUMUX at the input of a logic circuit) acts as a logic circuit, the HUMUX augments the computational abilities of the logic circuit. For instance, in the example illustrated in FIG. 23 , lets assume that the core logic circuit 2320 is a three-input LUT that receives three inputs from three multiplexers 2315. Lets further assume that the four-to-one HUMUX 900 is used as the HUMUX 2315a at the input of the core logic circuit 2320. This HUMUX receives two user-signal bits 2330 and 2335 that would select one of the four inputs 2340 for output to the three-input LUT 2320.
[0136] The combination of the logic circuit formed by the three-input LUT 2320 and the HUMUX 2315a (acting as a logic circuit) serves as a four-input logic circuit. It is expected that such a four-input logic circuit would be capable of implementing as many as 50 of the 220 most prevalent four-input functions that a configurable logic circuit can perform. Such added functionality comes relatively inexpensively, as it only comes at the expense of the slightly larger size of the HUMUX as the input select multiplexer 2315. Also, such added functionality not only increases the flexibility of the design of the configurable IC, but also might reduce the overall size of the IC by requiring fewer overall number of logic circuits.
[0137] In some embodiments, an input-select multiplexer can have a fan out of greater than 1. In these embodiments, the input-select multiplexer still connects directly to one logic circuit so that it can select an input of this logic circuit. However, in these embodiments, the input-select multiplexer also can provide its output to other circuits in the circuit arrangement.
[0138] 3. HUMUX's as Input-Select Multiplexers, Routing Muxes, and Logic Circuits
[0139] The IC's of some embodiments have circuit arrangements that use HUMUX's as both input-select multiplexers and routing multiplexers. FIG. 24 illustrates one such embodiment. Specifically, this figure illustrates a circuit arrangement 2400 that has numerous logic circuits 2405 and interconnect circuits 2407 arranged in numerous rows and columns. This circuit arrangement 2400 also includes several HUMUX's as routing interconnect circuits 2410 and several HUMUX's 2415a as input select multiplexers 2415 of some logic circuits 2405a.
[0140] It is advantageous to use in a configurable IC HUMUX's as both input select multiplexers and routing interconnect multiplexers. This is because such HUMUX's allow the configurable IC to form very complex logic circuit structures relatively easily by supering logic and HUMUX circuits. Some embodiments, however, use HUMUX's only for input select multiplexers.
V. HUMUX Useful for Decomposing all Functions
[0141] HUMUX's are hybrid interconnect/logic circuits. In other words, as mentioned above, HUMUX's can serve as logic and interconnect circuits in a configurable IC. This hybrid quality is especially advantageous since, as logic circuits, HUMUX's can be used to decompose and implement functions. In order to decompose and implement functions with HUMUX's, some embodiments define one input of some or all HUMUX's to be a permanently inverting input.
[0142] More specifically, some embodiments use Shannon and Davio decomposition to decompose functions. Some embodiments use the multiplexer function of the HUMUX to implement the “if-then-else” (ITE) expression needed for a Shannon decomposition. Through this ITE expression, these embodiments implement the AND function and its NPN equivalents, where NPN stands for negate input, permute input, and negate output.
[0143] FIGS. 25–30 illustrate how the multiplexer functionality of an HUMUX allows the HUMUX to implement the AND function and its NPN equivalents. Specifically, FIG. 25 illustrates a two-input multiplexer 2500 that receives variables “b” and “c” on its input lines and variable “a” on its select line. As shown in this figure, this multiplexer 2500 has an output (i.e., performs a function) that can be expressed as [(a·b)+(ā·c)].
[0144] The multiplexer 2500 can be used to generate the AND function and its NPN equivalents by routing constants to one of the multiplexer inputs and/or performing NPN operations. For instance, FIG. 34 illustrates that the multiplexer can perform the AND function by routing a binary 0 to its second input. Similarly, FIG. 27 illustrates that routing a binary 1 to the multiplexer's first input, allows the multiplexer to perform the OR function, which is one of the NPN equivalent functions of the AND function.
[0145] Like Shannon decomposition, Davio decomposition relies on the multiplexer functionality. However, unlike Shannon decomposition, Davio decomposition uses the XOR function to decompose a function. FIG. 28 illustrates a two-input multiplexer 2800 that implements an XOR function. As shown in this figure, the multiplexer 2800 has two inputs, one of which is permanently inverting. Both inputs of the multiplexer 2800 receives the same input signal “b”, while this multiplexer's select line receives the input signal “a”. Because of these input signals and the permanently inverting input, the multiplexer computes [(a· b )+(ā·b)], which is another representation of (a⊕b), i.e., of “a” XOR “b”. The multiplexer 2800 can also compute NPN equivalents' of the XOR function through NPN operations (i.e., through negating its inputs, permuting its inputs, and/or negating its output).
[0146] The multiplexers illustrated in FIGS. 25–28 can all be the core multiplexer of an HUMUX (e.g., a multiplexer like the four-to-one multiplexer 925 of the HUMUX 900 of FIG. 9 ). When the HUMUX acts as a logic circuit, this core multiplexer receives a user signal. For instance, FIG. 29 illustrates an example of an HUMUX 2900 that has a core multiplexer 2905 that operates like the multiplexer 2500 of FIGS. 25–27 as it receives the user signal “a” through the select multiplexer 2910.
[0147] FIG. 30 illustrates another example of an HUMUX 3000 that has a core multiplexer 3005 that operates like the multiplexer 2800 of FIG. 28 as it receives the user signal “a” through the select multiplexer 3010. Like the multiplexer 2800, the core multiplexer 3005 has one permanently inverting input. One of ordinary skill will realize that other embodiments might obviate the need for a permanently inverting input in the core multiplexer of an HUMUX by routing inverted inputs to such a multiplexer.
[0148] FIG. 31 illustrates a recursive process 3100 that a synthesizer can perform to decompose a function. This process uses a series of Shannon and/or Davio decompositions to decompose a function with more than two inputs into one or more functions with two inputs. The synthesizer can then implement each two-input function by the multiplexers illustrated in FIGS. 25–28 and their NPN equivalents.
[0149] As shown in FIG. 31 , the process 3100 initially receives (at 3105) a function with more than two inputs. It then determines (at 3110) whether it should use Shannon or Davio decomposition to remove one variable from the received function, in order to decompose the function. In some embodiments, the process makes this determination by using commonly known techniques, such as sifting on ordered Kronecker Decision Diagrams. For instance, some of these techniques determine whether the received function is highly dependent on a variable that the process can determine (at 3110) to remove. If so, the process determines (at 3110) to use the Shannon decomposition to remove the variable. Otherwise, the process determines (at 3110) to use the Davio decomposition to remove the variable.
[0150] When the process determines (at 3110) to use the Shannon decomposition to remove the variable, the process transitions to 3115. At 3115, the process performs Shannon decomposition on the received function. The decomposition operation results in a new expression of the received function that is dependent on the removed variable and two functions that are not dependent on the removed variable. Equation (A) illustrates an example of a Shannon decomposition for a five variable function F(a,b,c,d,e).
F(a,b,c,d,e)=[{a·F1(b,c,d,e)}+{ā·F0(b,c,d,e)}]. (A)
As expressed in Equation (A), the Shannon decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F1 and F0, which are individually AND'ed with the removed variable “a” and its complement, where the result of the AND operations are OR'ed together. After performing the Shannon decomposition at 3115, the process 3100 transitions to 3120, which will be described further below.
F(a,b,c,d,e)=[{a·F1(b,c,d,e)}+{ā·F0(b,c,d,e)}]. (A)
As expressed in Equation (A), the Shannon decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F1 and F0, which are individually AND'ed with the removed variable “a” and its complement, where the result of the AND operations are OR'ed together. After performing the Shannon decomposition at 3115, the process 3100 transitions to 3120, which will be described further below.
[0151] When the process determines (at 3110) to use the Davio decomposition to remove the variable, the process transitions to 3125. At 3125, the process performs Davio decomposition on the received function. This decomposition operation results in a new expression of the received function that is dependent on the removed variable and two functions that are not dependent on the removed variable:
[0152] There are two variations of Davio decomposition, a positive Davio decomposition and a negative Davio decomposition. Equation (B) illustrates an example of a positive Davio decomposition for the five variable function F(a,b,c,d,e).
F(a,b,c,d,e)=[{a·F1(b,c,d,e)}⊕{F2(b,c,d,e)}]. (B)
where
F2(b,c,d,e)=F1(b,c,d,e)⊕F0(b,c,d,e), (C)
where F0 and F1 are identical in Equations (A), (B), and (C). As expressed in Equation (B), the positive Davio decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F1 and F2, with the first function F1 AND'ed with the removed variable “a” and the result XOR'ed with the second function F2.
F(a,b,c,d,e)=[{a·F1(b,c,d,e)}⊕{F2(b,c,d,e)}]. (B)
where
F2(b,c,d,e)=F1(b,c,d,e)⊕F0(b,c,d,e), (C)
where F0 and F1 are identical in Equations (A), (B), and (C). As expressed in Equation (B), the positive Davio decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F1 and F2, with the first function F1 AND'ed with the removed variable “a” and the result XOR'ed with the second function F2.
[0153] Equation (D) illustrates an example of a negative Davio decomposition for the five variable function F(a,b,c,d,e).
F(a,b,c,d,e)=[{a·F0(b,c,d,e)}⊕{F2(b,c,d,e)}]. (D)
where F0 and F2 are identical in Equations (A), (B), (C), and (D). As expressed in Equation (D), the negative Davio decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F0 and F2, with the first function F0 AND'ed with the removed variable “a” and the result XOR'ed with the second function F2.
F(a,b,c,d,e)=[{a·F0(b,c,d,e)}⊕{F2(b,c,d,e)}]. (D)
where F0 and F2 are identical in Equations (A), (B), (C), and (D). As expressed in Equation (D), the negative Davio decomposition can decompose the five-variable function F(a,b,c,d,e) into two four-variable functions F0 and F2, with the first function F0 AND'ed with the removed variable “a” and the result XOR'ed with the second function F2.
[0154] After performing the Davio decomposition at 3125, the process 3100 transitions to 3120. At 3120, the process determines whether any of the functions that resulted from the decomposition (e.g., whether functions F0, F1, or F2) has more than two variables. When the process determines (at 3120) that none of the resulting functions have more than two variables, the process returns (at 3135) the two-input functions that the process identified itself or identified through its recursive calls, and then ends. On the other hand, if the process determines (at 3120) that one or more of the resulting functions has more than two variables, the process recursively calls itself (at 3130) once for each of these functions. Once the process has received the result of its recursive call, it returns (at 3135) the two-input functions that the process identified itself or identified through its recursive calls, and then ends.
[0155] When the original function has been broken down into a series of two-input functions, the original function can be implemented by a series of HUMUX's that perform two-input function AND and/or XOR operations and their NPN equivalents. When an HUMUX has more than two input lines and more than one select line, the HUMUX can be reduced into a two input HUMUX by setting all the select lines except one to default values, which, in turn, renders all the inputs of the HUMUX irrelevant except two of its inputs.
[0156] The process 3100 decomposes a function into a series of two-input functions. It is not necessary, however, for the decomposition operation to decompose the function into a series of two-input functions. The end result of other decomposition processes might include functions with three or more variables. These more complex functions, in turn, can be implemented by using other logic circuits (e.g., three or four input LUT's) or using HUMUX's with more than two inputs. Accordingly, the above-described process 3100 presents only one manner of decomposing a function. This process 3100 serves as an example of how a function with more than two variables can be decomposed through Shannon and/or Davio decomposition into a series of two input functions that can be implemented by HUMUX's.
[0157] Also, the discussion above focuses on using HUMUX's to decompose and implement complex functions. FUMUX's, however, can also be used to decompose and implement complex functions, by having some FUMUX's with at least one input that is a permanently inverting input or that receives an inverted version of another of its inputs. The advantage of using HUMUX's in an IC, however, is that HUMUX's can serve not only as logic circuits (that can decompose and implement complex functions) but can also server as interconnect circuits.
VI. Sub-Cycle Reconfigurable HUMUX
[0158] Reconfigurable IC's are one type of configurable IC's. Reconfigurable IC's are configurable IC's that can reconfigure during runtime. In other words, a reconfigurable IC is an IC that has reconfigurable logic circuits and/or reconfigurable interconnect circuits, where the reconfigurable logic and/or interconnect circuits are configurable logic and/or interconnect circuits that can “reconfigure” more than once at runtime. A configurable logic or interconnect circuit reconfigures when it receives a different set of configuration data. Some embodiments of the invention are implemented in reconfigurable IC's that are sub-cycle reconfigurable (i.e., can reconfigure circuits on a sub-cycle basis).
[0159] FIGS. 32–36 illustrate a more detailed example of an HUMUX 3200 of some embodiments of the invention. This example is a sub-cycle reconfigurable HUMUX that is implemented in complementary pass logic (CPL) for a sub-cycle reconfigurable IC. In a CPL implementation of a circuit, a complementary pair of signals represents each logic signal, where an empty circle at the input or output of a circuit denotes the complementary input or output of the circuit in the figures. In other words, the circuit receives true and complement sets of input signals and provides true and complement sets of output signals. A sub-cycle reconfigurable IC is an IC that has reconfigurable circuits that can receive configuration data sets on a sub-cycle basis and therefore can reconfigure on a sub-cycle basis. Examples of sub-cycle reconfigurable circuits are disclosed in U.S. patent application entitled “Configurable IC with Interconnect Circuits that also Perform Storage Operations”, which is filed concurrently with the present application, with the Ser. No. 11/081,859. This application is incorporated herein by reference.
[0160] As shown in FIG. 32 , the HUMUX 3200 is an eight-to-one HUMUX that is formed by four multiplexers 3205, 3210, 3215, and 3220. The inputs and outputs of these multiplexers are shown as thick lines to indicate that each of these lines represents a CPL true/complement pair of lines.
[0161] As shown in FIG. 32 , the multiplexer 3205 is an eight-to-one multiplexer that, on a sub-cycle basis, connects one of its input lines to its output line based on the values of the signals S2, S1, and S0′, which it receives along its three select lines. In response to three signals ST0, ST1, and CLK (which is not illustrated in FIG. 32 ), the multiplexer 3210 supplies two of the select signals S2 and S1 to the multiplexer 3205 on a sub-cycle basis. Specifically, based on the signals ST0 and ST1 that it receives on its select lines, the multiplexer 3210 connects one of its four three-bit input lines (each of which connects to a storage element 3225 that stores configuration data) to its three output lines. Hence, the three output lines of multiplexer 3210 provide three configuration select signals S2, S1, and S0. Two of these output lines connect to the third and second select lines of the multiplexer 3205, in order to provide the select signals S2 and S1.
[0162] The first output line of the multiplexer 3210 carries the first select signal S0. This output line connects to one of the two input lines of the multiplexer 3220. The other input line of the multiplexer 3220 receives a user signal. Through its two input lines, the multiplexer 3220 receives two inputs on a sub-cycle basis. Based on the signal that it receives on a sub-cycle basis on its select line from the multiplexer 3215, the multiplexer 3220 supplies one of its two inputs to its output line. This output line connects to the first select line of the multiplexer 3205 to provide the select signal S0′. Hence, the signal S0′ is a signal that in each sub-cycle might be either a user signal or configuration-driven select signal S0.
[0163] Which of these signals gets routed to the multiplexer 3205 as the select signal S0′ depends on the value of the configuration data output from the multiplexer 3215 on a sub-cycle basis. The multiplexer 3215 is a four-to-one multiplexer that (1) has its four inputs connected to four storage elements storing four configuration data bits, and (2) has one output that receives one of the four configuration data bits in each sub-cycle based on the signals ST0 and ST1 supplied to the select lines of the multiplexer 3215.
[0164] FIG. 33 illustrates a multiplexer 3300 that in some embodiments is used as the multiplexer 3205. As shown in FIG. 33 , the multiplexer 3300 includes one set of input buffers 3305, three sets of pass transistors 3310, 3315, and 3320, two pull-up PMOS transistors 3325 and 3330, and two output buffers 3335 and 3340. One subset of the input buffers 3305 receives eight input bits (0–7), while another subset of the input buffers 3305 receives the complement of the eight input bits (i.e., receives 0 – 7 ). These input buffers serve to buffer the first set 3310 of pass transistors.
[0165] The first set 3310 of pass transistors receive the third select bit S2 or the complement of this bit, while the second set 3315 of pass transistors receive the second select bit S1 or the complement of this bit. The third set 3320 of pass transistors receive the first select bit S0′ or its complement. The three select bits S2, S1, and S0 cause the pass transistors to pass one of the input bits and the complement of this input bit to two intermediate output nodes 3355 and 3360 of the circuit 3300. For instance, when the enable signal is low, and the select bits are 011, the pass transistors 3365a, 3370a, 3375a, and 3365b, 3370b, and 3375b turn on to pass the 6 and 6 input signals to the intermediate output nodes 3355 and 3360.
[0166] The pull-up PMOS transistors 3325 and 3330 are used to pull-up quickly the intermediate output nodes 3355 and 3360, and to regenerate the voltage levels at the nodes that have been degenerated by the NMOS threshold drops, when these nodes need to be at a high voltage. In other words, these pull-up transistors are used because the NMOS pass transistors are slower than PMOS transistors in pulling a node to a high voltage. Thus, for instance, when the 6th input signal is high, the enable signal is low, and the select bits are 011, the pass transistors 3365–3375 start to pull node 3355 high and to push node 3360 low. The low voltage on node 3360 turns on the pull-up transistor 3325, which, in turn, accelerates the pull-up of node 3355.
[0167] The output buffer inverters 3335 and 3340 are used to allow the circuit 3300 to drive a load. These buffers are formed by more than one inverter in some embodiments. The outputs of these buffers are the final output 3380 and 3385 of the multiplexer 3300. It should be noted that, in some embodiments, the output buffers 3335 and 3340 are followed by multiple inverters.
[0168] Although FIG. 32 conceptually illustrates the multiplexer 3220 as a separate multiplexer that is after the multiplexer 3210, some embodiments implement the multiplexer 3220 as part of a multiplexer structure that is used to define the multiplexer 3210. In some embodiments, the multiplexer 3210 of FIG. 32 is formed by three multiplexer structures. One structure is used to generate the third select signal S2, the other structure is used to generate the second select signal S1, and the last structure is used to generate the first select signal S0′.
[0169] FIG. 34 illustrates a CPL implementation of a two-tier multiplexer structure 3400 for generating the second signal S1 and its complement. The multiplexer structure for generating the third select signal S2 is identical to the structure 3400. In addition, an identical circuit can be used to implement the multiplexer 3215 of FIG. 32 . The multiplexer structure 3400 is a two-tiered multiplexer structure, where one tier of multiplexers is driven by the signals ST0 and ST1, while the other tier of multiplexers are driven by the clock signal CLK that operates at twice the rate of the signals ST0 and ST1, as further described below.
[0170] As illustrated in FIG. 34 , the select signal generation circuit 3400 can be divided into four sections, which are (1) storage cell section 3405, (2) first two-to-one multiplexer section 3410, (3) second two-to-one multiplexer section 3415, and (4) pull-up PMOS transistor sections 3420. The first section 3405 includes four storage cells 3425a–3425d that store four configuration bits for four sub-cycles. In other words, each storage cell provides a configuration bit 3430 and the complement of this bit 3435, where each such pair of bits provides the select bit signal S1 and its complement during a particular sub-cycle.
[0171] The second section includes two multiplexers 3440 and 3445 that are driven by two signals ST0 and ST1 that are offset by 90°, and the differential complement ST0 and ST1 of these signals. The third section is one two-to-one multiplexer 3415 that is driven by the clock signal CLK and its differential complement CLK .
[0172] FIG. 35 illustrates an example of the signals CLK, ST0, and ST1. Some embodiments use the multiplexer/storage circuit 3300 and the select-signal generator 3400 in a configurable IC that implements a design that has a primary clock rate of X MHZ (e.g., 200 MHZ) through a four sub-cycle implementation that effectively operates at 4×MHZ. In some of these embodiments, the two signals ST0 and ST1 would operate at X MHZ, while the clock signal CLK would operate at 2×MHZ.
[0173] The fourth section 3420 includes two pull-up PMOS transistors 3485 and 3490, which are used to quickly pull-up the output of the multiplexer 3415 that is high. The two complementary outputs of the multiplexer 3415 provide the select signal S1 and its complement. The S1 select signal and its complement drive the pass transistor set 3315 in FIG. 33 .
[0174] FIG. 34 illustrates one possible implementation 3450 of the multiplexer 3445 and the connections of this multiplexer 3445 and the storage cells 3425c and 3425d. As shown in this figure, the multiplexer 3445 can be implemented by four pass transistors, where two transistors 3455 and 3460 receive the true configuration bits 3430c and 3430d from the third and fourth storage cells 3425c and 3425d, while the other two transistors 3465 and 3470 receive the complement configuration bits 3435c and 3435d from the third and fourth storage cells. As further shown, transistors 3455 and 3465 are driven by signal ST1, while transistors 3460 and 3470 are driven by the complement ST1 of signal ST1. A similar implementation can be used for multiplexer 3440. However, the pass transistors 3455–3470 of the multiplexer 3440 would be driven by the signal ST0 and its complement ST0 .
[0175] FIG. 34 also illustrates one possible implementation of the two-to-one multiplexer 3415. This implementation is similar to the implementation 3450 of the multiplexer 3445. However, instead of the signal ST1, the pass transistors 3455–3470 of the multiplexer 3415 are driven by the CLK and CLK signals. Also, these transistors receive a different set of signals. Specifically, the transistors 3455 and 3465 of the multiplexer 3415 receive the true and complement outputs of the multiplexer 3440, while the transistors 3460 and 3470 of the multiplexer 3415 receive the true and complement outputs of the multiplexer 3445.
[0176] The transistors 3455 and 3465 of the multiplexer 3445 (1) output the true and complement configuration bits stored in the storage cells 3425c when the signal ST1 is high, and (2) output the true and complement configuration bits stored in the storage cells 3425d when the signal ST1 is low. Similarly, the transistors 3455 and 3465 of the multiplexer 3440 (1) output the true and complement configuration bits stored in the storage cells 3425a when the signal ST0 is high, and (2) output the true and complement configuration bits stored in the storage cells 3425b when the signal ST0 is low. Finally, the transistors 3455 and 3465 of the multiplexer 3415 (1) output the true and complement output bits of the multiplexer 3440 when the clock CLK is high, and (2) output the true and complement output bits of the multiplexer 3445 when the clock signal CLK is low.
[0177] Given the above-described operations of multiplexers 3440, 3445, and 3415, and given the 90° offset between signals ST0 and ST1 and the faster frequency of the clock signal CLK, FIG. 35 illustrates the value of the select signal S1 and its complement that the circuit 3400 generates during each half-cycle of the clock signal CLK. This clocking scheme hides all the timing of the selection of the configuration bits from the storage cells 3425 behind the two-to-one multiplexer 3415. For instance, while the multiplexer 3440 is switching between outputting the configuration bits stored in cell 3425a and the bits stored in cell 3425b, the clocking scheme directs the multiplexer 3415 to output the configuration bits previously selected by the multiplexer 3445 (i.e., the configuration bits stored in cell 3425c). Similarly, while the multiplexer 3445 is switching between outputting the configuration bits stored in cell 3425c and the bits stored in cell 3425d, the clocking scheme directs the multiplexer 3415 to output the configuration bits previously selected by the multiplexer 3440 (i.e., the configuration bits stored in cell 3425b).
[0178] When implementing a design that has a primary clock rate of X MHZ through a four sub-cycle implementation that effectively operates at 4×MHZ, this clocking scheme allows the configuration bits to be read from the storage cells at an effective rate of 4×MHZ without the need for a 4×MHZ clock. Some embodiments globally distribute the differential pair of CLK and CLK signals, while locally generating the differential signals ST0, STO , ST1, and ST1 . Examples of such distribution and generation are further described in U.S. patent application entitled “Configurable IC with Interconnect Circuits that also Perform Storage Operations”, which was incorporated above.
[0179] As mentioned above, FIG. 32 conceptually illustrates the multiplexer 3220 as a separate multiplexer that is after the multiplexer 3210. However, some embodiments implement the multiplexer 3220 in conjunction with the multiplexer structure of the multiplexer 3210 that is used to generate the signal S0 and its complement. FIG. 36 illustrates a CPL implementation of this combined multiplexer structure 3600 of some embodiments.
[0180] This multiplexer structure 3600 outputs the select signal S0′, which is provided to the first select line of the multiplexer 3205. The circuit 3600 illustrated in FIG. 36 can be divided into five sections, which are (1) storage cell section 3605, (2) first two-to-one multiplexer stage 3610, (3) a second two-to-one multiplexer stage 3620, (4) a third two-to-one multiplexer section 3625, and (5) a second pull-up transistor stage 3630.
[0181] The storage cell section 3605 is identical to the storage cell section 3405 of the circuit 3400 of FIG. 34 , with the exception that the storage cells in FIG. 36 store configuration bits for the first select signal S0, instead of storing configuration bits for the second select signal S1. In other words, each storage cell 3425 provides a configuration bit 3430 and the complement of this bit 3435, where each such pair of bits provides the select bit signal S0 and its complement during a particular sub-cycle.
[0182] The second section 3610 includes two multiplexers 3440 and 3445 that are identical to the two multiplexers 3440 and 3445 of the circuit 3400 of FIG. 34 . As in circuit 3400, the multiplexers 3440 and 3445 are for outputting the configuration bits from cells 3425a, 3425b, 3425c, and 3425d. The outputs of the second section 3610 can be tied to four pull-up PMOS transistors, which can quickly pull-up the outputs of the multiplexers 3440 and 3445 that are high. Some embodiments, on the other hand, might not include such pull-up PMOS transistors.
[0183] The third section 3620 includes two two-to-one multiplexers 3640 and 3645 that select respectively between the output of the multiplexer 3440 and the user signal US, and between the output of the multiplexer 3445 and the user signal US, based on the output UM and UM of the multiplexer 3215. As mentioned above, the output of the multiplexer 3215 specifies whether the select signal S0′ should be the user signal or the select signal S0 stored in the configuration data cell for the current sub-cycle.
[0184] The fourth section 3625 is one two-to-one multiplexer 3415 that is driven by a clock signal CLK, which operates at twice the frequency of the signals ST0 and ST1. The signals ST0, ST1, and CLK are illustrated in FIG. 35 , as described above. Also, as mentioned above, the use of the two-to-one multiplexer 3415 and the signals CLK, ST0, and ST1 and their differential complements, hides all the timing of the selection of the configuration bits from the storage cells 3425 behind the two-to-one multiplexer 3415.
[0185] The fifth section 3630 includes two pull-up transistors 3665 and 3670 that are used to pull-up quickly the output nodes 3655 and 3660 of the fourth section 3625, and to regenerate the voltage levels at the nodes that have been degenerated by the NMOS threshold drops, when these nodes need to be at a high voltage. The nodes 3655 and 3660 provide the first select signal S0′ and its complement for the first select line of the multiplexer 3205.
VII. Alternate Implementation of an HUMUX
[0186] In the HUMUX 3200, the first select line of the multiplexer 3205 can configurably receive either a configuration-derived select signal S0 or a user signal. Hence, the operation of the HUMUX 3200 can be based either on the configuration-derived select signal S0 or on the user signal. FIG. 37 illustrates another implementation of an HUMUX, which can operate based on a configuration-derived select signal S0, a first user signal US0, or a second user signal US1. Specifically, in the HUMUX 3700 of this figure, the first select line of the multiplexer 3205 can configurably receive either the configuration-derived select signal S0, the first user signal US0, or the second user signal US1.
[0187] The HUMUX 3700 is identical to the HUMUX 3200 except that the HUMUX 3700 also includes a multiplexer 3705. This multiplexer 3705 provides the HUMUX 3700 with the ability to supply the first select line of the multiplexer 3205 with one of two user signals US0 and US1, in addition to the select signal S0 output from the multiplexer 3210. In particular, the multiplexer 3705 receives the two user signals US0 and US1 as input signals. It also receives the select signal S0 along its select line. Based on the value of the select signal S0, the multiplexer 3705 routes one of the two user signals US0 and US1 to the multiplexer 3220, which also receives the select signal S0 as one of its input signals. Based on the value that the multiplexer 3220 receives on its select line, the multiplexer 3220 then outputs as select signal S0′ either the select signal S0 or the user signal that it receives. The select signal S0′ then drives the first select line of the multiplexer 3205 as described above.
[0188] FIG. 37 conceptually illustrates the multiplexer 3705, 3220, and 3210 as separate multiplexers. However, some embodiments implement the two multiplexers 3705 and 3220 in conjunction with the multiplexer structure of the multiplexer 3210 that is used to generate the signal S0 and its complement.
[0189] FIG. 38 illustrates a CPL implementation of this combined multiplexer structure 3600 of some embodiments. This combined multiplexer structure is identical to the combined multiplexer structure 3600 of FIG. 36 , except that the multiplexer structure 3600 also includes 2 two-to-one multiplexers 3805 and 3810.
[0190] The multiplexer 3805 selects between the user signals US0 and US1 based on the output of the multiplexer 3440, while the multiplexer 3810 selects between the user signals US0 and US1 based on the output of the multiplexer 3445. Each multiplexer includes two transistors (3815 and 3825, or 3835 and 3845) that receive the user signals US0 and its complement, and two transistors (3820 and 3830, or 3840 and 3850) that receive the user signals US1 and its complement. The transistors that receive the user signal US0 and its complement are driven by the true output of the multiplexer 3440 or 3445, while the transistors that receive the user signal US1 and its complement are driven by the complement output of the multiplexer 3440 or 3445.
[0191] The true and complement outputs of each two-to-one multiplexer 3805 and 3810 is supplied to the two-to-one multiplexers 3640 and 3645 of the third section 3620. These multiplexers then select respectively between the output of the multiplexer 3440 and the user signal (US0 or US1) supplied by the multiplexer 3805, and between the output of the multiplexer 3445 and the user signal (US0 or US1) supplied by the multiplexer 3810. The selection of these multiplexers 3640 and 3645 are based on the output UM and UM of the multiplexer 3215, which specifies whether the select signal S0′ should be the user signal or the select signal S0 stored in the configuration data cell for the current sub-cycle.
[0192] Several embodiments were described above by reference to examples of sub-cycle reconfigurable circuits that operate based on four different sets of configuration data. In some of these examples, a reconfigurable circuit receives its four different configuration data sets sequentially in an order that loops from the last configuration data set to the first configuration data set. Such a sequential reconfiguration scheme is referred to as a 4 “loopered” scheme.
[0193] Other embodiments, however, might be implemented as six or eight loopered sub-cycle reconfigurable circuits. In a six or eight loopered reconfigurable circuit, a reconfigurable circuit receives six or eight configuration data sets in an order that loops from the last configuration data set to the first configuration data set. Several examples of how make a four loopered circuit into a six and eight loopered circuit and the clocking scheme for such circuits are described in the above mentioned U.S. patent application entitled “Configurable IC with Interconnect Circuits that also Perform Storage Operations”, which is filed concurrently with the present application, with the Ser. No. 11/081,859.
VIII. Alternative Two Tiered Structure for Retrieving Data
[0194] Several circuits described above utilize a two-tiered structure for retrieving data (e.g., configuration data, etc.) on a sub-cycle basis. Examples of such circuits are the circuits illustrated in FIGS. 34 , 36, and 38. These circuits employ multiple storage elements 3425 that store multiple sets of data for multiple sub-cycles. They also include two tiers of multiplexers, where two two-to-one multiplexers (e.g., 3440 and 3445) form the first tier and one two-to-one multiplexer (e.g., 3415) forms the second tier. In some circuits, the two tiers of multiplexers have intervening circuits between them, such as AND'ing transistors or gates, etc. The second-tier multiplexer runs at the clock rate CLK, while the first-tier multiplexers runs at half that rate. From the storage elements, these multiplexers together output data at a sub-cycle rate that is twice the clock rate CLK.
[0195] Some embodiments that use this two-tiered structure, build the first tier of multiplexers into the sensing circuitry of the storage elements 3425. FIG. 39 illustrates an example of such an approach. Specifically, this figure illustrates four storage elements 3425a–3425d that are arranged in two columns 3950 and 3955. Each storage element stores one logical bit of data in a complementary format. This data might be configuration data, enable data, or any other data that needs to be provided to the reconfigurable IC on a sub-cycle basis.
[0196] Each of the two complementary outputs of each storage element 3425 connects to a pair of stacked NMOS transistors 3920 and 3925. One transistor 3925 in each stacked pair of NMOS transistors is part of a first tier multiplexer structure. Specifically, in the two-tiered circuit structure 3900 illustrated in FIG. 39 , the first tier multiplexer structure is formed by the eight transistors 3925, which receive the sub-cycle signals ST0, ST1, or the complements of these signals.
[0197] Through the sub-cycle signals ST0, ST1, ST0 , and ST1 , the multiplexer transistors 3925 selectively connect the NMOS transistors 3920 to the cross-coupled PMOS transistors 3905 and 3910. One pair of PMOS transistors 3905 and 3910 exists in each column and form part of the sensing amplifier for the storage elements in that column.
[0198] Specifically, when NMOS transistors 3920 associated with one storage element 3425 connect to the PMOS transistors 3905 and 3910, they form a level-converting sense amplifier. This amplifier then translates the signals stored in the storage element to the bit lines 3935 or 3940. The circuit 3900 provides the content of the storage elements through level-converting sense amplifiers, because, in some embodiments, the storage elements are storage cells that use a reduced voltage to store their data in order to conserve power. One such example of a reduced power storage cell is provided in United States Application entitled “Method and Apparatus for Reduced Power Cell,” filed concurrently with the present application, with the Ser. No. 11/081,874.
[0199] The bit lines 3935 and 3940 connect to the next stage in the circuit that they are used. Specifically, the bit lines 3935 and 3940 are provided to the two-to-one multiplexer 3415 in the circuit 3400, while they are provided to transistor stages 3640 and 3645 in the circuits 3600 and 3800, which, in turn, connect to the multiplexer 3415. As described above, the multiplexer 3415 is controlled through the clock signal CLK and its complement. Accordingly, when the clock signals CLK and CLK , and the sub-cycle signals ST0, ST1, ST0 , and ST1 , have the timing relationship illustrated in FIG. 35 , the first tier multiplexer (formed by the transistors 3925) and the second tier multiplexer 3415 operate to output data from the storage elements 3425 at a rate that is twice the rate of the clock signal CLK. This outputting is analogous to how the circuit 3400 outputs the S1 select signal on the sub-cycle basis that is illustrated in FIG. 35 .
[0200] By building the first multiplexer stage into the sense amplifier section of the storage elements, this circuit reduces signal path delay from the storage elements. Also, it operates with storage elements that have less power consumption. Furthermore, it reduces power consumption by using NMOS transistors 3920 that are not driven by full voltage levels, and sharing the PMOS transistors 3905 and 3910 that are necessary for level conversion between two storage elements.
[0201] The two-tiered structure of the circuit 3900 of FIG. 39 can be easily extended to six and eight loopered structures. For a six loopered structure, all that needs to be done is to stack another pair of storage elements above elements 3425c and 3425d, and to drive the transistors 3925 with two sets of three one-hot signals. Similarly, for an eight loopered structure, all that needs to be done is to stack two pairs of storage elements on top of elements 3425c and 3425d, and to drive the transistors 3925 with the two sets of four one-hot signals. These sets of one-hot signals are further described in the U.S. patent application entitled “Configurable IC with Interconnect Circuits that also Perform Storage Operations”, which is filed concurrently with the present application, with the Ser. No. 11/081,859.
IX. Configurable IC Architectures
[0202] Different embodiments of the invention are implemented in different configurable IC's with different architectures. FIGS. 40–45 illustrate the architecture of some embodiments of the invention. As shown in FIG. 40 , this architecture is formed by numerous configurable tiles 4005 that are arranged in an array with multiple rows and columns. In FIGS. 40–45 , each configurable tile includes a sub-cycle reconfigurable three-input LUT 4010, three sub-cycle reconfigurable input-select multiplexers 4015, 4020, and 4025, and two sub-cycle reconfigurable routing multiplexers 4030 and 4035. Other configurable tiles can include other types of circuits, such as memory arrays instead of logic circuits.
[0203] In FIGS. 40–45 , an input-select multiplexer is an interconnect circuit associated with the LUT 4010 that is in the same tile as the input select multiplexer. One such input select multiplexer receives several input signals for its associated LUT and passes one of these input signals to its associated LUT.
[0204] In FIGS. 40–45 , a routing multiplexer is an interconnect circuit that at a macro level connects other logic and/or interconnect circuits. In other words, unlike an input select multiplexer in these figures that only provides its output to a single logic circuit (i.e., that only has a fan out of 1), a routing multiplexer in some embodiments either provides its output to several logic and/or interconnect circuits (i.e., has a fan out greater than 1), or provides its output to other interconnect circuits.
[0205] FIGS. 41–45 illustrate the connection scheme used to connect the multiplexers of one tile with the LUT's and multiplexers of other tiles. This connection scheme is further described in U.S. Application entitled “Configurable IC with Routing Circuits with Offset Connections”, filed concurrently with this application with the Ser. No. 11/082,193. This application is incorporated herein by reference.
[0206] In the architecture illustrated in FIGS. 40–45 , each tile includes one three-input LUT, three input-select multiplexers, and two routing multiplexers. Other embodiments, however, might have a different number of LUT's in each tile, a different number of inputs for each LUT, a different number of input-select multiplexers, and/or a different number of routing multiplexers. For instance, some embodiments might employ an architecture that has in each tile: one three-input LUT, three input-select multiplexers, and eight routing multiplexers. Several such architectures are further described in the above-incorporated patent application.
[0207] In some embodiments, the examples illustrated in FIGS. 40–45 represent the actual physical architecture of a configurable IC. However, in other embodiments, the examples illustrated in FIGS. 40–45 topologically illustrate the architecture of a configurable IC (i.e., they show connections between circuits in the configurable IC, without specifying (1) a particular geometric layout for the wire segments that establish the connection, or even (2) a particular position of the circuits). In some embodiments, the position and orientation of the circuits in the actual physical architecture of a configurable IC is different than the position and orientation of the circuits in the topological architecture of the configurable IC. Accordingly, in these embodiments, the IC's physical architecture appears quite different than its topological architecture. For example, FIG. 46 provides one possible physical architecture of the configurable IC 4000 illustrated in FIG. 40 . This and other architectures are further described in the above-incorporated patent application.
X. Configurable IC and System
[0208] Some embodiments described above are implemented in configurable IC's that can compute configurable combinational digital logic functions on signals that are presented on the inputs of the configurable IC's. In some embodiments, such computations are state-less computations (i.e., do not depend on a previous state of a value).
[0209] Some embodiments described above are implemented in configurable IC's that can perform a continuous function. In these embodiments, the configurable IC can receive a continuous function at its input, and in response, provide a continuous output at one of its outputs.
[0210] FIG. 47 illustrates a portion of a configurable IC 4700 of some embodiments of the invention. As shown in this figure, this IC has a configurable circuit arrangement 4705 and I/O circuitry 4710. The configurable circuit arrangement 4705 can be any of the invention's configurable circuit arrangements that were described above. The I/O circuitry 4710 is responsible for routing data between the configurable circuits 4715 of the arrangement 4705 and circuits outside of the arrangement (i.e., circuits outside of the IC, or within the IC but outside of the arrangement 4705). As further described below, such data includes data that needs to be processed or passed along by the configurable circuits.
[0211] The data also includes in some embodiments configuration data that configure the circuits to perform particular operations. FIG. 48 illustrates a more detailed example of this. Specifically, this figure illustrates a configuration data pool 4805 for the configurable IC 4700. This pool includes N configuration data sets (CDS). As shown in FIG. 48 , the input/output circuitry 4710 of the configurable IC 4700 routes different configuration data sets to different configurable circuits of the IC 4700. For instance, FIG. 48 illustrates configurable circuit 4845 receiving configuration data sets 1, 3, and J through the I/O circuitry, while configurable circuit 4850 receives configuration data sets 3, K, and N-1 through the I/O circuitry. In some embodiments, the configuration data sets are stored within each configurable circuit. Also, in some embodiments, a configurable circuit can store multiple configuration data sets so that it can reconfigure quickly by changing to another configuration data set. In some embodiments, some configurable circuits store only one configuration data set, while other configurable circuits store multiple such data sets.
[0212] A configurable IC of the invention can also include circuits other than a configurable circuit arrangement and I/O circuitry. For instance, FIG. 49 illustrates a system on chip (“SoC”) implementation of a configurable IC 4900. This IC has a configurable block 4950, which includes a configurable circuit arrangement 4705 and I/O circuitry 4710 for this arrangement. It also includes a processor 4915 outside of the configurable circuit arrangement, a memory 4920, and a bus 4910, which conceptually represents all conductive paths between the processor 4915, memory 4920, and the configurable block 4950. As shown in FIG. 49 , the IC 4900 couples to a bus 4930, which communicatively couples the IC to other circuits, such as an off-chip memory 4925. Bus 4930 conceptually represents all conductive paths between the components of the IC 4900.
[0213] This processor 4915 can read and write instructions and/or data from an on-chip memory 4920 or an offchip memory 4925. The processor 4915 can also communicate with the configurable block 4950 through memory 4920 and/or 4925 through buses 4910 and/or 4930. Similarly, the configurable block can retrieve data from and supply data to memories 4920 and 4925 through buses 4910 and 4930.
[0214] Instead of, or in conjunction with, the system on chip (“SoC”) implementation for a configurable IC, some embodiments might employ a system in package (“SiP”) implementation for a configurable IC. FIG. 50 illustrates one such SiP 5000. As shown in this figure, SiP 5000 includes four IC's 5020, 5025, 5030, and 5035 that are stacked on top of each other on a substrate 5005. At least one of these IC's is a configurable IC that includes a configurable block, such as the configurable block 4950 of FIG. 49 . Other IC's might be other circuits, such as processors, memory, etc.
[0215] As shown in FIG. 50 , the IC communicatively connects to the substrate 5005 (e.g., through wire bondings 5060). These wire bondings allow the IC's 5020–5035 to communicate with each other without having to go outside of the SiP 5000. In some embodiments, the IC's 5020–5035 might be directly wire-bonded to each other in order to facilitate communication between these IC's. Instead of, or in conjunction with the wire bondings, some embodiments might use other mechanisms to communicatively couple the IC's 5020–5035 to each other.
[0216] As further shown in FIG. 50 , the SiP includes a ball grid array (“BGA”) 5010 and a set of vias 5015. The BGA 5010 is a set of solder balls that allows the SiP 5000 to be attached to a printed circuit board (“PCB”). Each via connects a solder ball in the BGA 5010 on the bottom of the substrate 5005, to a conductor on the top of the substrate 5005.
[0217] The conductors on the top of the substrate 5005 are electrically coupled to the IC's 5020–5035 through the wire bondings. Accordingly, the IC's 5020–5035 can send and receive signals to and from circuits outside of the SiP 5000 through the wire bondings, the conductors on the top of the substrate 5005, the set of vias 5015, and the BGA 5010. Instead of a BGA, other embodiments might employ other structures (e.g., a pin grid array) to connect a SiP to circuits outside of the SiP. As shown in FIG. 50 , a housing 5080 encapsulates the substrate 5005, the BGA 5010, the set of vias 5015, the IC's 5020–5035, the wire bondings to form the SiP 5000. This and other SiP structures are further described in United States patent Application entitled “Method for Manufacturing a Programmable System in Package”, filed concurrently herewith with the Ser. No. 11/081,820.
[0218] FIG. 51 conceptually illustrates a more detailed example of a computing system 5100 that has an IC 5105, which includes one of the invention's configurable circuit arrangements that were described above. The system 5100 can be a stand-alone computing or communication device, or it can be part of another electronic device. As shown in FIG. 51 , the system 5100 not only includes the IC 5105, but also includes a bus 5110, a system memory 5115, a read-only memory 5120, a storage device 5125, input devices 5130, output devices 5135, and communication interface 5140.
[0219] The bus 5110 collectively represents all system, peripheral, and chipset interconnects (including bus and non-bus interconnect structures) that communicatively connect the numerous internal devices of the system 5100. For instance, the bus 5110 communicatively connects the IC 5110 with the read-only memory 5120, the system memory 5115, and the permanent storage device 5125.
[0220] From these various memory units, the IC 5105 receives data for processing and configuration data for configuring the IC's configurable logic and/or interconnect circuits. When the IC 5105 has a processor, the IC also retrieves from the various memory units instructions to execute. The read-only-memory (ROM) 5120 stores static data and instructions that are needed by the IC 5110 and other modules of the system 5100. The storage device 5125, on the other hand, is read-and-write memory device. This device is a non-volatile memory unit that stores instruction and/or data even when the system 5100 is off. Like the storage device 5125, the system memory 5115 is a read-and-write memory device. However, unlike storage device 5125, the system memory is a volatile read-and-write memory, such as a random access memory. The system memory stores some of the instructions and/or data that the IC needs at runtime.
[0221] The bus 5110 also connects to the input and output devices 5130 and 5135. The input devices enable the user to enter information into the system 5100. The input devices 5130 can include touch-sensitive screens, keys, buttons, keyboards, cursor-controllers, microphone, etc. The output devices 5135 display the output of the system 5100.
[0222] Finally, as shown in FIG. 51 , bus 5110 also couples system 5100 to other devices through a communication interface 5140. Examples of the communication interface include network adapters that connect to a network of computers, or wired or wireless transceivers for communicating with other devices. One of ordinary skill in the art would appreciate that any other system configuration may also be used in conjunction with the invention, and these system configurations might have fewer or additional components.
[0223] While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
Claims
We claim:
1. A configurable integrated circuit (“IC”) comprising:
a) a plurality of configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data; and
b) a plurality of hybrid circuits, each particular hybrid circuit having:
1) a set of inputs,
2) a set of outputs for selectively connecting to the set of inputs, and
3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner, wherein at least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.
2. The configurable IC of claim 1, wherein a particular hybrid circuit performs an interconnect operation when the particular hybrid circuit receives only configuration data on the set of select lines of the particular hybrid circuit.
3. The configurable IC of claim 2, wherein the particular hybrid circuit performs a computation when the particular hybrid circuit receives at least one non-configuration data on the set of select lines of the particular hybrid circuit.
4. The configurable IC of claim 2 further comprising non-configurable circuits, wherein a hybrid circuit receives configuration data through a non-configurable circuit.
5. The configurable IC of claim 1, wherein the hybrid circuits are hybrid multiplexers that are controllable either by configuration data for configuring the configurable IC or by signals generated by the IC.
6. The configurable IC of claim 5, wherein the configuration data is supplied from the outside of the IC.
7. The configurable IC of claim 6, wherein the configuration data is data generated by a compiler to configure the configurable IC to implement a particular design.
8. A configurable integrated circuit (“IC”) comprising:
a) a plurality of configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data; and
b) a plurality of hybrid configurable multiplexers, each particular hybrid configurable multiplexer having a select terminal set for receiving configuration data and for receiving output data from the configurable circuits.
9. The configurable IC of claim 8, wherein each particular hybrid configurable multiplexer further has an input terminal set and an output terminal set, wherein each hybrid configurable multiplexer is for connecting the input and output terminal sets in a particular manner based on the data that the multiplexer receives along the multiplexer's select terminal set.
10. The configurable IC of claim 8, wherein each of a plurality of hybrid configurable multiplexer comprises:
a) a core multiplexer having the select terminal set, and
b) an interconnect circuit for receiving the configuration data and for receiving the output data from the configurable circuits and for supplying part of the received data to the select terminal set.
11. The configurable IC of claim 10, wherein the supplied part of the received data includes only configuration data or only output data.
12. The configurable IC of claim 10, wherein the supplied part of the received data includes configuration and output data.
13. The configurable IC of claim 10, wherein the configuration data received by the interconnect circuit is a first set of configuration data, wherein the interconnect circuit receives at least a second set of configuration data for directing the interconnect circuit to supply part of the received data to the select terminal set.
14. The configurable IC of claim 8, wherein the plurality of configurable circuits include a plurality of configurable logic circuits and a plurality of configurable interconnect circuits.
15. The configurable IC of claim 14, wherein the output data is the output data of the logic circuits.
16. The configurable IC of claim 15, wherein at least a plurality of output data is supplied to a plurality of hybrid configurable multiplexers through a plurality of configurable interconnect circuits.
17. The configurable IC of claim 8, wherein the configurable circuits include at least fifty configurable circuits.
18. The configurable IC of claim 17, wherein the configurable circuits are arranged in an array.
19. The configurable IC of claim 18, wherein the hybrid configurable multiplexers are part of the array.
20. The configurable IC of claim 18, wherein the hybrid configurable multiplexers are interspersed in the array.
21. A electronic device comprising:
a) a memory for storing data;
b) a configurable integrated circuit (“IC”) for receiving data from the memory, the IC comprising:
a) a plurality of configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data; and
b) a plurality of hybrid circuits, each particular hybrid circuit having:
1) a set of inputs,
2) a set of outputs for selectively connecting to the set of inputs, and
3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner, wherein at least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.
22. The electronic device of claim 21, wherein a particular hybrid circuit performs an interconnect operation when the particular hybrid circuit receives only configuration data on the set of select lines of the particular hybrid circuit.
23. The electronic device of claim 22, wherein the particular hybrid circuit performs a computation when the particular hybrid circuit receives at least one non-configuration data on the set of select lines of the particular hybrid circuit.
24. The electronic device of claim 22 further comprising non-configurable circuits, wherein a hybrid circuit receives configuration data through a non-configurable circuit.
25. The electronic device of claim 21, wherein the hybrid circuits are hybrid multiplexers that are controllable either by configuration data for configuring the configurable IC or by signals generated by the IC.
26. The electronic device of claim 25, wherein the configuration data is supplied from the outside of the IC.
27. The electronic device of claim 26, wherein the configuration data is data generated by a compiler to configure the configurable IC to implement a particular design.
Patent Citations (95)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4873459(A) | 1989-10-01 | El Gamal et al. | Applicant |
| US5245575(A) | 1993-09-01 | Sasaki et al. | Applicant |
| US5349250(A) | 1994-09-01 | New | Applicant |
| US5357153(A) | 1994-10-01 | Chiang et al. | Applicant |
| US5365125(A) | 1994-11-01 | Goetting et al. | Applicant |
| US5369622(A) | 1994-11-01 | McLaury | Applicant |
| US5521835(A) | 1996-05-01 | Trimberger | Applicant |
| US5532958(A) | 1996-07-01 | Jiang et al. | Applicant |
| US5552721(A) | 1996-09-01 | Gould | Applicant |
| US5610829(A) | 1997-03-01 | Trimberger | Applicant |
| US5631578(A) | 1997-05-01 | Clinton et al. | Applicant |
| US5646544(A) | 1997-07-01 | Iadanza | Applicant |
| US5659484(A) | 1997-08-01 | Bennett et al. | Applicant |
| US5692147(A) | 1997-11-01 | Larsen et al. | Applicant |
| US5694057(A) | 1997-12-01 | Gould | Applicant |
| US5719889(A) | 1998-02-01 | Iadanza | Applicant |
| US5732246(A) | 1998-03-01 | Gould et al. | Applicant |
| US5737235(A) | 1998-04-01 | Kean et al. | Applicant |
| US5745422(A) | 1998-04-01 | Iadanza | Applicant |
| US5745734(A) | 1998-04-01 | Craft et al. | Applicant |
| US5764954(A) | 1998-06-01 | Fuller et al. | Applicant |
| US5768178(A) | 1998-06-01 | McLaury | Applicant |
| US5777360(A) | 1998-07-01 | Rostoker et al. | Applicant |
| US5802003(A) | 1998-09-01 | Iadanza et al. | Applicant |
| US5815726(A) | 1998-09-01 | Cliff | Applicant |
| US5889411(A) | 1999-03-01 | Chaudhary | Applicant |
| US5914616(A) | 1999-06-01 | Young et al. | Applicant |
| US5914906(A) | 1999-06-01 | Iadanza et al. | Applicant |
| US5973340(A) | 1999-10-01 | Mohsen | Examiner |
| US5982655(A) | 1999-11-01 | Doyle | Applicant |
| US6002991(A) | 1999-12-01 | Conn, Jr. | Applicant |
| US6023421(A) | 2000-02-01 | Clinton et al. | Applicant |
| US6038192(A) | 2000-03-01 | Clinton et al. | Applicant |
| US6044031(A) | 2000-03-01 | Iadanza et al. | Applicant |
| US6054873(A) | 2000-04-01 | Laramie | Applicant |
| US6069490(A) | 2000-05-01 | Ochotta et al. | Applicant |
| US6075745(A) | 2000-06-01 | Gould et al. | Applicant |
| US6086631(A) | 2000-07-01 | Chaudhary et al. | Applicant |
| US6091263(A) | 2000-07-01 | New et al. | Applicant |
| US6091645(A) | 2000-07-01 | Iadanza | Applicant |
| US6107821(A) | 2000-08-01 | Kelem et al. | Applicant |
| US6110223(A) | 2000-08-01 | Southgate et al. | Applicant |
| US6118707(A) | 2000-09-01 | Gould et al. | Applicant |
| US6130854(A) | 2000-10-01 | Gould et al. | Applicant |
| US6134154(A) | 2000-10-01 | Iwaki et al. | Applicant |
| US6140839(A) | 2000-10-01 | Kaviani et al. | Applicant |
| US6150838(A) | 2000-11-01 | Wittig et al. | Applicant |
| US6173379(B1) | 2001-01-01 | Poplingher et al. | Applicant |
| US6175247(B1) | 2001-01-01 | Scalera et al. | Applicant |
| US6184707(B1) | 2001-02-01 | Norman et al. | Applicant |
| US6205076(B1) | 2001-03-01 | Wakayama | Applicant |
| US6233191(B1) | 2001-05-01 | Gould et al. | Applicant |
| US6292019(B1) | 2001-09-01 | New et al. | Applicant |
| US6346824(B1) | 2002-02-01 | New | Applicant |
| US6381732(B1) | 2002-04-01 | Burnham et al. | Applicant |
| US6487709(B1) | 2002-11-01 | Keller et al. | Applicant |
| US6490707(B1) | 2002-12-01 | Baxter | Applicant |
| US6496918(B1) | 2002-12-01 | Dehon et al. | Applicant |
| US6515509(B1) | 2003-02-01 | Baxter | Applicant |
| US6526559(B2) | 2003-02-01 | Schiefele et al. | Applicant |
| US6529040(B1) | 2003-03-01 | Carberry et al. | Applicant |
| US6545501(B1) | 2003-04-01 | Bailis et al. | Applicant |
| US6593771(B2) | 2003-07-01 | Bailis et al. | Applicant |
| US6601227(B1) | 2003-07-01 | Trimberger | Applicant |
| US6603330(B1) | 2003-08-01 | Snyder | Applicant |
| US6629308(B1) | 2003-09-01 | Baxter | Applicant |
| US6636070(B1) | 2003-10-01 | Altaf | Applicant |
| US6642744(B2) | 2003-11-01 | Or-Bach et al. | Applicant |
| US6667635(B1) | 2003-12-01 | Pi et al. | Applicant |
| US6668361(B2) | 2003-12-01 | Bailis et al. | Applicant |
| US6675309(B1) | 2004-01-01 | Baxter | Applicant |
| US6714041(B1) | 2004-03-01 | Darling et al. | Applicant |
| US6806730(B2) | 2004-10-01 | Bailis et al. | Applicant |
| US6809979(B1) | 2004-10-01 | Tang | Applicant |
| US6831479(B2) | 2004-12-01 | Lo | Applicant |
| US6838902(B1) | 2005-01-01 | Elftmann et al. | Applicant |
| US6870395(B2) | 2005-03-01 | Schadt et al. | Examiner |
| US6924663(B2) | 2005-08-01 | Masui et al. | Applicant |
| US6937535(B2) | 2005-08-01 | Ahn et al. | Applicant |
| US6956399(B1) | 2005-10-01 | Bauer | Applicant |
| US6991947(B1) | 2006-01-01 | Gheewala | Examiner |
| US6992505(B1) | 2006-01-01 | Zhou | Applicant |
| US6998872(B1) | 2006-02-01 | Chirania et al. | Applicant |
| US7028281(B1) | 2006-04-01 | Agrawal et al. | Applicant |
| US2002/0008541(A1) | 2002-01-01 | Young et al. | Applicant |
| US2002/0125910(A1) | 2002-09-01 | New et al. | Examiner |
| US2002/0125914(A1) | 2002-09-01 | Kim | Applicant |
| US2002/0163357(A1) | 2002-11-01 | Ting | Applicant |
| US2003/0042931(A1) | 2003-03-01 | Ting | Applicant |
| US2003/0080777(A1) | 2003-05-01 | Baxter | Applicant |
| US2003/0110430(A1) | 2003-06-01 | Bailis et al. | Applicant |
| US2004/0010767(A1) | 2004-01-01 | Agrawal et al. | Applicant |
| US2004/0103265(A1) | 2004-05-01 | Smith | Applicant |
| US2004/0196066(A1) | 2004-10-01 | Ting | Applicant |
| US2004/0233758(A1) | 2004-11-01 | Kim et al. | Applicant |
Non-Patent Literature (125)
- U.S. Appl. No. 11/081,883, filed Mar. 15, 2005, Hutchings.Applicant
- U.S. Appl. No. 11/269,141, filed Nov. 7, 2005, Caldwell.Applicant
- U.S. Appl. No. 11/082,199, filed Mar. 15, 2005, Hutchings.Applicant
- U.S. Appl. No. 11/081,850, filed Mar. 15, 2005, Hutchings.Applicant
- U.S. Appl. No. 11/269,168, filed Nov. 7, 2005, Redgrave.Applicant
- “§3 Programmable Logic Devices,” Digital System Design, 2001, pp. 3.1-3.28, Month N/A.Applicant
- “Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.Applicant
- “The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, pp. 1-10, Unpublished Date N/A.Applicant
- “The Xilinx Virtex Series FPGA,” Jan. 22, 2001, sildes 1-22.Applicant
- “Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,” ISCA '04, 2004, ACM, Munchen, Oberbayern, Germany, Month N/A.Applicant
- Agrawal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Gain-Month N/A Architecture and Wide-gating Functions,” FPGA 99, 1999, pp. 17-26, ACM, Monterey, CA, USA, Month N/A.Applicant
- Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,” FPGA 2000, 2000, ACM, Monterey, CA, USA, Month N/A.Applicant
- Altera Corp., “6. DSP Blocks in Stratix II Devices,” SII52006-1.0, Feb. 2004, pp. 1-32.Applicant
- Altera, “Stratix II DSP Performance,” White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.Applicant
- Backus, J., “Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs,” Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM.Applicant
- Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set,” A Technology Application Whitepaper, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, Month N/A.Applicant
- Brand, D., et al., “Minimization of AND-EXOR Expressions Using Rewrite Rules,” IEEE Transactions on Computers, May 1993, pp. 568-576, IEEE.Applicant
- Butts, M., “Future Directions of Dynamically Reprogrammable Systems,” IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 487-494, IEEE, Month N/A.Applicant
- Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, pp. 1-74, Synopsys, Inc, Month N/A.Applicant
- Caspi, E., et al., “A Streaming Multi-Threaded Model,” MSP-3, Dec. 2, 2001, pp. 1-23.Applicant
- Caspi, E., et al., “Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.Applicant
- Ciemat, J.V., et al., “Annealing Placement by Thermodynamic Combinatorial Optimization,” ACM Transactions on Design Automation of Electronic Systems, Jul. 2004, pp. 310-332, vol. 9, No. 3, ACM, New York, NY.Applicant
- Compton, K., et al., “An Introduction to Reconfigurable Computing,” , Unpublished Date N/A.Applicant
- Compton, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,” ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY.Applicant
- Cong, J., et al., “A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA,” pp. 1-22, Unpublished Date N/A.Applicant
- Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,” ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1. No. 2, ACM, Inc.Applicant
- Coudert, O., “Chapter 13: Doing Two-Level Logic Minimization 100 Times Faster,” pp. 112-121, Unpublished Date N/A.Applicant
- Damiani, M., et al., “The Disjunctive Decomposition of Logic Functions,” pp. 1-5, Unpublished Date N/A.Applicant
- Davare, A., et al., “The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications,” DAC '04, Jun. 7-11, 2004, ACM, San Diego, California, USA.Applicant
- Dehon, A., Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization). pp. 1-10. (Applicants believe that this article also appears in Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134.).Applicant
- Dehon, A., “DPGA Utilization and Application.” , Unpublished Date N/A.Applicant
- Dehon, A., “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,” Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54.Applicant
- Dehon, A., “Reconfigurable Architectures for General-Purpose Computing,” A.I. Technical Report No. 1586, Oct. 1996, pp. i-353.Applicant
- Dehon, A., “The Density Advantage of Configurable Computing,” Apr. 2000, pp. 41-49, IEEE.Applicant
- Dehon, A., “Transit Note #121: Notes on Programmable Interconnect,” M.I.T. Transit Project, Feb. 1995, pp. 1-13.Applicant
- Dehon, A., et al., “Design Patterns for Reconfigurable Computing,” Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 2004.Applicant
- Dehon, A., et al., “DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century,” FCCM '94-IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 10-13, 1994.Applicant
- Dehon, A., et al., “Reconfigurable Computing: What, Why, and Implications for Design Automation,” DAC 99. New Orleans, Louisiana, 1999. ACM, Month N/A.Applicant
- Enzler, R., et al., “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” pp. 151-160, Unpublished Date N/A.Applicant
- Gayasen, A., et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement,” FPGA '04, Feb. 22-24, 2004, pp. 51-58, ACM, Monterey, California, USA.Applicant
- George, V., “Low Energy Field-Programmable Gate Array,” A Dissertation Submitted in Partial Satisfaction of the Requirements for the Degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley, Fall 2000, pp. 1-190, Month N/A.Applicant
- Giraud-Carrier, C., “A Reconfigurable Data Flow Machine for Implementing Functional Programming Languages.” , Unpublished Date N/A.Applicant
- Goldstein, S.C., et al., “PipeRench: A Coprocessor for Streaming Multimedia Acceleration.” , Unpublished Date N/A.Applicant
- Goldstein, S.C., et al., “PipeRench: A Reconfigurable Architecture and Compiler,” 2000, pp. 70-77, IEEE, Unpublished Date N/A.Applicant
- Hauck, S., et al., “Montage: An FPGA for Synchronous and Asynchronous Circuits,” pp. 1-4, (Applicants believe that this article also appears in Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, 1993, pp. 44-51, Springer-Verlag, Berlin.), Month N/A.Applicant
- Hauck, S., et al., “Totem: Domain-Specific Reconfigurable Logic,” pp. 1-25, Unpublished Date N/A.Applicant
- Heidari, G., et al., “Introducing a Paradigm Shift in the Design and Implementation of Wireless Devices,” A Wireless Devices Whitepaper, Apr. 28, 2004 but ® 2003, pp. 1-10, QuickSilver Technology, Inc., San Jose, California.Applicant
- Hofstee, H.P., “Cell Broadband Engine, Architecture from 20,000 Feet,” Aug. 24, 2005, pp. 1-6.Applicant
- Huang, A.S., “Tao: An Architecturally Balanced Reconfigurable Hardware Processor,” Submitted to the Dept. of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degrees of Bachelor of Science in Electrical Science and Engineering and Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, May 23, 1997, pp. 1-86, 107-109.Applicant
- IBM, “Cell Broadband Engine Architecture, Version 1.0,” Aug. 8, 2005, pp. 1-319, USA.Applicant
- IBM, “SPU Application Binary Interface Specification, Version 1.3,” CBEA JSRE Series, Aug. 1, 2005, pp. iv-26, USA.Applicant
- IBM, “SPU Assembly Language Specification, Version 1.2,” CBEA JSRE Series, Aug. 1, 2005, pp. iii-22, USA.Applicant
- IBM, “SPU C/C++ Language Extensions, Version 2.0” CBEA JSRE Series, Aug. 1, 2005, pp. iv-84, USA.Applicant
- IBM, “Synergistic Processor Unit Instruction Set Architecture, Version 1.0,” Aug. 1, 2005, pp. 1-257, USA.Applicant
- Kaviani, A., et al., “Computational Field Programmable Architecture.” , Unpublished Date N/A.Applicant
- Kaviani, A., et al., “Hybrid FPGA Architecture,” Department of Electrical and Computer Engineering, University of Toronto, Canada, Unpublished Date N/A.Applicant
- Keutzer, K., “Overview of “configurable” architectures,” slides 1-29, Unpublished Date N/A.Applicant
- Kocan, F., et al., “Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays,” FPL 2004, 2004, pp. 289-300, Springer-Verlag, Berlin Heidelberg, Month N/A.Applicant
- Kravets, V.N, et al., “Generalized Symmetries in Boolean Functions” Unpublished Date N/A.Applicant
- Lehn, D.I., et al., “Evaluation of Rapid Context Switching on a CSRC Device,” Unpublished Date N/A.Applicant
- Lemieux, G., et al., “Generating Highly-Routable Sparse Crossbars for PLDs,” FPGA 2000, 2000, ACM, Monterey, California, USA, Month N/A.Applicant
- Lemieux, G., et al., “Using Sparse Crossbars within LUT Clusters,” FPGA 2001, Feb. 11-13, 2001, ACM, Monterey, CA.Applicant
- Lertora, F., et al., “Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-On-Chip,” , Unpublished Date N/A.Applicant
- Lewis, D., et al., “The Stratix-II Routing and Logic Architecture,” pp. 1-22, Unpublished Date N/A.Applicant
- Ling, A., “The Search for the Optimal FPGA Logic Block,” ACM, Month N/A.Applicant
- M2000, “FlexEOS Embedded FPGA Cores,” 2003, M2000, Month N/A.Applicant
- Markovskiy, Y., et al., “Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine,” FPGA '02, Feb. 24-26, 2002, ACM, Monterey, California, USA.Applicant
- Master, P., “The Next Big Leap in Reconfigurable Systems,” A Technology Vision Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-8, QuickSilver Technology, Inc., San Jose, California.Applicant
- MathStar, Inc., “MathStar FPOA Architecture: A New Approach to High Throughput, Scalable, and Reprogrammable Design,” Technology Overview, 2003, MathStar, Inc., Month N/A.Applicant
- Mirsky, E., et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1996.Applicant
- Mirsky, E., et al., “MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distribution and Deployable Resources,” Hot Chips Symposium 1997, 1997, Month N/A.Applicant
- Mishchenko, A., “Fast Computation of Symmetries in Boolean Functions” , Unpublished Date N/A.Applicant
- Mishchenko, A., et al., “A New Enhanced Constructive Decomposition and Mapping Algorithm,” DAC 2003, Jun. 2-6, 2003, pp. 143-148, ACM, Anaheim, California, USA.Applicant
- Morris, K., “Lattice Launches XP: Non-Volatility at the Forefront of FPGA,” FPGA and Programmable Logic Journal, 2005, pp. 1-5, Techfocus Media, Inc, Month N/A.Applicant
- Morris, K., “Rationalizing Reconfigurability: The Importance of Being Programmable,” FPGA and Structured ASIC Journal, Sep. 27, 2005.Applicant
- Nelson, B.E., “Reconfigurable Computing: An Introduction and Overview,” Sep. 23, 1998, pp. 1-43.Applicant
- Niedzielski, D., “An Overview of Reconfigurable Computing,” Unpublished Date N/A.Applicant
- Ochotta, E.S., et al., “A Novel Predictable Segmented FPGA Routing Architecture,” FPGA 98, 1998, pp. 3-11, ACM, Monterey, CA, USA, Month N/A.Applicant
- Ohkura, J., et al., “Dataflow in the Adaptive Computing Machine (ACM),” A Technology Application Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-9, QuickSilver Technology, Inc., San Jose, California.Applicant
- Parhami, B., “Part IV: Low-Diameter Architectures,” ECE 254B: Advanced Computer Architecture: Parallel Processing, UCSB, Spring 2005, slides 1-93, Behrooz Parhami, Santa Barbara, CA., Month N/A.Applicant
- Pedram, M., “IEEE Circuits and Systems Society Distinguished Lecturer Program.” Unpublished Date N/A.Applicant
- Perissakis, S., et al., “Embedded DRAM for a Reconfigurable Array,” Unpublished Date N/A.Applicant
- Perissakis, S., et al., “Embedded DRAM for a Reconfigurable Array,” Proceedings of the 1999 Symposium on VLSI Circuits, Jun. 1999.Applicant
- Perkowski, M.A., “A New Representation of Strongly Unspecified Switching Functions and its Application to Multi-Level AND/OR/EXOR Synthesis.” Unpublished Date N/A.Applicant
- Plunkett, B., “In Search of the SDR Holy Grail,” A Technology Application Whitepaper, Apr. 28, 2004 but © 2003, pp. 1-7, QuickSilver Technology, Inc., San Jose, California.Applicant
- Plunkett, B., et al., “Adapt2400 ACM Architecture Overview,” A Technology Whitepaper, 2004, pp. 1-9, QuickSilver Technology, Inc., Month N/A.Applicant
- QuickLogic Corp., “Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM,” Eclipse II Family Data Sheet, 2005, pp. 1-92, QuickLogic Corporation, US, Month N/A.Applicant
- QuickSilver Technology, Inc., “Adapt2000 ACM System Platform,” Apr. 2004, pp. 1-39, QuickSilver Technology, Inc., San Jose, California.Applicant
- QuickSilver Technology, Inc., “InSpire SDK Tool Set,” Product Brief, 2004, QuickSilver Technology, Inc., San Jose, California, Month N/A.Applicant
- QuickSilver Technology, Inc., “QS2412 Adaptive Computing Machine,” Product Brief, 2004, QuickSilver Technology, Inc., San Jose, California, Month N/A.Applicant
- Rahman, A., et al., “Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2003, pp. 44-54, vol. 11, No. 1, IEEE.Applicant
- Rose, J., “Hard vs. Soft: The Central Question of Pre-Fabricated Silicon,” pp. 1-4, Unpublished Date N/A.Applicant
- Sambhwani, S., et al., “Implementing W-CDMA Transceiver Structure on an Adaptive Computing Platform,” A Technology Application Whitepaper, Apr. 28, 2004, but © 2003, pp. 1-12, QuickSilver Technology, Inc., San Jose, California.Applicant
- Scalera, S.M., et al., “A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing.” , Unpublished Date N/A.Applicant
- Schaumont,P., et al., “A Quick Safari Through the Reconfiguration Jungle,” , Unpublished Date N/A.Applicant
- Schmit, H., “Extra-Dimensional Island-Style FPGAs,” 2003, Month N/A.Applicant
- Schmit, H., “Extra-dimensional Island-Style FPGAs,” pp. 1-10, Unpublished Date N/A.Applicant
- Schmit, H., “Incremental Reconfiguration for Pipelined Applications.” , Unpublished Date N/A.Applicant
- Schmit, H., et al., “FPGA Switch Block Layout and Evaluation,” FPGA ′02, Feb. 24-26, 2002, ACM, Monterey, California, USA.Applicant
- Schmit, H., et al., “PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology,” , Unpublished Date N/A.Applicant
- Schmit, H., et al., “Queue Machines: Hardware Compilation in Hardware.” , Unpublished Date N/A.Applicant
- Scholl, C., “Multi-output Functional Decomposition with Exploitation of Don't Cares,” , May 19-21, 1997.Applicant
- Sharma, A., et al., “Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques” , Unpublished Date N/A.Applicant
- Singh, A., et al., “Interconnect Pipelining in a Throughput-Intensive FPGA Architecture,” FPGA 2001, Feb. 11-13, 2001, pp. 153-160, ACM, Monterey, CA, USA.Applicant
- Singh, A., et al., “PITIA: An FPGA for Throughput-Intensive Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jun. 2003, pp. 354-363, vol. 11, No. 3, IEEE.Applicant
- Slade, A.L., et al., “Reconfigurable Computing Application Frameworks,” , Unpublished Date N/A.Applicant
- Snider, G., “Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware,” FPGA′02, Feb. 24-26, 2002, pp. 177-186, ACM, Monterey, California, USA.Applicant
- Stankovic, R.S., et al., “Remarks on the Number of Logic Networks with Same Complexity Derived from Spectral Transform Decision Diagrams,” pp. 1-8, Unpublished Date N/A.Applicant
- Tau, E., et al., “A First Generation DPGA Implementation,” Proceedings of the Third Canadian Workshop on Field-Programmable Devices, May 1995, pp. 138-143.Applicant
- Tau, E., et al., “Transit Note #114: A First Generation DPGA Implementation,” M.I.T. Transit Project, Jan. 1995, pp. 1-8.Applicant
- Teifel, J., et al., “Highly Pipelined Asynchronous FPGAs” FPGA ′04, ACM, Monterey, California, USA, Month N/A.Applicant
- Tessier, R., et al., “Balancing Logic Utilization and Area Efficiency in FPGAs,” , Unpublished Date N/A.Applicant
- Tom, M., et al., “Clustering of Large Designs for Channel-Width Constrained FPGAs,” Univsersity of British Columbia, Department of Electrical and Computer Engineering, slides 1-39, Vancouver, BC, Canada, Unpublished Date N/A.Applicant
- Tom, M., et al., “Logic Block Clustering of Large Designs for Channel-Width Constrained FPGAs,” DAC 2005, Jun. 13-17, 2005, pp. 726-731, ACM, Anaheim, California, USA.Applicant
- Trimberger, S., “Effects of FPGA Architecture of FPGA Routing,” 32nd ACM/IEEE Design Automation Conference, 1995, ACM, Month N/A.Applicant
- Tsu, W., et al., “HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array,” pp. 1-10. (Applicants believe that this also appears in Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 69-78).Applicant
- Wawrzynek, J., “EECS150-Digital Design: Lecture 5—Field Programmable Gate Arrays (FPGAs),” Feb. 4, 2002, pp. 1-4, slides 1-20, multiple slides per page.Applicant
- Weaver, N., et al., “The SFRA: A Corner-Turn FPGA Architecture,” FPGA ′04, Feb. 22-24, 2004, ACM, Monterey, California, USA.Applicant
- Wegener, I., “The Complexity of Boolean Functions,” Wiley-Teubner Series in Computer Science, 1987, John Wiley & Sons Ltd. and B.G. Teubner, Stuttgart, New York, Month N/A.Applicant
- Wilton, S.J.E., “Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays,” FPGA 97, 1997, pp. 10-16, ACM, Monterey, California, USA, Month N/A.Applicant
- Xilinx, Inc., “Virtex-4 Family Overview,” Advance Product Specification, Sep. 10, 2004, pp. 21-30, v1.1, Xilinx, Inc.Applicant
- Zilic, Z. et al., “Using BDDs to Design ULMs for FPGAs,” pp. 1-10, Unpublished Date N/A.Applicant
- Zuchowski, P.S., “A Hybrid ASIC and FPGA Architecture,” 2002, IEEE, Month N/A.Applicant
- U.S. Appl. No. 11/081,883, filed Mar. 15, 2005, Hutchings et al., Non-Final Rejection mailed Nov. 03, 2006 of Related Application.Applicant
- U.S. Appl. No. 11/082,199, filed Mar. 15, 2005, Hutchings et al., Non-Final Rejection mailed Nov. 21, 2006 of Related Application.Applicant