Method and apparatus for real time identification and correction of pixel defects for image sensor arrays

[0001] The present invention relates to a method and apparatus that enables real time identification and correction of defective pixels in an image sensor array in a digital imaging environment.

[0002] When an image is exposed onto an image sensor, each pixel records the amount of light that it “sees” as an intensity level between a dark signal wherein no light reaches that pixel, to a full white signal representing the maximum amount of light detectable by that pixel. The image thus captured by the image sensor is processed as a grayscale image.

[0003] To detect the colors of the image exposed onto the image sensor, the pixels of the image sensor are covered with a respective color filter that absorbs light wavelengths for all colors except the color of the filter. An exemplary method for acquiring color information from an image sensor is to place a color filter array over the pixels of an image sensor. The most common example of such a color filter array is a Bayer mosaic filter, shown in FIG. 1. The Bayer mosaic filter has a checkerboard like configuration and is composed of alternating rows of red and green, and blue and green filters. The red and blue filters are offset from each other so that no two green filters share an edge between adjacent rows and columns. To obtain complete color information for each pixel, it is necessary to interpolate the intensity of the colors based on the level of those colors at the surrounding pixels.

[0004] Although a typical image sensor has at least hundreds of thousands of pixels collecting color filtered information for an image, each pixel is important, not just for the signal value recorded in that pixel, but also for use in interpolating color information for other surrounding pixels. Thus, when a pixel is defective, its effects can be compounded to affect a significant portion of the image.

[0005] Due to a number of inherent variabilities in the manufacturing processes of image sensors such as charge-coupled devices (CCDs) or complementary metal oxide semiconductors (CMOSs), some of the pixels of the imaging array in each sensor are either always dark (often due to a short in the circuitry) or always too bright (often due to abnormally high leakage current). In most cases these defects can be corrected by substituting the defective signal values with the values of adjacent pixels during image processing. However, this substitution requires knowledge of the defective pixel locations.

[0006] In most cameras presently known, the locations of the defective pixels are determined during an off-line testing procedure during the production stage and are stored in a non-volatile memory in the camera. The main drawback of this conventional approach is that the number of defects that can be corrected is limited by the size of the non-volatile memory dedicated to this purpose. Another drawback of the conventional approach is that it requires a separate manufacturing step for the identification and storage of the defect locations.

[0007] Other existing camera modules perform correction of defective pixels by comparing each pixel with adjacent pixels, such as those on either side of the pixel in the same line, and performing substitution using threshold-based criteria. Such defect correction methods using comparisons based on predetermined thresholds tend to diminish resolution, as fine details such as thin vertical lines are “eliminated” from the image.

[0008] In view of the present state of the art, the process for correcting defective pixels would thus be greatly improved if the dedicated non-volatile memory currently required for storing the pre-calibrated defect map could be eliminated, and if the correction of defective pixels could be made without using threshold criteria.

[0009] The present invention addresses the disadvantages of the prior art by providing a method and apparatus which enables real time correction of image data for an arbitrary number of both dark and bright defective pixels in an image sensor array without the need for a separate production-stage calibration to account for the defective pixels or a non-volatile medium to store a pre-calibrated defect map. The method and apparatus of the invention also enables the identification of defective pixel data without relying on a specific definition of a defect and without requiring the use of any specified thresholds against which potential defects are compared. The method and apparatus of the invention also enables correction of defective pixel data in an image regardless of the image contents and the correction of defective pixel data in an image without appreciably affecting the resolution of the image, and the correction of defective pixel data in an image, while also reducing peak-to-peak noise variations in the image.

[0010] An image processing system and method of the invention compares the signal of each pixel in an image with the respective signals of at least eight surrounding pixels of the same color in the filter array. If the signal of a given pixel is larger than the respective signals of all eight surrounding pixels of the same color, then the value of that central pixel signal is substituted with the maximum signal value among the surrounding eight pixels of the same color. Similarly, if the signal of a given pixel is smaller than the respective signals of all eight surrounding pixels of the same color, then the value of that central pixel signal is substituted with the minimum signal value among the surrounding eight pixels of the same color.

[0011] The present invention also includes the capability to detect a cluster of defective pixels in an image sensor pixel array, which may be performed after the defective pixel data identification and correction operation, and in which the absolute value of the difference between the signal values of two adjacent pixels of the same color type are compared against a threshold value, wherein a cluster defect is present if the absolute value of any difference between two signal values is determined to be greater than the threshold. Preferably, this operation is only performed during testing at the factory, but may also be configured to execute automatically in the imaging apparatus after completion of the defective pixel data identification and correction operation.

[0012] Other features and advantages of the present invention will become apparent from the following description of the invention with reference to the accompanying drawings.

[0019] In the method aspect of the present invention, the signal value of each pixel in an image obtained by an image sensor is compared with the values for at least eight closest surrounding pixels having the same color filter located adjacent to or near the pixel being tested. An example of this method will be described for an image obtained by an image sensor having a Bayer mosaic filter array. As illustrated in FIG. 2, the signal value of the central pixel, P₀, is compared with the signal values for each of the eight closest surrounding pixels of the same color. In this example, these eight closest surrounding pixels are located along the same row (P₄, P₅), column (P₂, P₇), and diagonally (P₁, P₃, P₆, and P₈) from the pixel being tested (P₀), each spaced one pixel away from P₀ in the relevant direction.

[0020] If the signal of P₀ is larger than the respective signals of all eight surrounding pixels P₁ through P₈, then the signal value for P₀ is substituted with the maximum signal value from among the signal values for pixels P₁ through P₈. Similarly, if the signal of P₀ is smaller than the respective signals of all eight surrounding pixels P₁ through P₈, then the signal value P₀ is substituted with the minimum signal value from among the signal values for pixels P₁ through P₈.

[0021] Stated in mathematical terms, if P₀=max(P₁, . . . , P₈) or if P₀=min(P₁, . . . , P₈), then P₀=P₁, where P_i satisfies |P₀−P_k|=min|P₀−P_k|, wherein k=1, . . . , 8.

[0022] Since this method requires image data from two rows and columns on each side of a pixel being tested (one on each side for monochromatic filtered arrays), the method as described above does not account for checking and correcting, if necessary, the pixels in the two outermost rows and columns of the image obtained by the image sensor because pixels in these locations do not have two rows and columns of surrounding pixels. One solution is to provide a slightly larger pixel array in the image sensor than will be displayed or outputted from the apparatus in which the image processing system of the present invention is incorporated. Hence, the image data contained in these pixels from the one or two rows and columns at the edges of the image sensor pixel array are not checked for defects and are not displayed, but are used for checking the function of the relevant interior pixels according to the present invention.

[0023] The method described above is preferably performed automatically in an imaging apparatus, such as a camera, for each image captured by the imaging sensor provided in the apparatus, and is effective for 8-bit, 10-bit, 12- bit, etc. bit depths of pixel color for each color channel in the color filter array over an image sensor. The operation of these method is transparent to an end user of the apparatus, so that the user will only see the corrected image without the initial defects. Moreover, it is noted that if the imaging apparatus has passed the quality control tests performed at the factory and is being operated by the end user, the cluster defect detection method should always produce a negative result, indicating that no cluster defects are present.

[0024] However, this method is only suited to correct isolated defects occurring no more frequently than once per 3×3 or 5×5 or other subarray size as needed for testing each pixel. In the case of a cluster of defective pixels, the method fails and the device should be rejected at the production testing stage. A cluster is defined as two or more defects of the same color located next to each other. In a Bayer mosaic filtered array, a cluster would include two or more defective pixels of the same color which are spaced apart from each other by an intervening pixel of another color.

[0025] Optionally, the capability to perform the following operation may be provided in the imaging apparatus to assist in determining the presence of clusters after the performance of the defect correction method described above. In this optional operation, the image sensor is uniformly illuminated following the defective pixel identification and correction process, and as illustrated in FIG. 3, the absolute value of the difference between the values of two adjacent pixels of a same color P₀₊ and P₆₊ is compared against a threshold value. Differences above the threshold level will be observed only if uncorrectable cluster defects are present in the image sensor. Stated mathematically, a cluster of defective pixels is present if, after execution of the defect correction process,
|P₀₊−P₆₊|>T_th.

[0026] The cluster defect detection operation may be set to be performed automatically in the imaging apparatus after a completion of the defective pixel data identification and correction operation, but is preferably controlled, such as by a switch in the system hardware, to be operated at the production stage after a complete test execution of the defective pixel data identification and correction operation. When performed at the factory during a production stage or quality control procedure, a successful execution of this cluster detection test serves as a verification that the image sensor is free of cluster defects. However, if the test yields a result which is greater than the threshold value, a cluster of defective pixels is present, and the image sensor should be discarded.

[0027] The defective pixel data identification and correction method described above is implemented in a system which includes a memory structure capable of holding image information obtained from at least a 3×3 subset, and preferably a 5×5 subset, of a pixel array of an image sensor. For example, if the architecture of the image sensor provides a monochrome image, such as by having a monochrome filter over the entire pixel array or by producing an image in grayscale, only three lines of storage are necessary for the memory frame because each pixel is immediately surrounded by eight pixels of the same color as the one to be tested. If, on the other hand, the image sensor architecture includes a multi-colored filter array, such as a Bayer mosaic filter in which rows of red and green alternating pixels are alternatingly arranged with rows of blue and green alternating pixels as shown in FIG. 1, then the memory structure of the present invention is capable of holding at least five lines of image information. Alternatively, the memory structure may be of any other size necessary for accommodating any other type of image sensor filter arrangement. As a further alternative, the buffer memory may be a full frame buffering memory capable of holding pixel information for an entire image.

[0028] FIG. 4 is a diagram illustrating a preferred embodiment of a processing unit 100 incorporated in an image processor and which implements the correction method described above. In the preferred embodiment, the processing unit 100 includes six rows of shift registers 108 for receiving image data, a delay circuit 112 for transferring a most recent line of image data into one of the rows of shift registers 108 in column synchrony with input of data into other rows of shift registers, five banks of random access memory (RAM) 102 for storing an equal number of previously read in lines of image data, a read/write address generator 110 for controlling the flow of data into and out of the RAM banks 102, a input multiplexer 104 for inputting the image data into the appropriate RAM as determined by the read/write address generator 110, an output multiplexer 106 for outputting the image data from the RAM banks 102 into the appropriate row of shift registers 108 as determined by the read/write address generator 110, a defect correction circuit for performing defective pixel data identification and correction as described above, and optionally, a second two-dimensional interpolation image processing operation circuit 116 for producing red, green and blue output signals.

[0029] For a monochrome image sensor array, since only three rows of shift registers are needed to perform the defective pixel data identification and correction operation fewer RAM banks 102 and rows of shift registers 108, e.g., three RAM banks 102 and four rows of shift registers 108, are needed.

[0030] In the preferred embodiment, each memory bank is a dual-ported SRAM (static RAM) allowing simultaneous read/write access. However, other types of random access memories may be used, such as any of the many different subspecies of DRAMs, including, for example, fast page mode DRAM (FPM DRAM), extended data out DRAM (EDO DRAM), burst EDO DRAM, synchronous DRAM (SDRAM), double data rate DRAM (DDR DRAM), Rambus DRAM (RDRAM), etc.

[0031] Additionally, the delay circuit can be embodied as a RAM or any other device, or may be substituted with any other mechanism through which an incoming line of image data can be transferred directly into the shift registers in column synchrony with the image data entering the shift registers through the RAM banks 102. In the preferred embodiment, however the delay circuit 112 is simply provided as a delay register which delays the input of a new line of image data into an upper row of the shift registers 108 to maintain pixel column synchronism with pixel data input into the remaining rows of shift registers from the RAM banks 102.

[0032] The six sets of shift registers 108 provide simultaneous access to six lines of image data (fewer lines are needed for a monochrome image array) to enable both pixel defect correction and another two-dimensional interpolation processing function to be performed while sharing the same shift register hardware as used for defect correction. As mentioned above, the most recent line of image data is transferred to the top row of shift registers shown in FIG. 4, while the next most recent line of image data is inputted into the second row of shift registers from one of the RAM banks 102, and so forth, with the sixth most recent line of image data being inputted into the last row of shift registers shown in FIG. 4.

[0033] The particular RAM bank from which data is being transferred into each respective row of shift registers 108 is determined by a pointer in address generator 110 which operates a switch provided in the output multiplexer 106. The data in the RAM banks 102 are read out to the shift registers 108 pixel by pixel in FIFO order. Also, the image data from the delay register 112 is synchronized with the output from the memory banks 102 so that the image data being fed into one set of the shift registers by the delay register is from the same column of the image array as the pixel information being read out of the five banks of memory into the other five sets of shift registers.

[0034] The architecture described above allows for defect correction to be performed at the pixel clock rate prior to further processing steps in the image processor. The identification and correction of defective pixels occurs in the shift registers by the defect correction circuit 114, and is sequentially performed for pixel data in the third row of shift registers using the data read into the first five rows of shift registers. Specifically, pixel data from each line of image data in the memory banks 102 is parsed into the appropriate shift registers in synchronization with the pixel clock rate, and detection and correction of data for defective pixels is performed for the central pixel 122 shown in the defect correction circuit 114 of the shift register array. Once the pixel data currently in the center of the defect correction circuit 114 has been checked and corrected, if necessary, the data in the shift register array shifts to the right, with new pixel data being read into the left most column of shift registers from the respective RAM banks 102 and the delay register 112, to check the pixel data for the next pixel to the left in the same line.

[0035] This process is repeated until all of the pixel data in the relevant image line, i.e. the third row of shift registers, has been checked and corrected, if necessary. As each line of image data is being moved through the shift registers, the RAM bank containing the oldest line of image data which is moving through the sixth row of shift registers is also being loaded with the new line of pixel data entering the first row of shift registers under control of the input multiplexer 104 and address generator 110. Thus, the old image data is overwritten as it is being read out to the sixth line of shift registers via the output multiplexer 106. As a result, the RAM bank reading out the oldest line of image data is loaded with the newest line of image data currently entering the first row of shift register. This RAM will thus contain pixel image data to be loaded into the second row of shift registers for correcting the next line of image data.

[0036] Upon reaching the end of the image data lines, the read/write address generator 110 updates the output multiplexer 106 so that the RAM bank 102 containing the line of image data just checked by the defect correction circuit 114 is rerouted to read out its contents to the fourth row of shift registers shown in FIG. 4, while the RAM bank 102 previously outputting its image data to the fourth row of shift registers is now configured to output to the fifth row of shift registers. Similarly, the RAM bank previously configured to read out its line of image data into the fifth row of shift registers is now rerouted to read out to the sixth row of shift registers, and the RAM bank previously outputting to the second row of shift registers is now configured to output to the third row of shift registers. As explained above, the image data previously read into the first row of shift registers is now resident in the RAM bank 102 previously holding the oldest line of image data and is now routed to the second row of shift registers.

[0037] The image data in the RAM banks 102 is then read out to the shift registers from left to right, as in the previous iteration, to begin the process anew for the line of pixel data now present in the third row of shift registers 108. Also, the next incoming line of image data is read into the first row of shift registers in column synchrony with the image data entering the second through sixth rows of shift registers from the RAM banks 102. In the preferred embodiment, column synchronization of the image data being read into the first row of shift registers relative to the remaining rows is achieved by a delay register 112 as shown in FIG. 4, although this may be achieved using any of the other means mentioned above.

[0038] Since the data buffered in the memory banks is used repeatedly, i.e. once for each line in the five RAM banks (three for monochrome image arrays), it is necessary to update the memory contents once a defect is found and corrected. The corrected value is written into the central shift register 122 in defect correction circuit 114 and also back into the appropriate pixel location in the RAM bank 102, via the input multiplexer 104, corresponding to the row of shift registers on which defect correction is being made (120 in FIG. 4).

[0039] Once the defect correction is performed, the same set of shift-registers can be used (with a delay of one line and one pixel) to perform other two-dimensional image processing operations such as color interpolation, indicated, for example, as circuit 116 in FIG. 4. Other image processing operations such as sharpness filtering, white balancing, etc. can also be performed by circuit 116 to produce a red, green and blue output signal 124.

[0040] For a monochrome image sensor array, the operation of the processing unit 100 is the same as described above, except that fewer RAM banks and rows of shift registers are provided, and the output signal 124 from the two-dimensional image processing circuit 116 will only have the color of the monochrome image.

[0041] An example of an imaging apparatus 200 incorporating the features of the present invention discussed above is shown in FIG. 5, and includes a lens system 202 for directing light from an object to be imaged to the image sensing unit 204 including an image sensor; an analog-to-digital converter 206 for converting the image signals received at the image sensing unit 204 into digital signals; the image/color processing unit 208 for performing image correction processes including the data correction for defective pixels as described above and also for performing other processes such as color interpolation, sharpness filtering, white balancing, etc.; an output format conversion/compression unit 210 for converting the image data into an appropriate file format for being outputted or displayed to the user; and a controller 212 for controlling the operations of the entire imaging apparatus 200.

[0042] The image sensor in the image sensing unit 204 is preferably constructed as an integrated circuit which includes pixels made of a photosensitive material such as silicon. The image sensor may be formed as a CMOS sensor and combined with a processor, such as a CPU, digital signal processor or microprocessor, in a single integrated circuit. Alternatively, the image sensor in the image sensing unit 204 may be constructed as a charge coupled device (CCD).

[0043] Without being limiting, such an imaging apparatus 200 could be part of a computer system, camera system, scanner, machine vision system, vehicle navigation system, video telephone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.

[0044] An exemplary processor system 400 to which the imaging apparatus 200 may be connected is shown in FIG. 6. The processing system 400, such as a computer system, for example, generally comprises a central processing unit (CPU) 444 that communicates with an input/output (I/O) device 446 over a bus 452. The imaging apparatus 200 communicates with the system over bus 452 or a ported connection. The processor system 400 also includes random access memory (RAM) 448, and, in the case of a computer system, may include peripheral devices such as a floppy disk drive 454 and a compact disk (CD) ROM drive 456 which also communicate with CPU 444 over the bus 452.

[0045] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.