Methods of forming atomic layers of a material on a substrate by sequentially introducing precursors of the material

[0001] This application claims the benefit of Korean Patent Application No. 2002-44318, filed Jul. 26, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.

[0002] The present invention relates to methods of forming thin films, and more particularly to methods of forming thin films through Atomic Layer Deposition (ALD).

[0003] Integrated circuit devices, such as logic and memory devices, are widely used in consumer and commercial applications. As the integration density of integrated circuit devices continues to increase, it may be desirable to form ultra thin layers, such as ultra thin dielectric layers, on a semiconductor substrate. These dielectric layers may be used, for example, as a gate dielectric layer of an insulated gate field effect transistor, also referred to as a MOSFET, and/or as a capacitor dielectric for an integrated circuit capacitor. As is well known to those having skill in the art, a field effect transistor includes spaced apart source and drain regions, a gate dielectric therebetween, and a gate electrode on the gate dielectric. Moreover, as is well known to those having skill in the art, an integrated circuit capacitor includes a first or lower electrode, a second or upper electrode, and a dielectric therebetween. Integrated circuit capacitors are widely used in integrated circuit memory devices such as Dynamic Random Access Memory (DRAM) devices.

[0004] Silicon dioxide is widely used as a dielectric layer for integrated circuit field effect transistors and/or capacitors. However, as the integration density of integrated circuits continues to increase, dielectric materials having a higher dielectric constant than silicon, such as Ta₂O₅, Y₂O₃, HfO₂, ZrO₂, Nb₂O₅, BaTiO₃, SrTiO₃ and/or other materials have been used.

[0005] Tantalum oxide (Ta₂O₅) has been widely used as the dielectric layer of a capacitor due to the potentially high thermal stability thereof. However, the tantalum oxide may react with a lower electrode of the capacitor. In particular, when polysilicon is used for the lower electrode, oxygen atoms contained in the tantalum oxide layer may react with silicon atoms contained in the polysilicon layer during a formation process of the tantalum oxide layer and/or during heat treatment after forming the tantalum oxide layer, so that the polysilicon layer may be oxidized. As a result, leakage current of the capacitor may increase.

[0006] Lower electrodes of a capacitor also have been made using metals, such as platinum (Pt), ruthenium (Ru), iridium (Ir) and the like, or of conductive metal nitride, such as titanium nitride (TiN). However, the metal or the conductive metal nitride used for the lower electrode may cause other problems.

[0007] In particular, the tantalum oxide layer may be continuously deposited in an atmosphere of oxygen by using a tantalum source and an oxygen source as an oxidizing agent. Examples of the tantalum source include TaCl₅, Ta(OCH₃)₅, Ta(OC₂H₅)₅, Ta(OC₃H₇)₅, Ta(OC₄H₉)₅, Ta(OC₂H₅) (OC₃H₇)₄, or Ta(OC₂H₅)₄(DMAE) (Ta(OC₂H₅)₄ [OC₂H₅N(CH₃)₂], tetraethoxy tantalum dimethylaminoethoxide (hereinafter referred to as “TAT-DAME”), etc. Examples of the oxygen source include O₂, H₂O, H₂O₂, N₂O, alcohols including OH group, etc. The combination of the tantalum source and the oxidizing agent may oxidize the lower electrode, which may decrease the quality of the tantalum oxide layer.

[0008] For instance, when ruthenium is used for the lower electrode of the capacitor, a surface of the ruthenium may be oxidized by the oxygen source to form a ruthenium oxide (RuO₂) layer. The ruthenium oxide layer may prevent the tantalum oxide from being uniformly deposited on the lower electrode of the capacitor. When the tantalum oxide layer is used for a dielectric layer of a cylinder-shaped or a concave capacitor having a high aspect ratio, the above-mentioned low deposition quality may be particularly observed. That is, the tantalum oxide may not be deposited upon the ruthenium electrode at a lower opening portion of the cylindrical capacitor and may be excessively deposited on an upper opening portion of the cylindrical capacitor. Therefore, the step coverage of the tantalum oxide may be poor.

[0009] The dielectric layer of the capacitor can be deposited through a conventional Chemical Vapor Deposition (CVD) process, a low-pressure CVD (LPCVD) process, a plasma enhanced CVD (PECVD) process, and/or a sputtering process. See, for example, U.S. Pat. No. 6,339,009 and Japanese Published Application 2001-85423. However, the above and other CVD processes may be carried out at a relatively high temperature, which may have an adverse thermal effect on a device. Furthermore, a thin film layer deposited through the CVD process may have a non-uniform thickness and/or poor step coverage.

[0010] Embodiments of the invention provide methods of forming a thin film layer through an atomic layer deposition process. A first reacting material including a tantalum precursor and a titanium precursor is introduced to a substrate so that a portion of the first reacting material is chemisorbed onto the substrate. A second reacting material including oxygen is introduced to the substrate so that a portion of the second reacting material is chemisorbed onto the substrate to form a solid material thereon. In some embodiments, a thin film layer having a high dielectric constant, good step coverage, and/or a superior leakage current characteristic is thereby formed on the substrate.

[0011] Other methods of forming an atomic layer of a material on the substrate, according to other embodiments of the present invention, introduce a first precursor of the material to a substrate, such that a first portion of the first precursor is chemisorbed onto the substrate, and a second portion of the first precursor is not chemisorbed onto the substrate. At least some of the second portion of the first precursor that is not chemisorbed onto the substrate is then purged. A second precursor of the material is introduced to the substrate, such that a first portion of the second precursor is chemisorbed onto the substrate and reacts with the first portion of the first precursor that is chemisorbed onto the substrate to form the atomic layer of the material, and a second portion of the second precursor is not chemisorbed onto the substrate. At least some of the second portion of the second precursor that is not chemisorbed onto the substrate is purged.

[0012] Still other embodiments of the present invention form an atomic layer of a material on a substrate by introducing a first precursor of the material to the substrate in a purge gas flow. Then, the introducing the first precursor is discontinued while maintaining the purge gas flow. Then, a second precursor of the material is introduced to the substrate in the purge gas flow. Finally, the introducing the first precursor is discontinued while maintaining the purge gas flow.

[0013] Integrated circuit capacitors may be fabricated, according to some embodiments of the invention, by forming a lower electrode of the capacitor on a substrate, forming a dielectric layer of the capacitor including titanium tantalum oxide on the lower electrode, and forming an upper electrode of the capacitor on the dielectric layer. In order to form the dielectric layer of the capacitor, a first reacting material, a second reacting material, and a purge gas are discontinuously introduced onto the lower electrode, and a portion of the first reacting material and the second reacting material are chemisorbed onto the substrate. At least some non-chemisorbed first and second reacting materials are purged from the substrate. The first reacting material can include a tantalum precursor and a titanium precursor, and the second reacting material can include oxygen. The purging gas can include an inert gas.

[0014] Integrated circuit field effect transistors may be fabricated, according to some embodiments of the invention, by forming a gate dielectric layer of the transistor including titanium tantalum oxide on a substrate, forming a gate electrode on the gate dielectric layer, and forming source and/or drain regions, for example, by implanting impurities into the substrate using the gate electrode as a mask. In order to form the gate dielectric layer of the transistor, a first reacting material, a second reacting material, and a purge gas are discontinuously introduced onto the substrate, and a portion of the first reacting material and the second reacting material are chemisorbed onto the substrate. At least some non-chemisorbed first and second reacting materials are purged from the substrate. The first reacting material can include a tantalum precursor and a titanium precursor, and the second reacting material can include oxygen. The purging gas can include an inert gas.

[0015] According to embodiments of the present invention, a thin film layer may be formed to include titanium tantalum oxide so that the dielectric constant of the thin film layer may be increased, and the step coverage and leakage current characteristic thereof also can be improved. Further, the titanium tantalum oxide thin film layer may form the dielectric layer of a capacitor and/or the gate oxide layer of a transistor. Therefore, thin films according to embodiments of the present invention can be widely used in semiconductor devices having a high degree of integration.

[0024] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Also, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.

[0025] FIGS. 1A to 1E are cross-sectional views showing a method for forming a thin film through an ALD process according to embodiments of the present invention. Referring to FIG. 1A, a substrate 1 of semiconductor material such as silicon is disposed in a depositing chamber, conceptually shown as 3, and a first reacting material 2 including a tantalum precursor and a titanium precursor is introduced to the substrate 1. The tantalum precursor includes TaCl₅, Ta(OCH₃)₅, Ta(OC₂H₅)₅, Ta(OC₃H₇)₅, Ta(OC₄H₉)₅, Ta(OC₂H₅)(OC₃H₇)₄, TAT-DAME (Ta(OC₂H₅)₄ [OC₂H₅N(CH₃)₂]), and/or a combination thereof. In some embodiments, only one tantalum precursor is used. Hereinafter, the word “DAME” is used as an abbreviation of dimethylaminoethoxide, meaning the group of —OC₂H₅N(CH₃)₂—. Further, the titanium precursor includes TiCl₄, Ti(OCH₃)₄, Ti(OC₂H₅)₄, Ti(OC₃H₇)₄, Ti(OC₄H₉)₄, Ti(OC₂H₅)(OC₃H₇)₄, Ti(OC₃H₇)₂(O₂C₁₁H₁₉)₂, Ti(OEt₂)(DAME)₂, or a combination thereof. In some embodiments, only one titanium precursor is used. Hereinafter, the word “OEt” is used to designate the group of —OC₂H₅—.

[0026] In some embodiments, the tantalum precursor and the titanium precursor are introduced to the substrate 1 in a mixed state, which is referred to as a mixed precursor. Examples of the mixed precursors are TAT-DAME/Ti(OEt)₂(DAME)₂ (hereinafter, referred to as TT), and/or Ta(OC₂H₅)₅/Ti(OC₂H₅)₄. The mixed precursor is preferably introduced to the substrate 1 through the same introducing line 5 in a mixed state. When the first reacting material 2 is introduced, an inert gas can be used as a carrier gas for carrying the first reacting material into the chamber 3. The inert gas includes argon (Ar) gas, nitrogen (N₂) gas, combinations thereof and/or other carrier gases.

[0027] Referring to FIG. 1B, a first portion of the first reacting material 2 is chemisorbed (chemically absorbed) onto the substrate 1, and therefore, a layer 4 is formed on a surface of the substrate 1. A second portion of the first reacting material 2 is physisorbed (physically absorbed) on the upper (outer) portion of the layer 4. That is, the second portion of the first reacting material 2 is loosely combined with the layer 4. Continuously, the inert gas, which is used as a carrier gas of the first reacting material, is again introduced into the chamber 3 without the first reacting material 2. As a result, the non-chemisorbed first reacting material, namely at least some of the second portion of the first reacting material, is purged out from the chamber 3 and, in some embodiments, only chemisorbed layer 4 of the first reacting material 2 remains on the substrate 1.

[0028] Referring to FIG. 1C, a second reacting material 6 is introduced into the chamber 3. The second reacting material 6 includes O₂, O₃, H₂O, H₂O₂, N₂O, alcohols having —OH group, or a combination thereof. In some embodiments, only a single second reacting material is used. In some embodiments, the second reacting material is introduced in an activated state by ultraviolet rays, in an activated state of a plasma, in an activated state by a remote plasma process and/or using other activation techniques. For example, an ozone (O₃) gas created by a plasma generator, a plasma O₂ gas, a plasma N₂O gas, and/or a remote plasma O₂ gas can be used as the second reacting material. Another example of the second reacting material can include an oxygen (O₂) gas and/or ozone (O₃) gas created by an ozone generator. Then, the second reacting material 6 is reacted with the chemisorbed layer 4 of the first reacting material 2. As a result, a solid material 8 of an atomic unit is formed on the substrate 1. Namely, the solid material 8 including tantalum titanium is formed on the substrate 1 through reaction between the first reacting material 2 and the second reacting material 6.

[0029] Referring to FIG. 1D, the inert gas is again introduced into the chamber 3, without the second reacting material 6, and at least some of the non-chemisorbed second reacting material 6 is purged from the chamber. As a result, the solid material 8 including tantalum titanium is completely formed on the substrate 1. That is, a thin film having a thickness of an atomic unit (hereinafter, referred to as and atomic layer) is formed on the substrate 1. Sequential repeating of the steps of introducing the first reacting material, purging the first reacting material, introducing the second reacting material, and purging the second reacting material can form an atomic layer 8a having a desired thickness as shown in FIG. 1E.

[0030] Subsequently, in some embodiments, the atomic layer 8a having a predetermined thickness is heat-treated to fill vacancies in the atomic layer. The heat treatment is carried out by radiating ozone (O₃) ultraviolet rays at a temperature range of about 650° C. to about 700° C., by flowing activated oxygen at a temperature range of about 700° C. to about 800° C. and/or using other techniques. Therefore, the atomic layer 8a can be condensed into a compact structure.

[0031] As is well known, the tantalum precursor and the titanium precursor, which may be used as precursors in a conventional CVD process, may be decomposed at a high temperature. Therefore, in some embodiments, the ALD process using the tantalum precursor and the titanium precursor according to embodiments of the present invention is carried out in a temperature range of about 200° C. to about 600° C. and, in some embodiments, at a temperature of about 400° C. Further, the tantalum precursor and the titanium precursor has a higher vapor pressure than that of some other precursors, such as a halogenide precursor. Namely, the number of molecules in a vapor state of the tantalum precursor or the titanium precursor is larger than that of some other precursors. Therefore, in performing the ALD process, a larger quantity of precursor gas may be provided into the process chamber compared with the other precursors, so that a larger number of the precursor gas molecules can reach a bottom surface of a stepped portion of the atomic layer. As a result, when the tantalum precursor and the titanium precursor are used during a deposition process according to embodiments of the present invention, the layer can be deposited to have good step coverage.

[0032] In addition, since the conventional CVD process for depositing a thin film is carried out at not less than about 500° C., a heat budget of high temperature is created during the process, which may make it difficult to deposit the thin film with a thickness no more than about 20 Å. However, ALD processes according to some embodiments of the present invention can deposit the thin film with a thickness of several Ångstroms.

[0033] As described above, embodiments of the present invention can deposit a tantalum titanium oxide (TaTiO) layer having relatively good step coverage and relatively constant thickness at a relatively low temperature. Furthermore, an atomic ratio of the tantalum and the titanium in the TaTiO layer can be controlled according to embodiments of the present invention. In one embodiment, the atomic ratio of the tantalum and the titanium is set to be about 1:0.01 to 0.2. This controlling of the atomic ratio of the tantalum and the titanium can improve a dielectric constant and/or a leakage current characteristic of the thin film.

[0034] Hereinafter, characteristics of a layer deposited by embodiments of the present invention will be described. A TaTiO layer specimen was deposited through an ALD process in which TAT-DAME was used as the tantalum precursor, Ti(OEt)₂(DAME)₂ was used as the titanium precursor, and ozone (O₃) was used as an oxidizer. A TT depositing step, a first argon (Ar) purging step, an ozone (O₃) depositing step, and a second argon (Ar) purging step were carried out for 4 seconds, 4 seconds, 2 seconds, and 4 seconds, respectively. A temperature of the chamber was varied from about 200° C. to about 550° C. during the ALD process. Then, various characteristics of the TaTiO layer specimen were measured.

[0035] Relation between the Deposition Rate and the Deposition Temperature

[0036] FIG. 2 is a graph showing a relation between a deposition temperature and a deposition rate of a tantalum titanium oxide layer deposited according to some embodiments of the present invention. The horizontal axis in FIG. 2 is a temperature of deposition, and the vertical axis is a deposition rate (Å/cycle).

[0037] Referring to FIG. 2, the deposition rate of the TaTiO layer has a minimum value at a temperature of about 200° C., and rapidly increases at a temperature of 450° C., which indicates that the TaTiO layer shows ALD characteristics in a temperature range of about 200° C. to about 450° C., and shows CVD characteristics at a temperature of about 450° C. or more. Accordingly, in some embodiments, the TaTiO layer is deposited at a temperature less than about 450° C. and, in other embodiments, in a temperature range of about 250° C. to about 350° C.

[0038] Relation between Number of Deposition Cycles and a Layer Thickness

[0039] FIG. 3 is a graph showing a relation between a thickness of the TaTiO layer and the number of deposition cycles thereof according to some embodiments of the present invention. The horizontal axis of the graph as shown in FIG. 3 is number of deposition cycles and the vertical axis is layer thickness. The deposition process was carried out at a temperature of about 400° C.

[0040] Referring to FIG. 3, since the TaTiO layer shows the ALD characteristics around the temperature of 400° C., the thickness of the layer is linearly increased as the number of deposition cycles is increased. Therefore, the TaTiO layer deposited through the ALD process using the TT and the ozone (O₃), can have good thickness controllability and superior uniformity, and can also be reduce a pattern-loading effect. In addition, the TaTiO layer can provide good step coverage of no less than about 90% in a structure having an aspect ratio no less than about 10:1, in some embodiments.

[0041] Relation between Post Heat Treatment and Crystallization of a Thin Film

[0042] FIG. 4 is a graph showing a crystal density of the TaTiO layer before and after a heat treatment. An X-ray diffraction (XRD) analysis apparatus was used for measuring the crystal density. In FIG. 4, curve A shows the crystal density of the TaTiO layer before a heat treatment. Curve B shows the crystal density of the TaTiO layer after the heat treatment wherein activated oxygen is introduced at a temperature of about 650° C. Curve C shows the crystal density of the TaTiO layer after the heat treatment wherein activated oxygen is introduced at a temperature of about 700° C. The horizontal axis is the diffraction angle, also called a Bragg diffraction angle, and the vertical axis is an intensity of emitted ions.

[0043] Referring to FIG. 4, it can be seen that a state of the TaTiO layer as shown in curve A and curve B is amorphous, and a state of the TaTiO layer in curve C is not amorphous since the curve C shows at least one peak. The peak points of the curve C are formed since the state of the TaTiO layer is transferred from the amorphous state into a crystal structure of an orthorhombic system when activated oxygen is introduced at a temperature of about 700° C. Therefore, ozone (O₃) radiation in a temperature range of about 650° C. to about 750° C. or heat treatment wherein activated oxygen is introduced at a temperature of about 700° C. to about 800° C. may be used for depositing the TaTiO layer of a compact crystal structure. Furthermore, tantalum oxide (TaO) is found at the peak points of the curve C, which appears to indicate that the TaTiO layer is not formed of chemical bonds of Ta—Ti or Ta—Ti—O but, rather, chemical bonds of Ta—O and Ti—O independent from each other. In experiments related to FIG. 4, the chemical bond of Ti—O was rare, which apparently is not because Ti—O bond does not exist in the TaTiO layer but, rather, appears to be because the number of Ta atoms is relatively larger than that of the Ti atoms.

[0044] Depth Profile of a Thin Film

[0045] FIG. 5 is a graph showing a relation between an etching time and ion density emitted from the cross-sectional surface of the TaTiO layer deposited by embodiments of the present invention. The graph is formed based on data measured by time of flight secondary ion mass spectrometer (TOF-SIMS). The horizontal axis is an etching time, and the vertical axis is intensity of ions that is emitted from an etched cross-sectional surface per unit time. A specimen TaTiO layer of the FIG. 5 was deposited according to the above-described method after a nitride layer was deposited on a silicon substrate.

[0046] Referring to FIG. 5, the chemical bond of TaO and TiO was uniformly detected irrespective of the TaTiO layer depth. Therefore, the TaTiO layer can be deposited to have good stoichiometric characteristics without including impurities that can be electron trap sites and/or leakage current sites.

[0047] FIGS. 6A to 6E are cross-sectional views showing methods for fabricating a semiconductor device according to embodiments of the present invention. Referring to FIG. 6A, a gate dielectric layer 104, gate electrode 110 and source/drain regions 116a and 116b are formed on a semiconductor substrate 100 including an active area 101 defined by an isolation region (or field area) 102. It may be desirable for a thin gate dielectric layer have a thickness of about 10 Å or so, so that the gate dielectric layer 104 may be deposited using embodiments of the present invention. Namely, in some embodiments, the gate dielectric layer 104 is formed to include TaTiO through the ALD process using an activated oxidizer. Examples of the activated oxidizer may include tantalum precursors, titanium precursors, ozone (O₃), plasma O₂, remote plasma O₂ and/or plasma N₂O. The TT and ozone (O₃) can be used for forming the gate dielectric layer 104 including the TaTiO in some embodiments.

[0048] The gate electrode 110 may have a polycide structure including a polysilicon layer 106 doped with impurities and a silicide layer 108. A capping insulating layer 112 is formed on an upper surface of the gate electrode 110, and a side spacer 114 is also formed on side surfaces of the gate electrode 110. Both the capping insulating layer 112 and the side spacer 114 may comprise silicon oxide and/or silicon nitride.

[0049] Referring to FIG. 6B, a first insulating layer 118 comprising an oxide is formed on the whole surface of the substrate 100. Then the first insulating layer 118 is selectively etched through a photolithography process to thereby form a contact hole 120 partially exposing the source region 116a. Subsequently, a first conductive layer, for example a polysilicon layer doped with phosphorus (P), is deposited in the contact hole 120 and on the first insulating layer 108, and removed to a surface of the first insulating layer 118 through an etch-back process and/or a chemical mechanical polishing (CMP) process. As a result, the contact hole 120 is filled with the first conductive layer to thereby form a contact plug 122.

[0050] Referring to FIG. 6C, an etch stop layer 123 is formed on the contact plug 122 and/or the first insulating layer 118. In some embodiments, the etch stop layer 123 can be formed as a high etching selectivity layer with respect to the first insulating layer 118, such as silicon nitride (Si_xN_y, wherein x and y are positive numbers) layer and/or a silicon oxynitride (SiON) layer. A second insulating layer 124 comprising an oxide is formed on the etch stop layer 123, and then is selectively etched, to thereby form an opening portion 126 exposing the contact plug 126. In more detail, the second insulating layer 124 is selectively etched until the etch stop layer 123 is exposed, and then is still further etched, that is over-etched. As a result, the opening portion 126 is formed. A sidewall of the opening portion 126 may be formed to slope downwards so that a cross-sectional area of an opening upper portion of the opening portion 126 is larger than that of a bottom portion of the opening portion 126, since an etching rate of the opening upper portion is different than that of the bottom portion of the opening portion due to a loading effect during the etching process. Then, a second conductive layer 127 is deposited on the sidewall and on the bottom surface of the opening portion 126 and on a surface of the second insulating layer 124. The second conductive layer 127 comprises a semiconductor material such as polysilicon, rare metals, such as ruthenium (Ru), platinum (Pt), Iridium (Ir) and the like, or conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN) and/or tungsten nitride (WN).

[0051] Referring to FIG. 6D, a dummy layer (not shown) is deposited on the second conductive layer 127 and on the opening portion 126, and subsequently, is etched back so that the second conductive layer 127 remains only on the sidewall and bottom surface of the opening portion 126. Accordingly, the second conductive layer 127 deposited on a surface of the second insulating layer 124 is removed, and only the second conductive layer 127 deposited along an inside profile of the opening portion 126 remains so that the second conductive layer 127 is separated into respective cell units of the substrate. Subsequently, the dummy layer is removed through a wet etching process, and finally a lower electrode layer 128 of a capacitor of the respective cell area is formed. Therefore, the lower electrode layer 128 is formed into a cylinder shape having a height of about 10,000 Å to about 17,000 Å with wide inlet and narrow bottom.

[0052] A dielectric layer 130 of the capacitor including TaTiO is formed on the lower electrode layer 128 through an ALD process according to some embodiments of the present invention using activated oxides, such as tantalum precursors, titanium precursors, ozone (O₃), plasma oxygen (O₂), remote plasma oxygen (O₂) and/or plasma N₂O. In some embodiments, the dielectric layer 130 of the capacitor including the TaTiO may be formed on the lower electrode layer 128 through the ALD process using the TT and ozone (O₃). Accordingly, the dielectric layer 130 can be deposited on the lower electrode layer 128 having an aspect ratio no less than about 10:1 with superior step coverage. In some embodiments of the present invention, the dielectric layer 130 can be deposited in such a structure such that a ratio between a upper thickness (t₁) and a lower thickness (t₂) is no less than about 1:0.9. When the lower electrode layer 128 is comprised of polysilicon, oxygen gases derived from the oxides are reacted with silicon in the lower electrode layer 128 and, therefore, the lower electrode layer 128 is oxidized during the process of forming the dielectric layer 130. Therefore, before the forming the dielectric layer 130, a surface of the lower electrode layer 128 may be nitrified through a rapid thermal nitrification (hereinafter, referred to as RTN) process in a nitride ambient for reducing or preventing the dielectric layer 130 from being reacted with the lower electrode layer 128.

[0053] After depositing the dielectric layer 130 through the ALD process by using oxides, the dielectric layer 130 is heat-treated in an oxygen ambient, such as ultraviolet-ozone (hereinafter, referred to as UV-O₃) so that impurities are removed and oxygen deficiency can be sufficiently cured. In addition, the heat treatment can transform a crystal state of the dielectric layer 130.

[0054] Referring to FIG. 6E, an upper electrode layer 132 of the dielectric layer 130 is deposited, and therefore, the capacitor C is formed to comprise the lower electrode layer 128, the dielectric layer 130, and the upper electrode layer 132. The upper electrode layer 132 can comprise a semiconductor material, rare metals, such as ruthenium (Ru), platinum (Pt), Iridium (Ir) and the like, or conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In some embodiments, the upper electrode layer 132 is formed to have a stacked structure of titanium nitride (TiN) and polysilicon.

[0055] It will be understood by those having skill in the art that many other configurations of integrated circuit field effect transistors and/or integrated circuit capacitors may be fabricated with gate dielectric layers and/or capacitor dielectric layers, respectively, according to embodiments of the present invention. Accordingly, the embodiments that were described with respect to FIGS. 6A–6E are exemplary and should not be regarded as limiting the present invention.

[0056] Measurement of a Capacitor Leakage Current

[0057] FIG. 7 and FIG. 8 are graphs showing a leakage current characteristics of a capacitor including a dielectric layer deposited through an ALD process according to embodiments of the present invention. In FIGS. 7 and 8, the horizontal axis denotes a voltage applied to the capacitor, and the vertical axis denotes a leakage current of the capacitor. Four groups of capacitors, a first to a fourth sample capacitors, were put into the experiment for measuring the leakage current of the capacitor.

[0058] The first sample capacitor was formed through the process as described in FIGS. 6A to 6E. First, a surface of the lower electrode layer including polysilicon doped with phosphorus (P) was nitrified through the RTP process. Then, a first TaTiO atomic layer was formed to a thickness of 20 Å on the lower electrode layer at a temperature range of about 200° C. to about 400° C. by using the TT and ozone (O₃), and a first heat treatment was carried out on the first TaTiO atomic layer by using UV-O₃ at a temperature of about 700° C. A second TaTiO atomic layer was formed to a thickness of 35 Å on the first TaTiO layer through an in situ multi-layer process by using the TT and ozone (O₃), and a second heat treatment was carried out on the second TaTiO atomic layer by using the UV-O₃ under the same conditions as the first heat treatment. Therefore, the TaTiO dielectric layer was formed of two atomic layers. Subsequently, a titanium nitride (TiN) layer was deposited on the TaTiO dielectric layer by using source gases, such as TiCl₄ or NH₃, and a P-doped polysilicon layer was deposited on the titanium nitride (TiN) layer. Thus, an upper electrode layer of capacitor was formed as a composite layer of TiN/polysilicon.

[0059] The second sample capacitor was formed as follows:

[0060] First, a first Ta₂O₅ layer was formed to a thickness of 20 Å, and a first heat treatment was carried out using the UV-O₃ on the first Ta₂O₅ layer. Then, a second Ta₂O₅ layer was formed to a thickness of 70 Å on the first Ta₂O₅ layer, and a second heat treatment was carried out using the UV-O₃ on the second Ta₂O₅ layer. Other process conditions were the same as those of the first sample capacitor. In FIG. 7, the leakage current of the first sample capacitor is expressed as a dotted line, and the leakage current of the second sample capacitor is displayed as a solid line.

[0061] Referring to FIG. 7, while the leakage current characteristic of the first and the second sample capacitors are similar to each other, the capacitance of the first and the second sample capacitor is 17.3 fF/cell and 15.3 fF/cell, respectively. Accordingly, when a TaTiO layer according to embodiments of the present invention is used as the dielectric layer of the capacitor, the capacitance of the capacitor can be increased 10% as compared when the Ta₂O₅ layer is used as the dielectric layer of the capacitor.

[0062] The third sample capacitor had the same structure as that of the first sample capacitor except that the second TaTiO layer had a thickness of about 30 Å.

[0063] The fourth sample capacitor was formed as follows: First, a Ta₂O₅ layer was formed to a thickness of 30 Å, and a first heat treatment was carried out using the UV-O₃ on the Ta₂O₅ layer. Then, a TiO₂ layer was formed to a thickness of 100 Å on the Ta₂O₅ layer, and a second heat treatment was carried out using the UV-O₃ on the TiO₂ layer. Other process conditions were the same as those of the first sample capacitor. In FIG. 8, the leakage current of the third sample capacitor is expressed as a dotted line, and the leakage current of the fourth sample capacitor is displayed as a solid line.

[0064] Referring to FIG. 8, while the effective thickness (T_ox) of the third and fourth sample capacitor are the same at about 31.1 Å, the leakage current characteristic of the third sample capacitor is superior to that of the fourth sample capacitor. Accordingly, when a TaTiO layer according to an embodiment of the present invention is used and the dielectric layer of the capacitor is formed as a single TaTiO layer, the leakage current characteristic of the capacitor can be sufficiently improved as compared when and the dielectric layer of the capacitor is formed as a sequentially stacked composite layer of the Ta₂O₅ layer and the TiO₂ layer.

[0065] Measurement of an Effective Thickness and Thickness Variance of the Dielectric Layer

[0066] FIG. 9 is a graph showing a relation between thickness variation of the dielectric layer and an effective thickness thereof deposited through an ALD process according to embodiments of the present invention. The third sample capacitor was used in the experiment as one embodiment of the present invention. The effective thickness is expressed as T_ox, and means a thickness of oxide layer formed by chemical reaction between the lower electrode layer and the dielectric layer. Generally, the effective thickness is linearly proportional to a thickness of the dielectric layer.

[0067] Referring to FIG. 9, it can be noted that the effective thickness is increased when the thickness of the dielectric layer is about 55 Å, which indicates that the capacitance of the capacitor can be improved by forming the capacitor to have a thickness of dielectric layer at which the effective thickness is minimized.

[0068] According to embodiments of the present invention, a thin film of superior leakage current characteristic may be formed to have a high dielectric constant and good step coverage, which can be used in semiconductor devices including minute patterns. The thin film can be used as the dielectric layer of the capacitor, which can provide good step coverage, superior leakage current characteristic, and/or high dielectric constant. In addition, the thin film may be hardly oxidized on a lower electrode layer having a high aspect ratio. Furthermore, the thin film can also be used as a gate dielectric layer of a transistor that can reduce or minimize oxidation on a boundary surface. Therefore, the reliability of the semiconductor device can be improved by forming a thin film using the above-described methods.

[0069] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.