Measurement control apparatus including interface circuits

[0001] This application claims priority of Japanese patent Application No. 2001-101356, filed on Mar. 30, 2001.

[0002] 1. Field of the Invention

[0003] The present invention relates to a measurement control apparatus, more particularly-relates to a measurement control apparatus for measuring a measurement controlled object using a processor (PC) through an interface.

[0004] As one example, there is a measurement control system for an electronic control unit (ECU) mounted on a vehicle which measures and evaluates the same using a PC. This system is realized by a measurement control apparatus. In general, a PC is used as the heart of the measurement control apparatus. In this case, the digital input/output (I/O) board is often used.

[0005] The digital I/O board for a PCI bus is similarly connected to a digital I/O unit of the measurement controlled object (the above ECU etc.). In this case, the level of the digital I/O board of the former (PC) is usually a TTL level of for example 5V. As opposed to this, the level of the digital I/O unit of the latter (ECU) is the battery voltage-GND level of for example 13V. Therefore, the measurement control apparatus has to include as components not only the above PC, but also an interface circuit for achieving a match between the two electrically.

[0006] On the other hand, according to the above example, different types of ECUs are used as the ECUs mounted in vehicles according to the types of the vehicles. This being the case, the interface circuit also must be selected to be compatible with the ECU in question. The present invention relates to a technique for selecting an interface circuit compatible with each ECU.

[0007] 2. Description of the Related Art

[0008] As will be explained later with reference to FIG. 10, in general a measurement control apparatus is mainly comprised of a measurement control processor and interface circuits. When a measurement controlled object is given, one interface circuit compatible with that object is used so as to output measurement control data compatible with the object from the processor to the object. When response data is returned from the object operating based on this measurement control data, this is input to the processor through the interface circuit. The processor analyzes this response data to evaluate the object. Therefore, in a conventional measurement control apparatus, there was the problem that considerable work and time were required to assemble a compatible interface circuit into the apparatus when a new measurement controlled object was presented for measurement.

[0009] Further, when a user performed a later explained reconnection operation or channel reconfiguration operation, a mistake by the user (error in reconnection or error in reconfiguration) in the work for reconnection or channel reconfiguration would cause the measurement controlled object to break down or sometimes burn out.

[0010] An object of the present invention is to provide a measurement control apparatus which does not require manual switching of the interface circuit by the user and can eliminate breakdowns or burnout of the measurement controlled object.

[0011] To attain the above object, the measurement control processor (2) outputs interface setting data for setting one interface circuit (3) compatible with the measurement controlled object in advance of output of measurement control data to the measurement controlled object (4). Based on this, an interface setting means (10) activates only that interface circuit. Further, the processor is provided with a loopback means (20) for returning the interface setting data to the measurement control processor (2) and confirms the match of the output interface setting data and the returned interface setting data. Further, it is provided with an identification code setting means (30) for setting an identification code unique to an interface board carrying the interface circuits (3) and confirms that the interface board has been correctly selected. Due to this, it is possible to automatically select the interface circuit compatible with the measurement controlled object without error.

[0023] Before describing the embodiments of the present invention, the related art and the disadvantages therein will be described with reference to the related figures.

[0024] FIG. 10 is a view of the conventional configuration of a measurement control apparatus. In the figure, reference numeral 1 represents a measurement control apparatus. The apparatus 1 is mainly comprised of a measurement control processor 2 and interface circuits 3. When a measurement controlled object 4 is given, one interface circuit 3 compatible with that object 4 is used so as to output measurement control data compatible with the object 4 from the processor 2 to the object 4. When response data is returned from the object 4 operating based on this measurement control data, this is input to the processor 2 through the interface circuit 3.

[0025] When for example the measurement controlled object 4 is the above ECU, rather than mount this ECU into an actual vehicle, it is possible to simulate the operating state of the vehicle by a PC (FIG. 10). In general, this is called a “hardware in the loop simulation (HILS)” system.

[0026] As explained above, there are a plurality of interface circuits 3 provided corresponding to the circuit configurations of the various measurement controlled objects 4. Therefore, in the past, when a new measurement controlled object 4 was presented for measurement, one of the following operations had to be performed by the user manually:

[0027] i) preparing an interface circuit 3 compatible with the newly given measurement controlled object 4,

[0028] ii) designing and preparing a plurality of types of interface circuits in advance and reconnection is achieved by using a switch for switching to one interface circuit compatible with an object 4 which is given, and

[0029] iii) preparing a plurality of channels of fixed interface circuits in advance and reconfiguring the channels in accordance with the object 4 given.

[0030] Therefore, in a conventional measurement control apparatus 1, there was the problem that considerable work and time were required to assemble a compatible interface circuit into the apparatus 1.

[0031] Further, looking in particular at the above operation ii) or iii), when a user performed the reconnection operation or channel reconfiguration operation, a mistake by the user (error in reconnection or error in reconfiguration) in the work for reconnection or channel reconfiguration would cause the measurement controlled object 4 to break down or sometimes burn out.

[0032] Therefore, the present invention realizes a measurement control apparatus which does not require manual switching of the interface circuit by the user and can eliminate breakdowns or burnout of the measurement controlled object. This will be explained in detail below.

[0033] FIG. 1 is a view of the basic configuration of the present invention. Note that throughout the drawings, the same components are assigned the same reference numerals or symbols. In FIG. 1, looking first at the already explained interface circuits 3, a plurality of types of circuits are prepared in advance and grouped together to form an interface circuit unit 5.

[0034] Similarly, a plurality of types of input interface circuits 6 are prepared in advance and grouped together to form an input interface circuit unit 7. The point to particularly note in this figure is the introduction of an interface setting means 10. Preferably, a loopback means 20 and an identification code setting means 30 are also introduced.

[0035] First, basically, the measurement control apparatus 1 according to the present invention is provided with an interface circuit unit 5 having a plurality of types of interface circuits 3 compatible with a plurality of types of measurement controlled objects 4 and a measurement control processor 2 for selecting one interface circuit compatible with any one measurement controlled object 4 and executing predetermined measurement control.

[0036] In such a measurement control apparatus 1, when a measurement controlled object 4 is given, the measurement control processor 2 outputs from the output port Do interface setting data ds (select data) for setting one interface circuit 3 compatible with a measurement controlled object 4 among the plurality of types of interface circuits 3 in advance of output of the measurement control data dm (measurement data) from the output port Do to the measurement controlled object 4.

[0037] Here, the above interface setting means 10 does not allow input of the interface setting data ds to the interface circuit unit 5 while the interface setting data ds is being output.

[0038] Further, the loopback means 20 returns the interface setting data ds latched to the interface setting means 10 to the input port Di of the measurement control processor 2. Further, the measurement control processor 2 confirms that the interface setting data which it output itself and the returned interface setting data match.

[0039] Further, the identification code setting means 30 is configured to enable a unique identification code set for each of the plurality of types of interface circuits 3 to be sent to the input port Di of the measurement control processor 2. When one interface circuit 3 is selected, the unique identification code set for the interface circuit is sent from the identification code setting means 30 to the measurement control processor 2.

[0040] The measurement control processor 2 confirms that the interface circuit corresponding to the sent identification code matches the interface circuit which has set by the processor itself.

[0041] Due to the above basic configuration of the present invention, there is no longer any need for a user to manually select an interface circuit as in the related art. Further, the correctness of the selection is automatically confirmed by the processor, so there is almost never breakdown or burnout of the measurement controlled object.

[0042] FIG. 2 is a view of a first embodiment of the present invention.

[0043] In the figure, the interface setting means 10 of FIG. 1 is shown more concretely. That is, the means 10 is comprised of a latch circuit 11 and a gated buffer circuit 12.

[0044] The latch circuit 11 latches interface setting data ds from the output port Do of the processor 2 by the illustrated L (Latch) signal among the control signals from the measurement control processor 2. The processor 2 knows what kind of object the object to be measured is, so can designate the one interface circuit 3 compatible with that object by the data ds. The data ds is output sharing the output port Do outputting the inherent measurement control data dm and in advance of the transmission of that data dm. This is one of the characterizing features of the present invention.

[0045] In this case, the interface setting data ds must not be input to the interface circuit unit 5 side while the data ds is being transmitted from the output port Do (input prohibited). The reason is that the data ds is not the inherent measurement control data dm to be input to the measurement controlled object 4. Therefore, the gated buffer circuit 12 is turned off by one of the control signals from the processor 2, that is, the S (Select) signal.

[0046] Next, the interface setting data ds is held by the latch circuit 11 so as to continue to make the set interface circuit 3 active while the inherent measurement control data dm is continuing to be output, that is, while the processor 2 is evaluating the measurement controlled object 4.

[0047] The present invention is sufficient if applied to only the output side (Do) of the measurement control processor 2, but it is also possible to provide, in addition to the interface circuit unit 5, an input interface circuit unit 7 arranged at the input side for receiving response data from the measurement controlled object 4 to the measurement control processor 2 and having a plurality of input interface circuits 6 compatible with a plurality of types of measurement controlled objects 4.

[0048] Further, the interface setting means 10 also sets one compatible input interface circuit 6. This setting is performed by the latch circuit 11. Note that the time charts of the data and signals output from the processor 2 will be explained in detail later with reference to FIG. 7 and FIG. 8.

[0049] In this way, the present invention divides the output state of one output port Do into the “state of output of data for switching the interface circuit” and “state of output of inherent measurement control data to the measurement controlled object 4 through the switched interface circuit” and generates these two states in a time-division manner.

[0050] The only components added for generating these two states by time-division are the L signal and S signal. Specifically, for example, when the digital signal port is composed of an 8-ch (channel) and 8 ch of interface switching signals are required for each port, if the switching signals are prepared separately, a total of 8 ch digital signals becomes necessary. As opposed to this, according to the present invention, only the two above L signal line and S signal line are sufficient.

[0051] FIG. 3 shows a second embodiment of the present invention.

[0052] The second embodiment, as shown in the figure, further includes the loopback means 20. This means 20 is mainly comprised of the gated buffer circuit 21. Interface setting data ds latched at the latch circuit 11 is returned to the input port Di of the measurement control processor 2 through this buffer circuit 21. The processor 2 compares the data ds which it output itself first and the returned data ds and can confirm that the interface setting data ds was correctly output when judging that the two match.

[0053] The buffer circuit 21 for returning the data can be turned on by the above S signal among the control signals.

[0054] In this case, the data from the input interface circuit unit 7 side must be blocked while the data ds is being returned to the input port Di by the buffer circuit 21. This is because if the two data are combined, the data ds cannot be correctly confirmed.

[0055] Therefore, an input gate unit 22 for controlling the passing of the response data dr from the measurement controlled object 4 to the measurement control processor 2 or prohibiting its transmission is provided at the output side of the input interface circuit unit 7. When the loopback means 20 is to be activated (gated buffer circuit 21 is turned on), the transmission of the response data dr must be prohibited by this input gate unit.

[0056] Therefore, according to the second embodiment of the present invention, it is possible for the processor 2 to monitor the interface setting data ds output by the measurement control processor 2 and improve the reliability of the selection of the interface circuit 3.

[0057] Note that in the above example, the interface setting data ds latched at the latch circuit 11 was looped back, but if actually monitoring and looping back the state of the contact of the relay R switched in accordance with the setting data ds, it is possible to more realistically and accurately monitor the same. In this case, it is also possible to make the relay R by double throw contact relay, use one of the contacts for the interface, and use the other contact (electrically isolated from the first contact) for the monitoring.

[0058] FIG. 4 is a view of a third embodiment of the present invention.

[0059] The third embodiment is characterized by provision of the identification code setting means 30.

[0060] There are usually several interface boards 8 carrying the interface circuit unit 5 and input interface circuit unit 7. Confirming whether the interface board 8 is correctly set is also effective in preventing breakdowns or burnout of the measurement controlled object 4 in advance. Therefore, the above identification code setting means 30 is provided.

[0061] The identification code setting means 30 can be realized in one example by the illustrated code setting circuit 31. In the example of the figure, the lines corresponding to the bits Di0 to Di3 are pulled up, the lines corresponding to the bits Di4 to Di7 are pulled down, and the identification code (00001111) is applied to the input port Di.

[0062] In this case, the input interface circuit unit of the 7 side of the code setting circuit 31 has to be set in the high impedance (Hz) state. That is, the input gate unit 22 has to be turned off. Further, while not shown in FIG. 4, the gated buffer circuit 21 forming the loopback means 20 shown in FIG. 3 also has to be turned off. This is because if it is not set in the high impedance state in this way, the intended bit data (00001111) cannot be output from the code setting circuit 31. Note that when either the gated buffer circuit 21 or the input gate unit 22 is turned on, the bit (H/L) of the data thereof passes through the code setting circuit 31 as it is.

[0063] Therefore, according to the third embodiment of the present invention, selection of an erroneous interface board 8 is prevented.

[0064] FIG. 5 is a first part of a view of a fourth embodiment of the present invention, while FIG. 6 is a second part.

[0065] The fourth embodiment combines all of the first to third embodiments discussed up to here. The parts were already explained. In particular, the component newly shown in the figures is the logic gate 41. This logic gate 41 is useful in preparing the high impedance state explained in the third embodiment. That is, only when confirming the identification code by the S signal and the L signal, the gated buffer circuit 21 and the input gate unit 22 are both turned off and the high impedance state can be prepared. Next, the sequence of the data and signals of the principal parts in FIG. 5 and FIG. 6 will be explained.

[0066] FIG. 7 is a first part of a time chart of the data and signals of the principal parts of the fourth embodiment, while FIG. 8 is a second part of the time chart.

[0067] The time charts of FIG. 7 and FIG. 8 will be explained while referring to FIG. 5 and FIG. 6. Note that among the types of data or signals in the columns at the left in FIG. 7, the ones first defined here are a, a′, and b. These a, a′, and b are the control signals appearing at a, a′, and b in FIG. 5 and FIG. 6.

[0068] The period from the time t1, where the L signal is switched from H (high) to L (low), to t2 is the operation according to the third embodiment of FIG. 5 and FIG. 6, that is, the operation of the processor 2 confirming the identification code (I/F code) of the interface board 8. At this time, through the intervention of the logical gate 41 of FIG. 5, the signals a, a′, and b are generated from the S signal and the L signal, the gated buffer circuit 21 and the input gate unit 22 are simultaneously turned off, and the above mentioned high impedance state is created. Note that at this time, the gated buffer circuit 12 is off, while the latch circuit 11 is on.

[0069] Next, at the time t2, when the S signal switches from H to L, the output phase of the interface setting data is started. This is the phase in which the first embodiment of FIG. 2 functions.

[0070] Further, at the time t3, the measurement control processor 2 outputs the above interface (I/F) setting data ds from the Do port.

[0071] While the interface setting data ds is being output, the time t4 is reached. Here, the processor 2 switches the L signal from L to H. Here, the latch circuit 11 latches the data ds and enters the phase for latching the interface (I/F) setting data.

[0072] While this phase starts (t4) up to the time t5, the second embodiment of FIG. 3 functions. That is, at this time, the interface setting data ds, latched at the latch circuit 11, passes through the bus 42 and via the now on gated buffer circuit 21 and is looped back to the Di port of the processor 2 where the setting data ds is confirmed. At this time, the input gate unit 22 is off since a′=H.

[0073] Further, at the time t5, the inherent measurement control data dm is output from the processor 2, passes via the interface circuit 3, and is applied to the measurement controlled object 4.

[0074] The data dr from the object 4 responding to the data dm is input to the Di port of the processor 2 from the time t6.

[0075] FIG. 9 is a view of a fifth embodiment of the present invention.

[0076] In the fifth embodiment, all of the functions to be performed by the fourth embodiment (FIG. 5 and FIG. 6) are realized by digital processing by for example a CPU 51 provided on the interface board 8. Therefore, a signal line 52 is provided between the CPU 51 and the measurement control processor 2 and the commands, data, etc. for the various processing are serially transferred (or parallel transferred) over this signal line 52.

[0077] The processing performed by this serial transfer (or parallel transfer) include for example the following:

• • [0078] setting of the latch data
  • [0079] confirmation of the latch data
  • [0080] control of timing
  • [0081] transfer of commands
  • [0082] output of interface identification code

[0083] The main functions of the CPU 51 are as follows:

[0084] First, there is the interface setting function for activating only the interface circuit while prohibiting input of the interface setting data ds to the interface circuit unit 5 when the interface setting data ds is to be output. This is executed by the CPU 51.

[0085] Second, there is the loopback function for returning the interface setting data ds set by the interface setting function of the CPU to the input port Di of the measurement control processor 2. This loopback function is executed by the CPU 51.

[0086] Third, there is the identification code output function for sending a unique identification code set for each interface board carrying a plurality of types of interface circuits 3 thereon to the input port Di of the measurement control processor 2. This identification code output function is executed by the CPU 51.

[0087] In the above second to fifth embodiments, preferably an alarm is issued to the user at the time of abnormalities.

[0088] First, the measurement control processor 2 monitors whether the interface setting data which it output itself and the returned interface setting data match and issues an alarm when they do not match.

[0089] Second, the measurement control processor 2 monitors if the interface board corresponding to the sent identification code and the interface board which it set itself match and issues an alarm when they do not match.

[0090] The above alarm is given to the user by for example displaying “INTERFACE CIRCUIT SEQUENCE ABNORMALITY” on the screen of the PC.

[0091] More preferably, at the same time as the alarm is issued, the measurement control system comprised of the measurement controlled object 4 and the measurement control apparatus 1 are made to shift to the failsafe mode.

[0092] Several modes of this failsafe mechanism are given below:

• • [0093] The supply of power to the measurement controlled object 4 is immediately prohibited.
  • [0094] After detection of a mismatch, the measurement control apparatus 1 is locked and not restarted until reset.
  • [0095] The gated buffer circuits (12, 21, and 22) are all turned off and all input to the measurement controlled object 4 is prohibited.
  • [0096] The output from the Do port is made such content as shifting to the safe mode.

[0097] Summarizing the effects of the invention, as explained above, according to the present invention, by just adding the two signal lines for the S signal and L signal, the object of the present invention, that is, automatic selection of the interface circuit without error, is realized. In this case, even if there is an abnormality in the latch circuit or the interface board is erroneously selected, this can be discovered in advance and therefore will never lead to burnout of the ECU or other measurement controlled objects 4.

[0098] While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.