System and method for fast data encryption/decryption using time slot numbering

[0001] This invention relates to encryption and decryption in communication systems using spread spectrum PN coding techniques and, more particularly, to encryption/decryption systems using time division (TD) time slot numbering.

[0002] Time division multiple access (TDMA) is a communications system that divides a single frequency channel into short-duration time slots to enable multiple users to transmit on the same channel.

[0003] Hybrid TD—Spread Spectrum (SS) or TDMA-SS transmission systems employ a succession of short-duration PN encoded data bursts emanating from one or more communication stations.

[0004] Spread spectrum (SS) systems, which may be CDMA systems, are well known in the art. SS systems can employ a transmission technique in which a pseudo-noise (PN) PN-code is used as a modulating waveform to spread the signal energy over a bandwidth much greater than the signal information bandwidth. At the receiver the signal is de-spread using a synchronized replica of the PN-code.

[0005] In general, there are two basic types of SS systems: direct sequence spread spectrum systems (DSSS) and frequency hop spread spectrum systems (FHSS).

[0006] The DSSS systems spread the signal over a bandwidth f_RF±R_c, where f_RF represents the carrier frequency and R_c represents the PN-code chip rate, which in turn may be an integer multiple of the symbol rate R_s. Multiple access systems employ DSSS techniques when transmitting multiple channels over the same frequency bandwidth to multiple receivers, each receiver sharing a common PN code or having its own designated PN-code. Although each receiver receives the entire frequency bandwidth, only the signal with the receiver's matching PN-code will appear intelligible; the rest appears as noise that is easily filtered. These systems are well known in the art and will not be discussed further.

[0007] FHSS systems employ a PN-code sequence generated at the modulator that is used in conjunction with an m-ary frequency shift keying (FSK) modulation to shift the carrier frequency f_RF at a hopping rate R_h. A FHSS system divides the available bandwidth into N channels and hops between these channels according to the PN-code sequence. At each frequency hop time a PN generator feeds a frequency synthesizer a sequence of n chips that dictates one of 2n frequency positions. The receiver follows the same frequency hop pattern. FHSS systems are also well known in the art and need not be discussed further. In many situations using CDMA or TDMA-SS, particularly military situations, data communications are encrypted by the sender and decrypted by the receiver. Decryption by the receiver requires that the receiver have a decryption key. The key may be private or public.

[0008] One method of public-key encryption, developed by Rivest, Shamir & Adelman, and generally referred to as RSA, is based upon the use of two large prime numbers which fulfill the criteria for the “trap-door, one-way permutation.” Such a permutation function enables the sender to encrypt the message using a non-secret encryption key, but does not permit an eavesdropper to decrypt the message by crypto-analytic techniques.

[0009] As described in U.S. Pat. No. 4,354,982 to Miller et al., public-key encryption is useful for transmitting periodic changes in encryption keys on open channels. In the public-key encryption method, the need for a master encryption key in which to encrypt the periodic changes of the standard key is avoided. Thus, the need to transmit over a secure channel, or to physically transport the master key by courier or the like, is avoided. Without public-key encryption, each user must have the master key. Though the master key does not change often, as each new user comes on the data encryption line, a master key must be sent in some secure manner to that user. Each such transfer, even over a secure channel or by physical hand delivery, could be compromised, thus necessitating changing the master key for all users.

[0010] Public-key encryption enables the standard keys, which change periodically, to be sent over open channels to each user with a publicly known public-key, which though publicly known, is not capable of decryption by anyone other than the individual user.

[0011] Generally, the RSA public-key system has the following features. Assuming that the receiver of the message is located at terminal A, terminal A will have first computed two very large random prime numbers p, q. The product of p and q is then computed and constitutes the value n. A large random integer e is then selected which has the property that the greatest common divisor (GCD) of e, and the product of (p−1) and (q−1) is 1. Stated in equation form:
GCD[e,(p−1)(q−1)]=1  (Eq. 1A)
where: e is a large random integer which is relatively prime to the product of (p−1) and (q−1). An integer d is then computed which is the “multiplicative inverse” of e in modulo (p−1) (q−1):
e*d≡1[mod(p−1)(q−1)]  (Eq. 2A).

[0012] Terminal A transmits n and e to another terminal, e.g., Terminal B, in clear text without encryption, or a public list of n and e for every terminal, including Terminal A, is made publicly known. Terminal B responds by encrypting and transmitting a message M into an encrypted transmission C as follows:
C≡E(M)≡M^e (mod n)  (Eq. 3A).

[0013] Terminal B then sends the encrypted message C. Terminal A then performs an operation upon the received encoded message C as follows:
M=(C)^d (mod n)  (Eq. 4A)
Due to the properties of the selected large random prime numbers this “open trap-door, one-way permutation” results in the identical message M.

[0014] An interceptor who receives, or otherwise knows the publicly transmitted n and e, cannot easily decode the message sent by terminal B without the number d. Thus, the transmission from Terminal B to Terminal A is secure against decryption by unauthorized recipients.

[0015] However, as is known in the art, there exists factoring algorithms such as the Schroeppel algorithm, for factoring the number n. For an n of e.g., 50 digits in length, the Schroeppel algorithm can be used to factor n in 3.9 hours, on a large-scale digital computer.

[0016] It will be appreciated by those skilled in the art that message security is measured, or determined, by the amount of time it would take an unauthorized user to decrypt a message using techniques such as factoring. A one thousand year period in which to factor the value of n using factoring techniques is generally accepted as completely secure. It will be appreciated therefore, that the random numbers p and q must be extremely large. For the public-key system, the digit length of n is generally one hundred digits; and the corresponding digit length of p and q are each approximately sixty digits. It can be readily understood that generating random prime numbers sixty digits in length requires several hours on commercially available microprocessors.

[0017] It is therefore desirable to provide a fast encryption/decryption method and system whereby information may be encrypted/decrypted using public and/or master keys less susceptible to compromise but quickly determined by authorized or intended users.

[0018] The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.

[0019] In accordance with one embodiment of the present invention, a system for fast data encryption/decryption, is provided. The system includes a transmitter system having at least three transmitter pseudo-noise (PN) component code generators PN_x, PN_y, PN_z, wherein each transmitter PN component code generator is adapted to generate relatively prime transmitter PN component codes when compared with each of the other transmitter PN component codes. The transmitter also includes a first processor adapted to determine a time slot number (TSN) relative to at least two of the relatively prime transmitter PN component codes. Also included in the transmitter is an encryptor for encrypting clear data in accordance with the TSN.

[0020] The system includes a receiver system having a second processor adapted to determine the TSN; and a decryptor coupled to the second processor. The decryptor is adapted to decrypting the encrypted clear data in accordance with the TSN.

[0021] In accordance with another embodiment of the present invention a method for fast data decryption is provided. The method includes determining a time slot number (TSN), and decrypting encrypted data associated with the TSN. Decrypting further includes decrypting in accordance with the TSN.

[0022] The invention is also directed towards a method for fast data encryption. The method includes determining a time slot number (TSN) and encrypting clear data associated with the TSN and encrypting in accordance with the TSN.

[0023] In accordance with another embodiment of the present invention an integrated circuit (IC) is provided. The IC includes at least three transmitter pseudo-noise (PN) component code generators PN_x, PN_y, PN_z, wherein each transmitter PN component code generator is adapted to generate relatively prime transmitter PN component codes when compared with each of the other transmitter PN component codes. The IC also includes a first processor adapted to determine a time slot number (TSN) relative to at least two of the relatively prime transmitter PN component code and an encryptor for encrypting clear data in accordance with the TSN.

[0024] In accordance with another embodiment of the invention an integrated circuit (IC) is provided. The IC includes a processor adapted to determine a time slot number (TSN); and a decryptor adapted to decrypting encrypted clear data in accordance with the TSN and coupled to the second processor.

[0025] The invention is also directed towards a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for fast data decryption. The method includes determining a time slot number (TSN), wherein determining the TSN further includes determining a receiver PN composite code minor epoch, wherein the receiver PN composite code minor epoch consists of at least two receiver PN component code epochs. Determining the receiver PN composite code minor epoch further includes determining the receiver PN composite code minor epoch with sufficient lead time to identify the TSN associated with the encrypted data to be decrypted. The program storage device also includes instructions for determining a receiver TSN relative to determining the receiver PN composite code minor epoch; and decrypting encrypted data associated with the TSN relative to the receiver PN composite code, wherein decrypting further comprises decrypting in accordance with the TSN.

[0026] The invention is also directed towards a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a fast data encryption method. The method includes determining a time slot number (TSN), wherein determining the TSN includes determining a transmitter PN composite code minor epoch having at least two transmitter PN component code epochs. The method also includes determining a transmitter TSN relative to determining the transmitter PN composite code minor epoch; and encrypting in accordance with the TSN, clear data associated with the TSN.

[0035] As disclosed herein, the present invention describes a novel method and system for determining encryption/decryption keys.

[0036] In one embodiment of the present invention, a method is presented to determine the phase position of a pseudo noise composite (PN_c) code. The phase position is then correlated to a time slot position in a direct sequence, spread-spectrum (DSSS) signal for TDMA (Time Domain Multiple Access) operation. The time slot position is then used to generate an encryption or decryption key.

[0037] Referring to FIG. 5A there is shown a method flow chart implementing features of the present invention shown in FIGS. 1 and 2A (described in detail below). Referring to FIG. 5A, in a TDMA-SS system step 51a determines a Time Slot Number (TSN) corresponding to the transmitter's assigned time slot and relative to a minor epoch of the transmitter's local composite PNc code. Step 53a encrypts clear data according to the TSN and step 54a spreads the data according to the composite PNc spreading code. Step 56a sends or transmits the PNc encoded and encrypted data.

[0038] It should be noted that very time slot in a PN code from XYZ to XYZ epoch (assuming a three component PN code) is numbered. For example, if there are 7E6 time slots from XYZ to XYZ epoch, the time slots are numbered from 1 to 7E6, consecutively. In this invention testing is performed at minor epochs, such as at XY epochs, and time slot numbers do not repeat from 1–56 per XY epoch.

[0039] Still referring to FIG. 5A it can be seen that optional steps 52a and 55a correspond to a quasi-public key encryption method. Step 52a pre-selects two of the relatively prime PN component codes and step 55a encrypts clear data according to the two prime PN component codes and the TSN. It will be appreciated that in alternate embodiments the composite PNc code can have any suitable number of relatively prime PN component codes.

[0040] Referring to FIG. 5B, there is shown a method flow chart implementing features of the present invention shown in FIGS. 1 and 2B (described in detail below). Step 51b receives the PNc spread and encrypted data and step 53b phase aligns, either partially and/or fully, the received data with the receiver's locally generated composite PNc code. Step 52b determines the encrypted data's TSN relative to the minor epoch of the composite PNc code and step 55b decrypts the encrypted data according to the determined TSN.

[0041] Still referring to FIG. 5B, step 54b shows an alternate embodiment corresponding to the quasi-public key method described above; step 54b decrypts the data according to the TSN and the pre-selected PN component codes.

[0042] In this invention the transmitter TSN translator is adapted to translate the TSN to an integer variable e, where integer variable e is relatively prime to the product of (X−1)(Y−1), wherein X and Y are code lengths of the at least two of the relatively prime transmitter PN component codes, respectively; and where the encryptor is adapted to encrypt the clear data according to EC=(clear data)^e(mod (X*Y)), where EC is encrypted data. The transmitter TSN translator can include a TSN-to-e look-up-table or a TSN-to-e algorithm.

[0043] Referring to FIG. 1, there is shown a pictorial diagram of a telecommunications system incorporating features of the present invention. Although the present invention will be described with reference to the embodiments shown in the drawings, it should be understood that the present invention might be embodied in many alternate forms of embodiments, e.g., point-to-point simplex links, point-to-multipoint links, and either simplex or full-duplex links. In addition, it should be understood that the teachings herein may apply to any group or assembly of spread spectrum (SS) or time domain—spread spectrum (TD-SS) receivers, including those that are fixed in place; vehicle mounted; and/or hand carried.

[0044] Still referring to FIG. 1, there is shown a full-duplex system 10 that is suitable for practicing this invention. Specifically, the system 10 employs direct sequence spread spectrum based techniques over an air link to provide data transfer between Terminal #1 12 and Terminal #2 14. The forward link (FL) from Terminal #1 12 to Terminal #2 14 contains a spread spectrum waveform that is constructed in the manner described herein, with the PN code being composed of relatively prime length codes. In a similar manner, the return link (RL) from Terminal #2 14 to Terminal #1 12 contains a spread spectrum waveform that is similar or identical to that of the FL.

[0045] Terminal #1 12 includes a Spread Spectrum Modulator (SSM) 12b; the SSM 12b generates a desired spread spectrum waveform at a desired RF frequency. The SSM 12b also provides a Tx clock 12d that is used to clock the Tx Data 12e into the SSM 12b. The SSM 12b then combines the Tx data 12e with a spread spectrum PN code to produce the desired spread spectrum waveform. Terminal #1 12 also includes an antenna 12a, which may transmit at any suitable RF frequency. Terminal #1 12 also includes a modulator/demodulator controller (MDC) 12c5 and module 2a1 for encrypting clear data in accordance with the teachings of the present invention.

[0046] The signal generated by Terminal #1 12 and transmitted by antenna 12a via the FL is received by Terminal #2 14 via antenna 14a to receiver 14c. Receiver 14c includes a spread spectrum correlator 14c1, PN generator 14c2, clock generator 14c3, and spread spectrum demodulator (SSD) 14c4. The received signal is then demodulated by SSD 14c4. Once the signal is acquired and the receiver 14c is tracking the received signal, the Rx Clock 14g and Rx Data 14f are output to the intended user. It will be appreciated that the data clocks 14g and 12d are synchronous and may be commanded to change frequency on the PN epochs; thus advantageously providing means to vary the data rate without interruption; and without the need for bit synchronizers to acquire and track at the new clock frequency with their associated loss of clock coherence between the transmitter and receiver.

[0047] Similarly, Terminal #2 14 generates a Tx Clock 14d and Tx Data 14e using the Spread Spectrum Modulator 14b in a similar fashion described earlier for Terminal #1. Likewise, Terminal #1 12 may receive the RL signal via antenna 12a, and demodulate and track the signal as described earlier with receiver 12c to provide Rx Data 12f and Rx Clock 12g to the intended user. Terminal #2 14 also includes a modulator/demodulator controller (MDC) 14c5 and module 2b1 for decrypting encrypted data in accordance with the teachings of the present invention.

[0048] In a preferred embodiment of this invention a composite PN code PNc contains PN component codes, each component code being relatively prime with respect to the other component codes. In other words, each of the PN component codes does not share any prime multiplicands with either of its companion PN component codes. For purposes of example only, consider three component codes of one digit each: X, Y, and Z; where Length (L) L_x=5 chips, L_y=7 chips, and L_z=9 chips. It can be seen that the numbers 5 and 7 are prime numbers, and the number 9 is derived from the prime number 3, meaning that the numbers 9, 5 or 7 do not share any prime multiplicands. It will be appreciated that in alternate embodiments the PN component codes can be any suitable number of digits.

[0049] The epoch of a PN component code occurs once per the length of the component code, and the epoch is customarily recognized as the all-ones state of the PN component code generator. In accordance with features of the present invention, the major epoch of a composite PN_C code occurs once per the length of the composite code (L_x×L_y×L_z=L_xyz) and is recognized as the simultaneous occurrence of the all-ones state of each component code.

[0050] The composite PN code includes three or more relatively prime component codes of lengths: X, Y, Z (in this non-limiting example). In the preferred embodiment, an integer number of time slots are chosen for an XY epoch: in units of Time-Slots/(L_xL_y chips). Each time slot is assigned a unique, Time Slot Number (TSN) from the beginning of the component code (the XYZ epoch). Time Slot Numbers may be consecutive counting numbers, beginning with 1 and ending with n, or may use any suitable method for uniquely identifying the Time Slot. It will also be appreciated that the invention presented herein may be used with any suitable PN composite encoded system. For example, a particular PN composite code phase position, or consecutive PN composite code phase positions, may be used to uniquely identify a particular phase segment of the PN composite code.

[0051] Referring to FIG. 2a there is shown an encryption system incorporating features of the present invention shown in FIG. 1. Discrete Digital Synthesizer (DDS) 2a71, driven by reference oscillator 2a6, drives PN code generator 2a72 to generate component PN codes PNx, PNy, and PNz. In alternate embodiments, any suitable number of component codes may be used. Logic combiner 2a8 combines the component codes to form the composite PNc code used by modulator 12b for spreading data. In embodiments where four PN component codes are used, the component codes may be MAND combined according to:
(X⊕(Y·(Z₁⊕Z₂)),
or MAJ combined according to:
(X·Y)⊕(X·Z₁)⊕(X·Z₂)⊕(Y·Z₁)⊕(Y·Z₂)⊕(Z₁·Z₂)

[0052] The modulator/demodulator controller (MDC) 12c5 manages PN code modulation and demodulation, measures time since initialization (TSI) of the PN codes by counting cycles of the reference oscillator 2a6 from which the PN chipping rates are mathematically derived by DDS (direct digital synthesizer) 2a71, and tracks PN code phase by counting the actual number of chips produced, and by recording intentional PN code slips and advances (delta phase).

[0053] The LCP 2a4 requests and receives timely TSI and PN code delta phase information from the MDC 12c5. The LCP 2a4 uses MDC status to statically correct its internal clock count to reflect the MDC's TSI, converted to units of LCP time, since, in practice, the LCP clock (not shown) is inferior to the MDC's internal oscillator. Aided by this MDC status, the LCP's clock keeps track of composite PN code phase in units of time since the beginning of the code (TOC, time of code). Continuously tracking TOC, the LCP 2a4 calculates the TOC for the next-occurring XY epoch and the time slot number (TSN) of the time slot that begins at the XY epoch. The LCP 2a4 is programmed to interrupt its processes at the TOC of the next occurring XY epoch minus a programmable amount of lead-time that allows time in which the LCP can communicate with the FEC Module 2a1 prior to the actual occurrence of the XY epoch. At the interrupt, the LCP 2a4 communicates to the FEC Module 2a1 the TSN of the time slot that begins at the next XY epoch.

[0054] The FEC Module 2a1 receives a symbol clock and an XY epoch clock from the MDC 12c5 and determines time slot boundaries by counting symbol clocks. At the LCP interrupt, it receives notification of the TSN of the time slot that begins at the next XY epoch, and generates the appropriate time slot number (TSN) for the time slot that begins with the next XY epoch, and continues to generate the appropriate TSN for each consecutive time slot.

[0055] In a quasi-public key embodiment the unique TSN may be used to equate the public key variable e (described above) to a predetermined, large random integer, relatively prime to the product of (X−1)*(Y−1) (where X and Y are the prime numbers representing PNx and PNy code lengths, respectively). It will be appreciated that any suitable method for equating the TSN to e may be used. For example, and as was noted above, the unique time slot identifier may be used as a pointer to a look-up-table of “e” values, or similar to the master key embodiment, as a seed value to a predetermined algorithm for generating “e” values. It will be appreciated that this embodiment has advantages of a public key system but is less susceptible to decryption by factoring the variable n. Indeed, the present invention advantageously allows the sender to dynamically encrypt time slot(s), where each time slot has a typical duration of milliseconds, with a different encryption key. For example, a one second stream of data from a user may be encrypted with one thousand different encryption keys; making interception and decryption by non-intended recipients extremely difficult.

[0056] Once the receiver 14 receives the broadcast signal from the transmitter 12, the receiver 14 uses PN code phase information received from the transmitter, and its own PN code phase information to slip or advance its transmit PN code phase to match the PN code phase of the transmitter. Since the receiver 14 initializes its PN code at any time before or after the transmitter initializes its PN code, the resulting PN phase difference between the transmitter and receiver is potentially large. Also, the corresponding receiver 14 LCP-generated TSN will not agree with the transmitter's 12 TSN until the PN code phase of the transmitter 12 is matched to the PN code phase of the receiver 14.

[0057] In terms of quantities measured by the MDC 14c5 or 12c5, composite PN code phase is given as follows:
θ_PN=TSI_→Chips+Δθ_PN=TSI_→Chips+Δθ_XYZ+ΔΣθ  (Eq. 1)

[0058] Equation 1 shows that composite PN code phase θ_PN, in chips, is equal to TSI of the PN code, converted into chips, plus delta phase Δθ_PN. If the PN code were free running (i.e., based only on the reference oscillator), the composite PN code phase would exactly equal the TSI, converted into chips; in a free-running system, an exact ratio exists of chips per TSI LSBs (least significant bits). For example, if TSI is a count of 10 MHz reference oscillator cycles, and chips are counted in finer increments of the master clock called sampling clocks. Therefore, there are n₁ sampling clocks per chip (SCPC): 1, 2, 4, or an integer number.

[0059] At the beginning of each time slot, a receiving demodulator 12c4 searches through a given PN code uncertainty to correlate its PN code phase with the PN code phase of the transmitting platform 14 assigned to the time slot. In addition, the receiver 12 accumulates PN code phase while it is demodulating a signal from the transmitting platform 14 having a clock 14c3 whose rate is not exactly equal to the receiver's reference clock 12c3. A receiver's demodulator 12c4 also accumulates some additional PN code phase difference because the signal from the transmitting platform 14 may not have compensated at all, or compensated imperfectly, for the Doppler effect.

[0060] As indicated in Equation 1, delta phase also includes intentional PN code slips or advances, Δθ_xyz.

[0061] If more or less chips are modulated or demodulated per unit of time than would have been had they been modulated or demodulated at the free-running rate of the respective reference oscillator, these chips are considered as accumulated delta phase or accumulated in an amount greater than or less than the free-running amount. Accumulated delta phase is calculated by the MDC 14c5 and 12c5, using Equation 2.
#SCLK_→Chips=TSI_{→Chips via exact conversion}+ΔΣθ  (Eq. 2)

[0062] MDC 14c5 and 12c5 latch their count of sampling clocks and TSI at the same instant that the TSI LSB increments. There is an exact relationship between TSI and the number of sampling clocks that should have occurred during the latched TSI. The difference between the number of chips that ideally occurs during the latched TSI and the actual number of sampling clocks counted, converted into chips, is equal to accumulated delta phase, ΔΣθ. For purposes of this invention description, the symbol Δ (delta) is used to indicate delta or difference, Σ (sigma) is used to indicate addition or accumulation, and θ (theta) is used to indicate phase.

[0063] The following numerical example is for purposes of illustration only and is not intended to limit the scope of the invention. The LCP 2b4 (see FIG. 2B) measures time in 0.4096 ms LSBs, and composite PN code phase, θ_PN, is then measured, for time slot counting purposes, in units of 0.4096 ms LSBs. In other words, delta phase is expressed in terms of 0.4096 ms LSBs, and an exact conversion between sampling clocks and 0.4096 ms LSBs (referred to hereafter as TOC_LSBs) is derived.

Sampling Clock to TOC_LSB Conversion Factor:

[0064] A more exact conversion between delta phase, in terms of sampling clocks, and TOC_LSBs, is given in Equation 3. The LCP 2b4 obtains (from the MDC 14c5) the status of delta phase in units of sampling clocks (not shown) and the numerical value of sample rate (samp_rate), and uses Equation 3 to convert delta phase into units of TOC_LSBs.

[0065] $\begin{array}{cc}\Delta {\theta }_{\mathrm{PN}}\left(\mathrm{TOC\_LSBs}\right)=\Delta {\theta }_{\mathrm{PN}}\left(\text{Sampling}\text{Clocks}\right)\times \frac{2^{15}}{\text{Sample}\text{Rate}\times 3}& (\text{Eq. 3)}\end{array}$

[0066] Sample Rate is the seed word used by the DDS 2b71, in units of DDS LSBs, to mathematically generate a master clock rate from the 10 MHz reference oscillator. The multiply-and-divide ratio of the DDS 2b71 used by the HRDD 14c4 is reflected in Equations 3 and 4. The numerical value of the of Sample Rate for the present example is calculated, using Equation 4, given the referenced DDS 2b71.

[0067] $\begin{array}{cc}\text{Sample Rate(Master Clock Rate, sampling clocks per second)}=\text{Chipping Rate}\times \frac{2^{20}}{3\times 5^7}\times \mathrm{SCPC}& \text{(Eq. 4)}\end{array}$

[0068] In general, Delta phase is a slowly changing quantity. For example, at 550 Knots each, the Doppler effect between two moving platforms changes slowly in terms of TOC_LSBs accumulated per XY epoch. It will be appreciated that intentional slips and advances of hundreds or thousands of chips used during the acquisition of a TDMA time slot are also small compared to TOC_LSBs.

[0069] The broadcast receiver LCP 2b4 uses delta phase status from its MDC 14c5 in order to calculate the PN code slip or advance needed to align the receiver's PN composite code phase with the transmitter's free-running PN composite code phase. In general, the receiver's MDC 14c5 reports that it has achieved its Track State when the Broadcast Link is acquired. The Track State is achieved almost immediately upon accomplishing PN Detect and can be reported immediately, but Delta Phase information takes some time to gather, and the Delta Phase information reported along with the first indication of Track State may not actually represent the delta phase associated with the Track State. Therefore, in order to avoid ambiguity, the LCP 2b4 waits for the MDC 14c5 status packet that follows the first report of Track State and uses the Delta Phase status from this packet for its calculation. Similarly, the LCP 2b4 preferably verifies that its MDC 14c5 has slipped or advanced its TDMA-link delta phase by the LCP-commanded amount, which places the received PN code phase in the center of the receiver's demodulator PN code phase uncertainty, before the LCP 2b4 uses the MDC's delta phase in LCP Time Slot Numbering equations.

Correcting TSI_LCP to TSI_MDC:

[0070] Referring to FIG. 3, there is shown a block diagram illustrating one method by which the LCP 2b4 updates its TOC correction term. Using Equation 3 the LCP 2b4 calculates the delta phase portion of composite PN code phase, the latter part of Equation 1, but in order for the LCP 2b4 to complete the calculation of TOC, the LCP 2b4 receives the MDC's TSI (in the above example, LSB=25.6 microseconds, which divided by 16 becomes compatible with 0.4096 ms units), step 32, and the LCP develops a correction factor, step 33, to correct its own TSI to agree with the MDC's TSI. Step 34's 3.4 seconds represents any appropriate integration time−the time in which the LCP clock drifts away from the MDC clock by an LSB, or some suitable unit of time. The TOC is then determined by:

[0071] $\begin{array}{cc}\mathrm{TOC}\left(0.4096\mathrm{ms}\mathrm{LSBs}\right)=\mathrm{TSI\_LCP}\mathrm{\_instantaneous}+\text{Correction}+\Delta {\theta }_{\mathrm{PN}}\times \frac{2^{15}}{\text{Sample Rate}\times 3}& \text{(Eq. 5)}\end{array}$
It can be seen that Equation 3 has been incorporated into Equation 5 as the last term. The LCP 2b4 latches its free-running, instantaneous TSI_LCP and uses Equation 5 to calculate TOC, which is the composite PN code phase expressed in 0.4096 ms LSBs.

[0072] With regard now to calculating an LCP interrupt, it should be remembered that time slot numbering is being done at the transmitter (encryptor) and at the receiver (decryptor). The LCP interrupt is by what the LCP 2b4 communicates the TSN to the FEC Modules 2a1 and 2b1, respectively. In order to calculate an LCP interrupt, a conversion factor is used to convert between TOC_LSBs and XY epochs. The conversion factor is provided in Equation 6:

[0073] $\begin{array}{cc}\mathrm{TOC\_LBS}\text{to}\mathrm{XY}\text{Epoch Conversion Factor}=\frac{2^{15}·L_X·L_Y·\mathrm{SCPC}}{\text{Sample Rate}·3}\frac{\mathrm{TOC\_LSBs}}{\mathrm{XY}\text{Epoch}}& \text{(Eq. 6)}\end{array}$
It can be seen that Equation 6 incorporates Equation 3's sampling clock to TOC_LSB exact conversion factor times the number of sampling clocks per XY epoch, which is the length of the X code in chips, L_X, times the length of the Y code in chips, L_Y, times SCPC, sampling clocks per chip. The number of the next-occurring XY epoch is given in Equation 7.

[0074] $\begin{array}{cc}\text{Next }\mathrm{XY}\text{Epoch}=\mathrm{XYE}=\mathrm{IP}\left[\mathrm{TOC}\times \frac{\text{Samlpe Rate}\times 3}{\mathrm{SCPC}·2^{15}·L_X·L_Y}\right]+1& \text{(Eq. 7)}\end{array}$

[0075] Equation 7 is an intermediate equation that leads to the calculation of the interrupt. It can be seen in Equation 7 that the LCP's 2b4 and 2a4 instantaneous TOC times the XY epoch per TOC_LSB conversion factor of Equation 6 is the current composite PN code phase in terms of an integer plus fractional number of XY epochs. The integer portion is the number of the last XY epoch that occurred, and adding 1 to that number is the number of the next XY epoch to occur.

[0076] The number of the next XY epoch to occur is used to calculate the number of the time slot that immediately precedes the next-occurring XY epoch, as shown in Equation 8.
Time Slot Number of Slot That Begins at the Next XY Epoch=TSN_—XY=XYE×TSPXYE+1  (Eq. 8)
Interrupt time is calculated as shown in Equation 9.

[0077] $\begin{array}{cc}\text{Interrupt Time}\left(\mathrm{TOC\_LSBs}\right)=\mathrm{XYE}\times \frac{\mathrm{SCPC}·2^{15}·L_X·L_Y}{\text{Sample Rate}\times 3}-\text{Lead Time}\left(0.4096\mathrm{ms}\mathrm{LSBs}\right)+11& \text{(Eq. 9)}\end{array}$

[0078] In a preferred embodiment, the LCP 2b1/2a1 checks its instantaneous TOC approximately once per millisecond to determine if TOC is equal to or greater than the interrupt time. If it is, the interrupt is serviced. The lead-time term of Equation 9 is the amount of time that the interrupt should preferably occur prior to the XY epoch.

[0079] It will be appreciated that TOC and interrupt uncertainties may be accounted for by adding TOC_LSBs to the interrupt time of Equation 9, see FIG. 4. Step 41 determines the interrupt time to be tested by step 42 to determine if sufficient time is available for the interrupt activities to be completed. The interrupt activity of concern, principally, is for the encryptor or decryptor to receive the LCP's TSN and make corrections as necessary. If there is not sufficient time then LCP 2b4/2a4 adds, step 43, an XY number of TOC_LSBs to its interrupt time (TOC_LSBs per XY Epoch=Equation 6), which has the effect of waiting for another XY epoch to perform the interrupt. In a preferred embodiment the LCP 2b4/2a4 leaves sufficient lead time prior to the next XY epoch.

[0080] The following example is for purposes of illustration only and is not intended to limit the scope of the invention. LCP 2b4/2a4 is provided an indication of an XY epoch from logic combiner 2b8/2a8. It will be appreciated that in alternate embodiments the XY epoch indication may be provided by any suitable circuitry, such as the MDC 14c5/12c5. It will be further appreciated that indication of the XY epoch may be provided by any suitable means such as a discrete, hardwired, logic signal, a register, or a memory device.

[0081] Referring to FIG. 6 there is shown a pictorial timing diagram of an example illustrating features of the present invention shown in FIGS. 1, 2A, & 2B. In this example the FEC 2b1/2a1 reports the TSN of the time slot immediately previous to an XY epoch, and that epoch number is reported for fifty-six time slots, as shown. The first time slot following an XY epoch is identified as Time Slot A, and the second time slot following the XY epoch is identified as Time Slot B. Further the LCP is informed of the XY epoch at the time of the XY epoch's occurrence. Stated differently, the LCP (2a4, 2b4) acknowledges the XY epoch and performs Time Slot Numbering during Time Slot A.

[0082] The TSN during time slot A is given by the following:
TSN reported=56*IP((TOC+5)*(Sample_Rate*3)/(SCPC*2*Lx*Ly)  (Eq. 10).

[0083] During Time Slot A, if the reported TSN does not agrees with an LCP's result of Eq. 10, then the LCP adds two to the result of Eq. 10, supplies the now modified result to FEC and sets a status flag (not shown) alerting the FEC that the modified result is the TSN to be applied as TSN of Time Slot B.

[0084] In Eq. 10, 5 LSBs of 0.4096 msec are added to TOC in order to account for the case of zero latency in the Correction term and in order to account for TSI sampling granularity and uncertainty. Adding 5 LSBs, in this example, helps to ensure a TOC reported PN code phase that exceeds the XY epoch by a couple of milliseconds in order for TOC to report the PN code phase equal to or slightly greater than the PN code phase of the XY epoch.

[0085] Once the receiver TSN is determined, the TSN may be used to generate a master decryption key by indexing a look-up table, or seeding a master key algorithm, as described above (the same operation is occurring at the transmitter's encryptor as well). It will be appreciated that such a dynamic distribution approach obviates the need for distributing the master key before a particular user may need it.

[0086] It will be further appreciated that using PN component code lengths Lx and Ly obviates the time consuming step of the public key method (described above) where p and q values are randomly generated and tested. In alternate embodiments, any two relatively prime PN component code lengths may be used to encrypt and decrypt clear data. For example, a PN composite code having four PN components (e.g., PNx, PNy, PNz₁ and PNz₂), PNz₁ and PNz₂ could be used in place of the p and q variables described above.

[0087] It is also understood that extended float arithmetic is suitable to accommodate the methods presented above. The equations have been tested using 64 bit binary arithmetic, rounded to 55 mantissa bits and the respective power of ten at each intermediate product. However, it is understood that any suitable arithmetic techniques may be used.

[0088] In addition, in alternate embodiments the TSN generator may be a programmable device such as an integrated circuit (IC). It will be further appreciated that the IC may be a field programmable gate array (FPGA), an application specific IC (ASIC), or a function of MDC firmware. The operation of the ICs or firmware may be defined by a suitable programming language such as a Very High Speed Integrated Circuit (VHSIC) Hardware Description (VHDL) Language file. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances that fall within the scope of the appended claims.