DC-DC converter and converter device

[0001] 1. Field of the Invention

[0002] The present invention relates to a DC—DC converter for down converting an input DC voltage to a fixed value DC voltage, that is, a ripple detection self-oscillating step-down converter and a converter device having a plurality of connected stand-alone converters.

[0003] 2. Description of the Related Art

[0004] Presently, low voltage and large current DC—DC converters are required due to the demand for power supply circuits in computers, etc. PWM controlled converters and ripple detection type self-oscillators (hereinafter simply referred to as ripple converters) representing such DC—DC converters are used. Since the response to load change is excellent, ripple converters, used since before the later developed PWM controlled converters, are being paid attention to once again.

[0005] FIG. 12 is a circuit diagram showing the basic circuit of a ripple converter.

[0006] As shown in FIG. 12, the ripple converter contains a PNP transistor Tr₁ as a switching element and an inductor L₀₁ connected in series between an input terminal 3, to which an input voltage Vin is input, and an output terminal 4 from which an output voltage Vout is output. The ripple converter also contains a flywheel diode D₀₁ connected between the ground (and the ground terminal 5) and the connection point of the PNP transistor Tr₁ and the inductor L₀₁. Furthermore, a voltage in accordance with the output voltage Vout is input to the non-inverting input terminal, a reference voltage Vo is input to the inverting input terminal, and a comparator 10 outputting a switching control signal to the PNP transistor Tr₁ is provided.

[0007] In such a ripple converter, when the PNP transistor Tr₁ is in the off state and the output voltage Vout becomes lower than the reference voltage Vo, a Low signal is output from the comparator and input to the base of the PNP transistor Tr₁, and then, the PNP transistor Tr₁ is turned on. Then, when the PNP transistor Tr₁ is turned on, the output voltage Vout increases. On the other hand, when the PNP transistor Tr₁ is in the on state and the output voltage Vout becomes higher than the reference voltage Vo, a High signal is output from the comparator and input to the base of the PNP transistor Tr₁, and then, the PNP transistor Tr₁ is turned off. Then, since the PNP transistor Tr₁ is turned off, the output voltage Vout decreases. By repeating such a control, the output voltage Vout goes up and down around a voltage close to the reference voltage Vo and an output voltage Vout substantially equal to the reference voltage Vo is obtained.

[0008] FIG. 13 shows the output voltage waveform of a related ripple converter.

[0009] As shown in FIG. 13, the output voltage Vout becomes a triangular waveform having a ripple in which the voltage (amplitude) goes up and down from a set voltage Vset, as a reference, on the basis of the reference voltage Vo. Then, in normal operation, the average voltage of the output voltage Vout is substantially in the middle between the maximum voltage and the minimum voltage in the waveform.

[0010] As a practical circuit of such a ripple converter, Japanese Unexamined Patent Application Publication No. 9-51672 discloses a ripple converter in which a switching element of a P-type FET and a choke coil are connected between an input terminal and an output terminal and a diode is connected between the ground potential and the connection point of the p-type FET and the choke coil. Furthermore, the ripple converter contains a comparator in which a voltage in accordance with the output voltage is input to the inverting input terminal and a reference voltage is input to the non-inverting input terminal and a driver IC outputting a switching control signal to the p-type FET in accordance with the output voltage of the comparator. Then, in this ripple converter, a desired output voltage is obtained from a fixed input voltage in such a way that the output voltage is compared with the reference voltage and the P-type FET is switched on the basis of the comparative result.

[0011] Now, in the related ripple converter in which the output voltage Vout is controlled so as to be constant, when the switching control is continuously performed, the duty factor, which is the ratio of the on time to the total of the on time and off time of a switching element such as an FET, etc., is dependent on the input voltage Vin. Or in a ripple converter in which the input voltage Vin is constant and the output voltage Vout changes according to the set condition, the duty factor is dependent on the output voltage Vout.

[0012] In the related ripple converter, there has been a problem in that, when the duty factor changes, the output voltage varies. Hereinafter, the principle is described.

[0013] FIG. 14 shows the waveform of the instantaneous value of the output voltage Vout, the average value Vavg, the set voltage Vset (dependent on the reference voltage Vo), and the on and off state of the switching element in the case where the input voltage is high. Furthermore, FIG. 15 shows the waveform of the instantaneous value of the output voltage Vout, the average value Vavg, the set voltage Vset (dependent on the reference voltage Vo), and the on and off state of the switching element in the case where the input voltage is low.

[0014] In the above-described ripple converter, when the instantaneous value of the output voltage Vout exceeds the set voltage Vset, the switching element is turned off. The time from the point where the instantaneous value of the output voltage Vout exceeds the set voltage Vset to the point where the switching element is turned off, that is, the time (t1 in the drawing) from the point where the instantaneous value of the output voltage Vout exceeds the set voltage Vset to the point where the instantaneous value becomes the maximum is decided by the circuit construction of the ripple converter, and not decided by the input voltage Vin, and accordingly, the time is basically the same.

[0015] Therefore, as shown in FIG. 14, when the input voltage Vin is high, since the slope of the increase in the output voltage Vout becomes steep, the maximum value of the output voltage Vout becomes high in accordance with the input voltage Vin. Here, since the rate at which the output voltage decreases is constant regardless of the input voltage, the time during which the instantaneous value of the output voltage Vo decreases from the maximum to the set voltage Vset becomes longer as the input voltage Vin increases.

[0016] On the other hand, the time from the point where the instantaneous value of the output voltage Vout goes below the set voltage Vset to the point where the instantaneous value becomes the minimum, that is, the time (t2 in the drawing) from the point where the instantaneous value of the output voltage Vout goes below the set voltage Vset to the point where the switching element is turned on is the same (does not change) regardless of the input voltage Vin. Accordingly, the minimum value of the output voltage Vout is constant regardless of the input voltage Vin. Moreover, the time from the point where the instantaneous value of the output voltage Vout becomes the minimum to the point where the instantaneous value returns to the set voltage Vset becomes shorter as the input voltage Vin increases because of the increasing amount of change of the voltage. Accordingly, the time during which the switching element is in the on state becomes shorter than the total of the time during which the switching element is in the on state and the time during which the switching element is in the off state. That is, the duty factor of the switching element becomes smaller. In this way, when the duty factor of the switching element becomes smaller, although the off time of the switching element, that is, the time during which the switching element is in the off state becomes longer, since the time during which the instantaneous value of the output voltage Vout is lower than the set voltage Vset in the off time is constant regardless of the input voltage Vin. Accordingly, when the input voltage Vin increases, as shown in FIG. 14, the time during which the instantaneous value of the output voltage Vout is higher than the set voltage Vset becomes longer. Because of this, the output voltage average value Vavg which is the time-average of the instantaneous value of the output voltage Vout becomes higher than the set voltage Vset.

[0017] Furthermore, as shown in FIG. 15, when the input voltage Vin is low, after the switching element has been turned on, a voltage transmitted to the output terminal Vout is also reduced in accordance with the input voltage Vin. Here, since the rate at which the output voltage Vout is lowered is constant regardless of the input voltage Vin, the time during which the instantaneous value of the output voltage Vout decreases from the maximum value to the set voltage Vset is more reduced as the input voltage Vin decreases.

[0018] On the other hand, the time from the point where the instantaneous value of the output voltage Vout goes below the set voltage Vset to the point where the instantaneous value becomes the minimum value, that is, the time (t2 in the drawing) from the point where the instantaneous value of the output voltage Vout goes below the set voltage Vset to the point where the switching element is turned on is also the same regardless of the input voltage Vin. Moreover, the time from the point where the instantaneous value of the output voltage Vout becomes the minimum to the point where the instantaneous value returns to the set voltage Vset becomes longer because the amount of change of the voltage is more reduced as the input voltage Vin decreases. Accordingly, the time during which the switching element is in the on state becomes longer to the total of the time during which the switching element is in the on state and the time during which the switching element is in the off state. That is, the duty factor of the switching element becomes larger. In this way, when the duty factor of the switching element becomes large, the on time of the switching element becomes long. However, in the on time, since the time during which the instantaneous value of the output voltage Vout is higher than the set voltage Vset is constant regardless of the input voltage Vin, when the input voltage Vin decreases, as shown in FIG. 15, the time during which the instantaneous value of the output voltage Vout is lower than the set voltage Vset becomes longer. Therefore, the output voltage average value Vavg, which is the time average of the instantaneous value of the output voltage Vout, becomes lower than the set voltage Vset.

[0019] Thus, when the related ripple converter is used, the average value of the output voltage Vout varies dependent on the value of the switching duty factor.

[0020] Furthermore, when ripple converters of the above-described construction are operated in parallel, the output terminals of the ripple converters in parallel operation are connected in parallel. But, as described above, the output voltage of each ripple converter is not constant due to the input voltage value and other factors. Accordingly, there is a possibility that a ripple converter having a high output voltage may adversely affect the operation of other converters. However, since the ripple converters do not contain a current detection mechanism, it is difficult to make uniform the load current of each ripple converter in parallel operation. Therefore, it is difficult to perform stable parallel operation of the ripple converters.

[0021] In order to overcome the problems described above, preferred embodiments of the present invention provide a ripple converter type DC—DC converter in which a fixed output voltage can be stably obtained without being affected by the value of a switching duty factor or without being affected by the change of an output voltage set value.

[0022] Furthermore, preferred embodiments of the present invention provide a converter device in which the operation of each ripple converter is stabilized when a plurality of ripple converter type DC—DC converters are operated in parallel.

[0023] A DC—DC converter of a preferred embodiment of the present invention includes an N-type FET for on and off controlling an input voltage, a smoothing circuit for smoothing a voltage output from the N-type FET and outputting the smoothed voltage, and a comparator circuit for outputting a switching control signal for the on and off controlling by comparing a voltage output from the smoothing circuit with a set voltage. In the DC—DC converter, the comparator circuit outputs the switching control signal by detecting the time average value of the voltage output from the smoothing circuit, comparing the detected time average value with the set voltage, and comparing a correction set voltage obtained on the basis of the comparative result with the voltage output from the smoothing circuit.

[0024] The comparator circuit corrects the set voltage (reference voltage) by a voltage in accordance with the difference between the output voltage time average and the set voltage (reference voltage) output from a constant-voltage power supply. At this time, for example, when the output voltage is high, the set voltage is corrected to be low, and, when the output voltage is low, the set voltage is corrected to be high. Then, the comparator circuit outputs a switching control signal for on and off controlling the N-type FET by comparing the output voltage and the corrected set voltage.

[0025] Furthermore, in a DC—DC converter of a preferred embodiment of the present invention, the comparator circuit includes a reference power supply generating a reference voltage in accordance with the set voltage, a divider circuit generating a comparative voltage by dividing the reference voltage, and a correction voltage generation circuit generating a correction voltage from the comparative voltage and the time average value of the voltage output from the smoothing circuit, and the correction set voltage is generated by applying the output from the correction voltage generation circuit to the generation point of the comparative voltage through a resistor.

[0026] In this construction, a comparative voltage is provided in the divider circuit by using a reference voltage generated from one reference voltage power supply, and a correction voltage for correcting the comparative voltage in accordance with the reference voltage is provided by comparing the comparative voltage with a voltage time average value in accordance with the output voltage. Then, a correction set voltage of the comparative voltage corrected by the correction voltage is compared with a voltage in accordance with the output voltage and a switching control signal in accordance with the comparative result is output by the comparator circuit.

[0027] Furthermore, a converter device of a preferred embodiment includes a plurality of DC—DC converters. In the converter device, the output terminals of the plurality of DC—DC converters are connected in parallel, and a switching control signal common to all the DC—DC converters connected in parallel is generated by using the logical sum or logical product of the outputs of the comparator circuits of the plurality of DC—DC converters.

[0028] In this construction, when the logical sum or logical product of the outputs of the comparator circuits of the converters connected in parallel is used, even if the switching control signal output from the comparator of all the converters is not the same, the switching control signal is unified to a switching control signal output from one of the comparator circuits. Accordingly, the N-type FET of all the converters connected in parallel is controlled by the same switching control signal.

[0029] Furthermore, in a converter device of a preferred embodiment of the present invention, the output portion of the comparator circuit of each DC—DC converter is of an open collector type or open drain type and these output portions are connected to each other.

[0030] In this construction, the output of the comparator circuit is of an open collector type or open drain type and the construction of the DC—DC converter in parallel connection becomes easy by connecting the outputs of the comparator circuits in parallel.

[0031] According to a preferred embodiment of the present invention, the set voltage is corrected in accordance with the value of a switching duty factor in such a way that the output voltage time average is detected and the set voltage is corrected by a voltage in accordance with the difference between the output voltage time average and the set voltage. Thus, a DC—DC converter for obtaining a stable output voltage can be constructed without being affected by the value of a switching duty factor. Moreover, by making use of the effect, a DC—DC converter for obtaining a stable output voltage can be constructed even if the set value of the output voltage changes.

[0032] Furthermore, according to a preferred embodiment of the present invention, a reference voltage formed from one reference power supply is divided, the divided reference voltage is used for correction of the set voltage, the divider voltage of the reference voltage is corrected by the correction result, and the correction reference voltage is compared with a voltage in accordance with the output voltage. Accordingly, the correction of the set voltage is stabilized. Thus, a DC—DC converter for obtaining a stable output voltage can be constructed.

[0033] Furthermore, according to a preferred embodiment of the present invention, since all the converters connected in parallel are controlled by the same switching control signal, the output current of all the converters becomes constant. That is, a converter device having a stable load current can be constructed.

[0034] Furthermore, according to a preferred embodiment of the present invention, since the output of each comparator circuit is preferably an open collector type or an open drain type, the parallel connection having a common switching control signal is simplified. Thus, a converter device having a stable load current has a simple structure.

[0035] Other features, elements, steps, advantages and characteristics of the present invention will become more apparent from the following detailed description of preferred embodiments thereof with reference to the attached drawings.

[0051] A ripple converter type DC—DC converter according to a first preferred embodiment of the present invention is described with reference to FIGS. 1 to 5.

[0052] FIG. 1 is a circuit diagram showing the construction of a ripple converter of the present preferred embodiment.

[0053] Furthermore, FIG. 2 shows in detail a reference voltage correction circuit 20 in the ripple converter shown in FIG. 1.

[0054] As shown in FIG. 1, in the ripple converter of the present preferred embodiment, an N-type FET₁ (hereinafter simply referred to as an FET₁) and an inductor L₁ are connected in order from the side of an input terminal 3 between the input terminal 3 and an output terminal 4. The drain of the FET₁ is connected to the input terminal 3 and the source of the FET₁ is connected to the inductor L₁. Furthermore, the gate of the FET₁ is connected to the control signal output terminal of an H/S driver circuit 1. Moreover, a bootstrap circuit in which a bootstrap diode D₀ and a bootstrap capacitor C₀ are connected in series is connected between the drain and source of the FET₁. In the bootstrap circuit, the anode of the bootstrap diode D₀ is connected to the drain of the FET₁ and the input terminal 3, and the bootstrap capacitor C₀ is connected to the source of the FET₁.

[0055] In the H/S driver circuit 1, the power input side terminal is connected to the connection point between the cathode of the bootstrap diode D₀ and the bootstrap capacitor C₀ of the bootstrap circuit, and the ground side terminal is connected to the connection point between the bootstrap capacitor C₀ and the source of the FET₁. In this way, the charged voltage at the bootstrap capacitor C₀ of the bootstrap circuit is applied to the H/S driver circuit 1. Moreover, the output terminal of a comparator 10 is connected to the signal input terminal of the H/S driver circuit 1 through an inverter 12, and a signal output from the comparator 10 is inverted and input to the signal input terminal.

[0056] An N-type FET₂ (hereinafter simply referred to as a FET₂) is connected between the ground terminal 5 and the connection point of the FET₁ and the inductor L₁. Here, in the FET₂, the drain is connected to the connection point between the FET₁ and the inductor L1 and the source is connected to the ground terminal 5. Furthermore, the gate of the FET₂ is connected to the control signal output terminal of an L/S driver circuit 2.

[0057] The power input terminal of the L/S driver circuit 2 is connected to the input terminal 3 and the ground side terminal is connected to the ground terminal 5. Moreover, the output terminal of the comparator 10 is connected to the signal input terminal of the L/S driver circuit 2 and a signal input from the comparator 10 is directly input to the signal input terminal.

[0058] A capacitor C₁ is connected between the ground terminal and the connection point between the inductor L₁ and the output terminal 4, and a series circuit of resistors R1 and R2 is connected in parallel with the capacitor C₁.

[0059] The connection point of the resistors R1 and R2 is connected to the non-inverting terminal of the comparator 10 and the connection point is also connected to the input side of the reference voltage correction circuit 20.

[0060] In the comparator 10, the non-inverting input terminal is connected to the connection point between the resistor R₁ and the resistor R₂, and the inverting input terminal is connected to the output side of the reference voltage correction circuit 20. Furthermore, the positive power-supply terminal of the comparator 10 is connected to the input terminal 3 and the negative power-supply terminal is grounded. Then, in the comparator 10, a voltage to be input to the non-inverting input terminal, that is, a voltage Vor obtained by dividing an output voltage Vout by the resistance values of the resistors R₁ and R₂ is compared with a correction reference voltage output from the reference voltage correction circuit 20 which is to be input to the non-inverting input terminal and a switching control signal of a two-state signal with a High state or a Low state is output.

[0061] Here, a smoothing circuit 13 includes the inductor L₁ and the capacitor C₁, and a comparator circuit 14 includes the comparator 10, the resistors R₁ and R₂, and the reference voltage correction circuit 20.

[0062] The reference voltage correction circuit 20 includes an operational amplifier 100, the inverting input terminal of which is connected to the connection point between the resistors R₁ and R₂ through a resistor R₂₁ and a capacitor C₂₁ connected between the output terminal of the operational amplifier 100 and the inverting input terminal. The non-inverting input terminal of the operational amplifier 100 is connected to the connection point between resistors R₃₃ and R₃₄ constituting a series circuit, the resistor R₃₃ is grounded, and the resistor R₃₄ is connected to the positive electrode of a reference power supply outputting a reference voltage Vo. The negative electrode of the reference power supply is grounded. The output terminal of the operational amplifier 100 is connected to the connection point between resistors R₂₃ and R₂₄ constituting a series circuit through a resistor R₂₂, the resistor R₂₃ is grounded, and the resistor R₂₄ is connected to the positive voltage side of the reference power supply outputting the reference voltage Vo. Furthermore, the connection point between the resistors R₂₃ and R₂₄ is connected to the inverting terminal of the comparator 10. Moreover, the resistors R₂₃ and R₃₃ preferably have the same resistance value, and the resistors R₂₄ and R₃₄ preferably have the same resistance value. The series circuit of the resistors R₂₃ and R₂₄ and the series circuit of the resistors R₃₃ and R₃₄ correspond to a voltage divider circuit of a preferred embodiment of the present invention. Furthermore, the reference voltage Vo is a voltage determined by the voltage divider ratio due to the resistors R₃₃ and R₃₄ of the divider voltage due to the resistors R₁ and R₂ to a desired output voltage so that the output voltage Vout may become the desired voltage value (set voltage value).

[0063] When such a circuit is constructed, an integration circuit is defined by the operational amplifier 100, the capacitor C₂₁, and the resistor R₂₁, and a correction voltage in accordance with the difference between the time average of a divider voltage Vor due to the resistors R₁ and R₂ of the output voltage Vout and a divider reference voltage Vop obtained by dividing the reference voltage Vo by the resistance values of the resistors R₃₃ and R₃₄ is output from the output terminal of the operational amplifier 100. Then, the reference voltage correction circuit 20 outputs a correction reference voltage Vref, that is, the divider voltage (divider reference voltage Vop) due to the resistors R₂₃ and R₂₄ of the reference voltage Vo corrected by the correction voltage to the inverting input terminal of the comparator 10. Here, the divider reference voltage Vop is a comparative voltage.

[0064] The ripple converter constructed as described above operates in the following way.

[0065] In the initial state where the output voltage Vout is 0 V, a voltage of 0 V is input to the non-inverting input terminal of the comparator 10. On the other hand, the correction reference voltage Vref of a fixed voltage value in accordance with the reference voltage Vo is input to the inverting input terminal of the comparator 10. Therefore, the comparator 10 outputs a switching control signal of 0 V (Low signal) by comparing the voltages. The inverter 12 outputs a High signal of a fixed voltage to the H/S driver circuit 1 by inverting the Low signal.

[0066] When the High signal is input, the H/S driver circuit 1 generates a gate-on signal (hereinafter simply referred to as an on signal) and outputs the on signal to the gate of the FET₁. At this time, since the bootstrap capacitor C₀ is charged by the input voltage Vin in advance, an on signal having a voltage value higher than the input voltage Vin raised by the bootstrap capacitor C₀ is input to the gate of the FET₁. On the other hand, a Low signal is directly input to the L/S driver circuit 2 from the comparator 10, and the L/S driver circuit 2 generates a gate-off signal (hereinafter simply referred to as an off signal) due to the Low signal and outputs the off signal to the gate of the FET₂.

[0067] Thus, since the FET₁ is turned on by an on signal from the H/S driver circuit 1 and the FET₂ is turned off by an off signal from the L/S driver circuit 2, a voltage in accordance with an input voltage Vin is supplied to the output terminal 4 through the smoothing circuit 13 having the inductor L₁ and the output voltage Vout gradually increases.

[0068] When an output voltage Vout in accordance with an input voltage Vin is supplied to the output terminal 4, a divider voltage Vor (=Vout·R₂/(R₁+R₂)) due to the resistors R₁ and R₂ connected between the output terminal 4 and the ground terminal 5 is input to the non-inverting input terminal of the comparator 10. When the divider voltage Vor is lower than the correction reference voltage Vref input to the inverting input terminal from the reference voltage correction circuit 20, the output of the comparator 10 does not change. At this time, the correction reference voltage Vref changes in accordance with the change of the input voltage Vout caused by the operation of the reference voltage correction circuit 20 as will be described later.

[0069] Next, when an output voltage Vout where the divider voltage Vor is larger than the correction reference voltage Vref is output from the output terminal 4, a switching control signal of a High signal in accordance with the power supply voltage corresponding to the input voltage Vin is output from the comparator 10. The inverter 12 inverts the input High signal and outputs a Low signal to the H/S driver circuit 1.

[0070] When the Low signal is input, the H/S driver circuit 1 generates an off signal to the gate of the FET₁. On the other hand, a High signal is input to the L/S driver circuit 2 directly from the comparator 10, and, when the High signal is input, the L/S driver circuit 2 generates an on signal and outputs the on signal to the gate of the FET₂.

[0071] In this way, the FET₁ is turned off by an off signal being input and the FET₂ is turned on by an on signal being input. Thus, the connection point of the drain of the FET₁, the source of the FET₂, and the inductor L₁ is made conductive to the ground terminal 5 between the drain and source of the FET₂ which is in the on state. Thus, the voltage Vds (substantially 0 V) between the drain and source of the FET₂ which is in the on state is applied to the inductor L₁, and thus, the input voltage Vout gradually decreases. At this time, a voltage obtained by subtracting the backward voltage of the bootstrap diode D₀ and the voltage between the drain and the source of the FET₂ from the input voltage Vin is applied to the bootstrap capacitor C₀ connected to the H/S driver circuit 1 in parallel to charge the bootstrap capacitor C₀.

[0072] This operation continues until the divider voltage Vor becomes lower than the correction reference voltage Vref, and, when the divider voltage Vor becomes lower than the correction reference voltage Vref, the FET₁ is turned on and the FET₂ is turned off as described above. Also at this time, the correction reference voltage Vref changes in accordance with the change of the output voltage Vout due to the operation of the reference voltage correction circuit 20 to be described later.

[0073] Then, an output voltage Vout substantially in agreement with a desired voltage value (corresponding to a set voltage of a preferred embodiment of the present invention) on the basis of the reference voltage Vo is continuously output from the output terminal 4 by repeating the above-described operation.

[0074] Next, the specific operation of the reference voltage correction circuit 20 is described.

[0075] A divider reference voltage Vop (Vo·R₃₃/(R₃₃+R₃₄) obtained by dividing the reference voltage Vo generated in the reference power supply by the resistance values of the resistors R₃₃ and R₃₄ is input to the non-inverting input terminal of the operational amplifier 100 in the reference voltage correction circuit 20.

[0076] When the divider voltage Vor of the output voltage Vout is input to the inverting input terminal of the operational amplifier 100 through the resistor R₂₁, the operational amplifier 100 generates a correction voltage by comparing the divider voltage Vor input with the divider reference voltage Vop input to the non-inverting input terminal. For example, when the voltage input to the inverting input terminal is lower than the divider reference voltage Vop, the correction voltage is a fixed positive voltage value, and, when the voltage input to the inverting input terminal is higher than the divider reference voltage Vor, the correction voltage is a fixed negative voltage value.

[0077] Furthermore, a voltage of the same level as the divider reference voltage Vop is supplied to the connection point between the resistors R₂₃ and R₂₄ from the reference power supply in such a way that the reference voltage Vo is divided by the resistance values of the resistors R₂₄ and R₂₃. Here, the correction voltage output from the operational amplifier 100 is applied to the connection point between the resistors R₂₃ and R₂₄ through the resistor R₂₂, and a voltage being the divider reference voltage Vop corrected by the correction voltage is output as a correction reference voltage Vref to the inverting input terminal of the comparator 10.

[0078] Since the operational amplifier 100 includes an integration circuit together with the capacitor C₂₁ and the resistor R₂₁ as described above, when the divider voltage Vor of the output voltage Vout is continuously input, the average value of the divider voltage Vor is input to the inverting input terminal. That is, the time average of the divider voltage Vor is input with the passage of time. Therefore, a correction voltage in accordance with the difference between the time average of the divider voltage Vor of the output voltage Vout and the divider reference voltage Vop is output from the operational amplifier 100. Then, the correction reference voltage Vref being the divider reference voltage Vop corrected by a divider voltage due to the resistors R₂₂ and R₂₃ of the correction voltage, as the output of the reference voltage correction circuit 20, is input to the inverting input terminal of the comparator 10.

[0079] Here, when the input voltage Vin is high and the average value of the output voltage Vout is higher than a set voltage Vset (voltage as a reference voltage), the divider voltage Vor of the output voltage Vout also becomes higher than the correction reference voltage Vop. This is because, as described with respect to the problems of the prior art, the period where the instantaneous value of the output voltage is higher than the set voltage Vset continues for a long time. In such a case, in the reference voltage correction circuit 20 shown in the present preferred embodiment, since the average value of the divider voltage Vor is higher than the divider reference voltage Vop, a negative correction voltage is output from the operational amplifier 100, and a correction reference voltage Vref which is a divider reference voltage Vop corrected by the negative correction voltage, that is, the correction reference voltage Vref lower than the divider reference voltage Vop is output to the inverting input terminal of the comparator 10. The comparator 10 outputs a switching control signal by comparing the correction reference voltage Vref with the divider voltage Vor of the output voltage Vout. The H/S driver circuit 1 and L/S driver circuit 2 on and off control the FET₁ and FET₂ on the basis of the switching control signal, respectively. Then, the peak voltages on the maximum-value side and minimum-value side of the instantaneous value of the output voltage Vout decreases in such a way that the FET₁ and FET₂ are on and off controlled by the correction reference voltage Vref.

[0080] The operation in this case is specifically described with reference to FIG. 3.

[0081] FIG. 3(A) shows a set voltage Vset (dependent on the reference voltage Vo) and the waveform of the instantaneous value and the average voltage Vavg of the output voltage Vout when a switching control is performed at the set voltage Vset in the case where the input voltage Vin is high. FIG. 3(B) shows a correction set voltage Vsa (dependent on the correction reference voltage Vref) and the waveform of the instantaneous value and the average voltage Vavg of the output voltage Vout when a switching control is performed by the correction set voltage Vsa in the case where the input voltage Vin is high.

[0082] First, since the time t1 from the point where the instantaneous value of the output voltage Vout becomes equal to or higher than the set voltage Vset and the correction set voltage Vsa to the point where the FET₁ is turned off (the point where the instantaneous value becomes the maximum voltage) is dependent on the transmission characteristics of a control signal of the converter and the switching characteristics of the FET₁, the time t1 is not dependent on whether or not the set voltage Vset is corrected. Accordingly, the time t1 is the same whether or not the set voltage Vset is corrected. In the same way, since the time t2 from the point where the instantaneous value of the output voltage Vout becomes equal to or lower than the set voltage Vset and the correction set voltage Vsa to the point of time where the FET₁ is turned on (point where the instantaneous value becomes the minimum voltage) is dependent on the transmission characteristics of a control signal of the converter and the switching characteristics of the FET₁, the time t2 is not dependent on whether or not the set voltage Vset is corrected. Accordingly, the time t2 is the same whether or not the set voltage Vset is corrected. Moreover, since the input voltage Vin is the same whether or not the set voltage Vset is corrected, the rate of time-dependent change of the output voltage Vout due to the switching of the FET₁ (inclination of the voltage waveform) is also the same.

[0083] Therefore, as shown in FIG. 3(B), when the correction set voltage Vsa is lower than the set voltage Vset, since the time t1 is the same and the ratio of time-dependent change (rate of increase) is the same as described above, the maximum value of the output voltage Vout is lowered as much as the amount where the correction set voltage Vsa is lower than the set voltage Vset. At the same time, since the time t2 is the same and the ratio of time-dependent change (rate of decrease) is the same as described above, the minimum value of the output voltage Vout is also lowered as much as the amount where the correction set voltage is lower than the set voltage Vset. Because of this, the output voltage Vout is lowered as a whole and, in accordance with this, the average voltage Vavg is lowered. At this time, since the reference voltage correction circuit 20 outputs a correction voltage in accordance with the difference between the average voltage of the divider voltage Vor of the output voltage Vout and the divider reference voltage Vop, when the average voltage Vavg of the divider voltage Vor becomes close to the divider reference voltage Vop, the absolute value of the correction voltage is also lowered. Thus, the average voltage Vavg of the output voltage Vout gradually becomes close to the set voltage Vset.

[0084] Next, when the input voltage Vin is low and the average value of the output voltage Vout is lower than the set voltage Vset (voltage as a reference voltage), the divider voltage Vor of the output voltage Vout also becomes lower than the divider reference voltage Vop. This is because the period where the instantaneous value of the set voltage Vset is lower than the set voltage Vset becomes longer as described with respect to the problems with the prior art. In such a case, in the reference voltage correction circuit 20 shown in the present preferred embodiment, since the average value of the divider voltage Vop is lower than the divider reference voltage Vop, a positive correction voltage is output from the operational amplifier 100, and the correction reference voltage Vref being the divider reference voltage Vop corrected by the positive correction voltage, that is, the correction reference voltage higher than the divider reference voltage Vop is output to the inverting input terminal of the comparator 10. The comparator 10 outputs a switching control signal by comparing the correction reference voltage Vref with the divider voltage Vor of the output voltage Vout. The H/S driver circuit 1 and L/S driver circuit 2 on and off control the FET₁ and FET₂ on the basis of the switching control signal. Then, the peak on the maximum-value side and the peak on the minimum-value side of the instantaneous value of the output voltage Vout increase and the average value of the output voltage Vout increases in such a way that the FET₁ and FET₂ are on and off controlled by the correction reference voltage Vref.

[0085] The operation in this case is specifically described with reference to FIG. 4.

[0086] FIG. 4(A) shows a set voltage Vset (dependent on the reference voltage Vo) and the waveform of the instantaneous value and the average voltage Vavg of the output voltage Vout when a switching control is performed at the set voltage Vset in the case where the input voltage Vin is low. FIG. 4(B) shows a correction set voltage Vsa (dependent on the correction reference voltage Vref) and the waveform of the instantaneous value and the average voltage Vavg of the output voltage Vout when a switching control is performed by the correction set voltage Vsa in the case where the input voltage Vin is low.

[0087] First, in the same way as in the case where the correction set voltage Vsa is lower than the set voltage Vset, the time t1 from the point where the instantaneous value of the output voltage Vout becomes equal to or higher than the set voltage Vset and the correction set voltage Vsa to the point where the FET₁ is turned off (point where the instantaneous value becomes the maximum voltage), the time t2 from the point where the instantaneous value of the output voltage Vout becomes equal to or lower than the set voltage Vset and the correction set voltage Vsa to the point where the FET₁ is turned on (point where the instantaneous value becomes the minimum voltage), and the rate of time-dependent change of the output voltage Vout due to the switching of the FET₁ (inclination of the voltage waveform) are always the same.

[0088] Therefore, as shown in FIG. 4(B), when the correction set voltage Vsa is higher than the set voltage Vset, since the time t1 is the same and the ratio of time-dependent change (the rate of increase) is the same as described above, the maximum value of the output voltage Vout is increased as much as the amount where the correction set voltage Vsa is higher than the set voltage Vset. At the same time, since the time t2 is the same and the ratio of time-dependent change (rate of decrease) is the same as described above, the minimum value of the output voltage Vout is also increased as much as the amount where the correction set voltage Vsa is higher than the set voltage Vset. Because of this, the output voltage Vout is increased as a whole and, in accordance with this, the average voltage Vavg is increased. At this time, since the reference voltage correction circuit 20 outputs a correction voltage in accordance with the difference between the average voltage of the divider voltage Vor of the output voltage Vout and the divider reference voltage Vop, when the average voltage Vavg of the divider voltage Vor becomes close to the divider reference voltage Vop, the absolute value of the correction voltage is also lowered. Thus, the average voltage Vavg of the output voltage Vout gradually becomes close to the set voltage Vset.

[0089] In the description up to now, although the change of the input voltage Vin is assumed, even if the input voltage Vin is constant and the set value of the output voltage changes, the fact that the duty factor changes with that and the output voltage Vout deviates from a set value is the same, and this case also functions in the same way as the above.

[0090] FIG. 5 shows the average voltage value of the output voltage Vout, the set voltage value, and their errors in the case where the input voltage Vin is about 5.0 V, the reference voltage Vo is about 0.8 V, and the set voltage value is changed. The figure shows the case where the ripple converter includes the reference voltage correction circuit and the case where the ripple converter does not include the reference voltage correction circuit.

[0091] FIG. 5 shows the effect in the case where the reference voltage Vo is constant, the set voltage Vset is decided by changing the divider ratio due to the resistors R₁ and R₂ between the output terminal 4 and the ground terminal 5 in FIG. 1, and the output voltage set value to the input voltage Vin is changed.

[0092] As shown in FIG. 5, when the reference voltage correction circuit is not provided, the set voltage Vset to the input voltage Vin is reduced, the output voltage Vout becomes higher than the set voltage Vset as the difference between the set voltage Vset and the input voltage Vin increases, the set voltage Vset becomes close to the input voltage Vin, and the output voltage becomes lower than the set voltage Vset as the difference between the set voltage Vset and the input voltage Vin.

[0093] On the other hand, when the reference voltage correction circuit is provided as shown in the present preferred embodiment, the output voltage Vout can be made substantially in accord with the set voltage Vset without being affected by the relatively large or small relationship between the set voltage Vset and the input voltage Vin.

[0094] When constructed as described above, a ripple converter type DC—DC converter of a simple structure in which a desired output voltage can be obtained without being affected by the value of switching duty factor can be constructed.

[0095] Next, a converter device according to a second preferred embodiment is described with reference to FIG. 6.

[0096] FIG. 6 shows a circuit diagram showing the structure of a converter device according to the present preferred embodiment.

[0097] As shown in FIG. 6, in the converter device of the present preferred embodiment, the output terminals 4 and the ground terminals 5 of ripple converters 101 and 102 are connected to each other and an output voltage is output from the common line. The structure of the ripple converters 101 and 102 of the converter device is preferably substantially the same as the ripple converter shown in FIG. 1.

[0098] Furthermore, the output of the comparator of each of the ripple converters 101 and 102 is preferably an open drain type or an open collector type and is pulled up by a resistor R40. Then, the output terminals of the comparators 10 of the ripple converters 101 and 102 are connected to each other to constitute a wired type OR circuit.

[0099] In such a circuit construction, when the output signal (switching control signal) of each comparator 10 of the ripple converters 101 and 102 follows OR logic (negative logic), that is, when the switching control signal output from at least one comparator 10 is a Low signal, the ripple converters 101 and 102 are controlled in accordance with the signal. Thus, the ripple converters 101 and 102 connected in parallel are synchronously controlled and the output currents of the ripple converters 101 and 102 become substantially the same. Moreover, in the state of ordinary operation, either of the ripple converters, in which the output voltage is high, is switched to the Low state and the output of the comparator of the other ripple converter is fixed to the High state. Furthermore, when the output voltages are in accord with each other, the ripple converters are synchronized to either of them which have a low frequency.

[0100] Furthermore, since the reference voltage correction circuit 20 is provided in each of the ripple converters 101 and 102, the output voltage of the ripple converters 101 and 102 is substantially in accord with the set voltage Vset regardless of the amplitude of the input voltage. Then, since the correction reference voltage in each of the ripple converters 101 and 102 is stable, even if the characteristics of the converters are changed by the effect of the external environment, etc., the high and low relationship between the correction reference voltages does not change and is able to continue a stable parallel operation.

[0101] This point is specifically described. FIG. 7 is the circuit diagram of a converter device in which a wired type OR circuit as shown in FIG. 6 is constituted by using ripple converters 103 and 104 not having a reference voltage correction circuit 20.

[0102] Furthermore, FIG. 8 shows output voltage waveforms of the ripple converters 103 and 104 used in the converter device shown in FIG. 7 and the change of the state of the FET. FIG. 8(A) shows the output voltage waveform of the ripple converter 103, FIG. 8(B) shows the change of the state of the FET₁ in the ripple converter 103, FIG. 8(C) shows the output voltage waveform of the ripple converter 104, and FIG. 8(D) shows the change of the state of the FET₁ in the ripple converter 104.

[0103] As shown in FIG. 7, in the converter device using the ripple converters 103 and 104 in which the reference voltage correction circuit 20 is not used, a reference power supply generating the reference voltage Vo is directly connected to the inverting input terminal of the comparator 10, and the other construction is the same as in the converter device shown in FIG. 6.

[0104] In such a circuit construction, although the ripple converters 103 and 104 are designed in the same way, as shown in FIG. 8, when the output voltage and the switching delay time are different due to variations of the characteristics of the structure elements and the circuit, the operation of the converter device becomes unstable.

[0105] As shown in FIG. 8, it is assumed that the reference voltage of the ripple converter 103 is practically Va, the delay time is t1a, and the average voltage of the ripple voltage is Va. Then, the case, in which the reference voltage of the ripple converter 104 is practically Va+α(α>0) due to characteristic variations, etc., the delay time is t1b (<t1a), and the average of the feedback voltage in the ripple converter 104 is Va due to the cancellation between variations of the reference voltage and variations of the delay time t1b, is considered.

[0106] Here, when the ripple converters 103 and 104 are operated in parallel, because of the above-described characteristics, first, the converter device operates in synchronization with the output of the comparator 10 of the ripple converter 103 having a low operation frequency. However, when the delay time t1b of the ripple converter 104 increases due to external factors, etc., during the parallel operation, the output of the ripple converter 104 increases and the converter device operates in synchronization with the output of the comparator 10 of the ripple converter 104. That is, the comparator 10 as a master controlling the operation of the converter device is easily switched between the ripple converters 103 and 104 due to external factors, etc. That is, the operation of the converter device becomes unstable.

[0107] Here, by using the structure of the present preferred embodiment (structure shown in FIG. 6), that is, by providing the reference voltage correction circuit 20 in each of the ripple converters in parallel operation, even if the operation shown in FIG. 8 is performed by the ripple converters 101 and 102 in simple parallel operation in FIG. 6, for example, the voltage (practical reference voltage) input to the comparator is stabilized at the correction reference voltage output from the reference voltage correction circuit 20. Also, the ripple converter 101 is synchronized to the output of the comparator 10 of the ripple converter 102 having a high output voltage. That is, even if the delay time is changed due to external factors, etc., the practical reference voltage is corrected by the reference voltage correction circuit 20 and stabilized at the correction reference voltage, and, as a result, the comparator 10 as a master is always on the side of the ripple converter 102.

[0108] At this time, in the reference voltage correction circuit 20 in the ripple converter 101, since the divider voltage Vor is always higher than the divider reference voltage Vop, the output of the operational amplifier 100 in the reference voltage correction circuit 20 becomes in the Low state and the correction reference voltage Vref of the comparator 10 becomes far lower than the divider reference voltage Vop and the divider voltage Vor. Therefore, a switching control signal output from the comparator 10 is in the High state. In this way, the practical reference voltage of the ripple converter 101 is greatly reduced from the original value, and, since the voltage does not cross the triangular waveform appearing as a divider voltage Vor, even if the delay times t1a and t1b change due to external factors, etc., the switching control signal output from the comparator 10 of the ripple converter 101 is always in the High state. Thus, the ripple converter 102 always functions as the master converter and the master and slave relationship does not change between the ripple converters. As a result, when the structure of the present preferred embodiment is used, a converter device capable of stable operation can be more securely constructed.

[0109] Next, the experimental result using a converter device having the structure shown in FIG. 6 of the present preferred embodiment is shown.

[0110] FIG. 9(A) and FIG. 9(B) show the waveform, operation frequency, output voltage, and output current share ratio of a switching control signal when each of two ripple converters constructed so as to obtain a fixed output voltage, respectively, is solely operated. Furthermore, FIG. 9(C) and FIG. 9(D) show the waveform, operation frequency, output voltage, and output current share ratio of a switching control signal when the two ripple converters in parallel connection are operated.

[0111] Moreover, in the present preferred embodiment, a ripple converter A having an operation frequency of 520 kHz and an output voltage of 2.562 V when solely operated and a ripple converter B having an operation frequency of 555 kHz and an output voltage of 2.504 V were used as an example.

[0112] As shown in FIG. 9(A) and FIG. 9(B), when each of the ripple converters A and B is independently operated, naturally the ripple converters A and B operate to have the characteristics (operation frequency and output voltage) in accordance with the characteristics when solely operated, respectively. Accordingly, when they are simply operated in parallel, a beat produced by the difference between the operation frequencies is generated, the share ratios of the ripple converter A and ripple converter B becomes about 70% and 30%, and, since the current sharing performance is reduced, the operation at the time of transition load becomes difficult to stabilize.

[0113] On the other hand, as shown in FIG. 9(C) and FIG. 9(D), when these ripple converters A and B are operated in parallel according to the structure of the present preferred embodiment, the driving frequencies of both ripple converters A and B are in accord with each other at 510 kHz and the output voltages are also in accord with each other at 2.562 V. Thus, since the output characteristics of both ripple converters A and B are in accord and the output current share ratio becomes 51% and 49%, that is, substantially the same, the load current is stabilized and the performance of current sharing is improved. As a result, a stable operating converter device can be constructed.

[0114] Moreover, in the ripple converters of the converter device shown in the above-described second preferred embodiment, although a wired OR circuit is constructed by making the output of the comparator of an open drain type or open collector type, the above construction can be applied without using such a comparator.

[0115] FIG. 10 shows a circuit diagram showing the output portion of the comparator 10 of the ripple converters 101 and 102 of the converter device shown in FIG. 6.

[0116] As shown in FIG. 10, when a comparator which is not an open drain type or an open collector type is used, the output of the comparator 10 is pulled up by a resistor R₄₀ through a diode D₄₀ and the connection point between the diode _D40 and the resistor R₄₀ may be used in the parallel connection. By using such a construction, the same operation can be performed as in the case where a comparator of open drain type or open collection type is used in the circuit construction shown in FIG. 6.

[0117] Furthermore, FIG. 11 is a circuit diagram of another construction showing the output portion of the comparator 10 of the ripple converters 101 and 102 of the converter device shown in FIG. 6.

[0118] As shown in FIG. 11, when a comparator that is not an open drain type or an open collector type is used, the output of the comparator 10 is pulled down by the resistor R₄₀ through the diode D₄₀ and the connection point between the diode D₄₀ and the resistor R₄₀ may be used in the parallel connection. By using such a construction, two ripple converters may be made to operate in synchronization with a ripple converter having a lower output voltage, different from the case where a comparator of an open drain type or open collector type is used in the circuit construction shown in FIG. 6.

[0119] Furthermore, two ripple converters may be operated in synchronization with a ripple converter having a lower output voltage in such a way that an extraction circuit for an OR logic in the output of each comparator is used in the parallel connection in the output of the comparator.

[0120] Moreover, in the above-described preferred embodiment, although a converter device in which two ripple converters are connected in parallel is shown, the above-described construction can be applied to a converter device in which three or more ripple converters are connected in parallel. All the ripple converters may be synchronously controlled by the output of the comparator of any one of the ripple converters and the above-described effect can be obtained.

[0121] Furthermore, in the construction of the above-described preferred embodiment, although an example in which ripple converters are connected by using a wired OR circuit is shown, ripple converters are connected in parallel by other constructions such as OR circuits other than the wired type and the output may be shared by all.

[0122] While the present invention has been described with respect to preferred embodiments thereof, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many preferred embodiments other those specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the present invention which fall within the true spirit and scope of the invention.