Scheme for determining internal mode using MCLK frequency autodetect

[0001] This application claims priority from U.S. Provisional Patent Application No. 60/574,330, entitled “CLOCK MODE DETECTION SCHEMES IN DATA CONVERTERS” filed May 25, 2004, which is hereby incorporated.

[0002] 1. Field of the Invention

[0003] The present invention generally relates to clocking systems for electronic circuits, and more particularly to a method of determining which of a plurality of different operating modes is to be used by a circuit, which is adapted to receive a variety of external clock signals.

[0004] 2. Description of the Related Art

[0005] Various types of electronic circuits have been constructed that support a wide range of different clock modes. For example, data converters can operate in different speed modes in which different master clock rates and sample clock rates are used. A digital-to-analog converter might have two operating modes, such as a base mode and a high mode, depending on what master clock rate and sample clock rate are being provided from the front-end circuitry. This capability allows a single converter to support multiple applications and gives the end-user (i.e., the final product manufacturer) greater flexibility in the design of the overall electronic system.

[0006] A conventional digital-to-analog converter (DAC) 10 is illustrated in FIG. 1 and includes a digital (binary) signal source 12, which provides the primary input to a delta-sigma modulator 14. The digital signal source could be from, e.g., a digital radio receiver, an audio compact disc (CD), a digital audio tape (DAT), a digital video disc (DVD), a broadcast satellite, or personal computer (PC) audio. Delta-sigma modulator 14 feeds a multilevel noise-shaped signal based on the digital input stream to a multi-level pulse-density modulation (PDM) encoder 16. PDM encoder 16 turns the signal from delta-sigma modulator 14 into a multi-level, discrete-time analog signal. Low-pass filter 18 removes high frequencies from the output, and the filtered output then drives some other device such as a speaker 20.

[0007] Conventional data converters have dramatically grown in complexity and capability, and their clocking systems have also grown in complexity to more fully utilize the function and high performance provided by CMOS technology. A typical clocking system can provide a multiplicity of timing signals to the internal converter elements and to external devices. These clocks define the timing cycle for the data flow of the machine. Some clock signals can be non-overlapping and serve to isolate one cycle of operation from the next cycle, while other clock signals overlap so as to gain a performance advantage by anticipating the next cycle of operation. The positioning in time of these clocks is very critical for high performance, particularly for circuits such as DACs which operate in a pipelined manner, that is, are divided into separate stages such that a single DAC can actually be simultaneously performing multiple tasks for different (successive) data sequences during a single clock cycle. However, this scheme requires precise timing. External device considerations may also require fairly exact timing signals. Clock design becomes further complicated when a DAC must support a variety of external clock inputs.

[0008] DAC 10, for example, might support frequency ranges from a sample rate of 2 kHz and master clock rate of 0.5 MHz, to a sample rate of 192 kHz and a master clock rate of 48 MHz, all as part of distinct internal operating modes. The master clock signal is used to derive most of the control signals for the components of DAC 10, and the sample rate signal represents the sampling rate for the encoder which previously created the digital signal stream from an original analog source. CDs typically use a sampling rate of 44.1 kHz, PC audio uses a sampling rate of 48 kHz, DVDs use a sampling rate of 96 kHz, and other high-end equipment can use a sampling rate of up to 192 kHz. Depending upon the particular operating mode that is selected, any or all of the components within DAC 10 (modulator 14, PDM encoder 16, and/or filter 18) might operate in a different manner.

[0009] Some devices provide a control port or other input that allows the user to explicitly select the desired clock configuration. However, this approach requires a higher pin count on the external physical interface for the integrated circuit (IC) which constitutes the device and assumes that the front-end circuitry will provide the mode selection signal. Accordingly, some converters have been devised which automatically determine the appropriate clock configuration based on the sample rate clock (or left/right clock, “LRCK”) and master clock (“MCLK”) frequencies. For instance, if the end-user provides an LRCK of 48 kHz and an MCLK of 12 MHz, these rates might imply a base mode of operation for the DAC, while a 96 kHz LRCK rate and a 12 MHz MCLK rate might imply a high mode of operation. The appropriate mode can be determined for these cases by simply examining the ratio of MCLK to LRCK, i.e., by counting the number of high signals for MCLK in an LRCK period. If the ratio is around 256, the base mode is enabled, and if the ratio is around 128, the high mode is enabled.

[0010] As digital signal processing technology improves and changes, a wider variety of clock rates must be supported to allow a single converter to be used in a growing number of applications. Unfortunately, existing solutions for establishing the proper clock configuration have become inadequate as more clock rate combinations are employed. For example, devices which utilize an LRCK of 48 kHz and an MCLK of 12 MHz currently exist for operation at a base rate, and other devices which utilize an LRCK of 96 kHz and an MCLK 24 MHz for operation at a high rate. Supporting both of these clock configurations would be preferable. However, the MCLK/LRCK ratio is the same for both (around 256) and selection of the base mode would result in improper operation for the latter case.

[0011] Another solution for determining the clock configuration examines the MCLK rate by comparing it to an internally generated frequency. A single comparison frequency can be so used for a wide range of MCLK rates, by dividing the MCLK signal using increasing integer values until it is at or near the internally generated value. A device that supported MCLK rates of 12 MHz, 18 MHz and 24 MHz could use a comparison frequency of 6 MHz and divide the MCLK signal successively by the integers 2, 3, and 4 until the quotient was around 6 MHz. This approach, however, also becomes unfeasible as alternative clock configurations arise which utilize the same master clock frequency and with more variation in the master clock rates.

[0012] In light of the foregoing, it would be desirable to devise an improved method for determining which of a plurality of clock configurations is to be used for an electronic device, such as a data converter. It would be further advantageous if the method were not solely dependent on either a master clock rate value or a ratio of two external clock signals.

[0013] The present invention provides an improved method and circuit for determining an internal operating mode of an electronic device based on externally provided clock signals.

[0014] The present invention provides a data converter which can operate in a plurality of different modes and support a plurality of different clock configurations for those modes.

[0015] The present invention provides a digital-to-analog converter that can automatically detect which operating mode is to be used based on external clock signals without adding excessive overhead to the circuit design and still allow for significant deviations in clock reference signals.

[0016] The present invention is a method for determining an internal operating mode of an electronic circuit such as an audio converter. The method involves deriving multiple comparison rates from a rate of a master clock input, computing one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determining whether any of the clock ratios is a valid ratio (i.e., one of a plurality of predetermined clock ratios) representing a supported clock configuration. The appropriate internal operating mode for the electronic circuit is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit derives at least first and second clock comparison rates, in which the first clock comparison rate is the same as the rate of the master clock input when the rate of the master clock input is less than or equal to a first trip frequency but is a fraction of the rate of the master clock input when the rate of the master clock input is greater than the first trip frequency. The second clock comparison rate is the same as the rate of the master clock input when the rate of the master clock input is less than or equal to a second trip frequency but is a fraction of the rate of the master clock input when the rate of the master clock input is greater than the second trip frequency. For example, to support master clock frequencies in the range of 8 MHz to 33 MHz, the first trip frequency is preferably at or around 16 MHz, and the second trip frequency is at or around 24 MHz. For the case in which the audio converter operates in three distinct modes (base, high, and quad), the base mode is selected when the clock ratio is at or about 256, the high mode is selected when the clock ratio is at or about 128, and the quad mode is selected when the clock ratio is at or about 64. A multiplexer can be used to sequence through the computed clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

[0017] The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.

[0026] The use of the same reference symbols in different drawings indicates similar or identical items.

[0027] With reference now to FIG. 2, one embodiment 30 of a digital-to-analog converter (DAC) constructed in accordance with the present invention is depicted. In this embodiment, DAC 30 operates as a 24-bit stereo D/A converter packaged in an integrated circuit (IC) chip having ten interconnection pins. DAC 30 generally includes a serial interface 32, de-emphasis logic 34, a pair of interpolation filters 36a, 36b, a pair of multibit delta-sigma modulators 38a, 38b, a pair of switched-capacitor DAC and filters 40a, 40b, an internal voltage reference 42, a single power supply 44 (e.g., 3.3 volts or 5 volts), and a clock autodetect unit 46. As explained further below, DAC 30 is adapted to support a wide variety of audio data interface formats having different master clock frequencies up to 49.1 MHz and different sample rate clock frequencies up to 192 kHz, and can operate in three different clock modes: base, high and quad modes. DAC 30 is particularly suited for audio applications, such as DVD players and recorders, digital televisions, home theater and set-top box products, and automotive audio systems.

[0028] A serial audio (data) input 50 is externally provided from front-end circuitry, representing a digitally-encoded stream of the combined left and right stereo channels that are to be reproduced. In this embodiment, DAC 30 utilizes two's complement serial audio data and accepts data at standard audio sample rates (LRCK) of 48 kHz, 44.1 kHz and 32 kHz in base mode, 96 kHz, 88.2 kHz and 64 kHz in high mode, and 192 kHz, 176.4 kHz and 128 kHz in quad mode. A serial clock is used to control the shifting of data into input data buffers. DAC 30 supports generation of both external and internal serial clock signals. With internal serial clock generation, the serial clock rate (SCLK) is derived from and synchronous with the master clock signal (MCLK) and LRCK. For example, the SCLK/LRCK frequency ratio can be set to 32, 48 or 64 depending upon the data format used (I²S format, left justified format, or right justified format). The master clock rate is an integer ratio of the sample rate, but not all sample rates are necessarily supported for all clock ratios. A phase relationship between MCLK, LRCK and SCLK is not required.

[0029] Serial interface 32 receives the data input 50 and acts as a switch to route the left and right serial data to the interpolation filters, i.e., the right channel data is fed to interpolation filter 36a and the left channel data is fed to interpolation filter 36b. The serial audio input is also received by de-emphasis logic 34. De-emphasis logic 34 is enabled only with internal serial clock generation and provides a de-emphasis curve having a frequency response which scales proportionally as the sample rate changes. De-emphasis provides additional digital filtering.

[0030] Interpolation filters 36a, 36b combine the interpolation and low pass filter response functions and can provide different passband characteristics depending upon the particular mode employed (base, high, or quad mode). The interpolation filters are respectively connected to the delta-sigma modulators, i.e., the output of interpolation filter 36a is connected to delta-sigma modulator 38a and the output of interpolation filter 36b is connected to delta-sigma modulator 38b. Delta-sigma modulators 38a, 38b are fourth order multi-bit modulators that provide quantized values used to drive the respective analog filters 40a, 40b. In this embodiment, each analog filter is actually a switched-capacitor DAC followed by a continuous-time low pass filter. The full-scale analog output voltage at outputs 52a, 52b is nominally about 0.688 times the DC power supply voltage.

[0031] Referring now to FIG. 3, a physical layout is shown of the interconnection pins (input and output) on the integrated circuit chip 54 for this embodiment of DAC 30. Pin # 1 is the pin for the serial audio data input (SDIN). Pin # 2 is the pin for the de-emphasis/external serial clock input (DEM/SCLK) used alternatively for enabling the de-emphasis logic or receiving the external serial clock input. Pin # 3 is the pin for the sample rate clock input (LRCK) that determines which channel, left or right, is currently active on the serial audio data line. Pin # 4 is the pin for the master clock input (MCLK) used as the clock source for the delta-sigma modulators and digital filters. Pin # 5 is the pin for an analog common mode output, or quiescent voltage (VQ). Pin # 6 is the pin for a positive reference voltage output for the internal sampling circuits (FILT+), i.e., voltage reference 42. Pin # 7 is the pin for the left channel analog output (AOUTL), i.e., output 52b. Pin # 8 is the pin for a reference input for electrical ground (GND). Pin # 9 is the pin for the analog power source input (VA), i.e., 3.3 volts or 5 volts. Pin # 10 is the pin for the right channel analog output (AOUTR), i.e., output 52a. In the system configuration shown in FIG. 3, an external clock 56 provides the MCLK signal directly to DAC 30 and also to an audio data processor 58, which, in turn, provides the SDIN, DEM/SCLK and LRCK.

[0032] DAC 30 is initialized at power-up by resetting interpolation filters 36a, 36b and delta-sigma modulators 38a, 38b. Power to internal voltage reference 42 and back-end filters 40a, 40b is initially cut off and remains so until MCLK and LRCK are present. Once MCLK and LRCK are detected, the clock configuration is examined by the autodetect unit 46 to determine the desired operating mode (base, high or quad mode) based on the supported combinations of MCLK and LRCK. Internal dividers are then appropriately set to generate the proper clock signals, and power is applied to internal voltage reference 42. Power is thereafter applied to back-end filters 40a, 40b and the analog outputs 52a, 52b will ramp to the common mode VQ. The audio outputs, AOUTL and AOUTR, can be clamped to VQ when the device is initially powered-up to reduce the effects of output transients.

[0033] The three modes of operation contemplated in the illustrative embodiment (base rate mode, high rate (or double speed) mode and quad rate mode), dictate what the output sample rate is for the DAC (or what the input sample rate would be for an ADC). More generally, the different operating modes represent two or more distinct methods of processing digital information signals input to the digital-to-analog converter. An operating mode can consist of both the clocks used within the chip, and other configuration information such as the appropriate filters to utilize. In this embodiment, three modes are used because different customers (i.e., end-use devices) have different requirements which can be suitably addressed using the three different modes. For instance, CD audio at 44.1 kHz is base rate mode, while DVD audio at 192 kHz is quad rate mode. While different modes have different sample rates, the chip clock (MCLK) may be the same for all the modes. Different modes may also have different on-chip filtering. One mode might support different features that are not supported in other modes. An example is the de-emphasis in the present chip. A given mode can cover a range of sample rates, not necessarily just one rate, e.g., base rate could be anywhere from 32 kHz to 64 kHz, high rate from 80 kHz to 128 kHz and so on. In the illustrative embodiment, filters 52a, 52b operate differently based on the particular mode employed, but alternative embodiments could allow other components (e.g., the modulators) to have different modes of operation for different clock configurations. Filters 52a, 52b have different low pass characteristics depending upon the particular clock mode used and can also use different amounts of interpolation. By utilizing the clock autodetect feature of the present invention, a single DAC can be integrated into a wider variety of end-use devices.

[0034] With further reference to FIGS. 4 to 7, autodetect unit 46 is designed to determine the desired operating mode for DAC 30 by computing a ratio of MCLK (or a rate derived from MCLK) to LRCK and then validating a supported clock configuration based on this MCLK/LRCK ratio. FIG. 4 is a high-level diagram of one embodiment of autodetect unit 46 which includes a divider 60 and a clock rate ratio sequencer 62. Divider 60 receives MCLK from the external clock source 56 and outputs two derived signals MCLK1 and MCLK2. These derived signals may be the same rate as MCLK or may be a different (lower) rate based on a comparison that is performed against two internal threshold frequencies. These threshold or trip frequencies are selected according to the particular set of MCLK rates that are to be supported by DAC 30. In the illustrative embodiment, trip frequencies (“F₁” and “F₂”) of 16 MHz (F₁) and 24 MHz (F₂) are used based on the following set of supported master clock rates (all in MHz):

• • [0035] 8.1920
  • [0036] 11.2896
  • [0037] 12.2880
  • [0038] 16.9344
  • [0039] 18.4320
  • [0040] 22.5792
  • [0041] 24.5760
  • [0042] 32.7680
  • [0043] 33.8680
  • [0044] 36.8640
  • [0045] 45.1580
  • [0046] 49.1520

[0047] The selection of particular trip frequencies also reflects potential variations in on-chip signal rates. A trip frequency may fluctuate by as much as ±20% due to process and temperature variations. A sufficient spread therefore exists between the two trip frequencies to ensure that a given MCLK input is properly detected. For example, an MCLK signal of 18 MHz may or may not evaluate to “high” as compared to a nominal trip frequency of 16 MHz since the actual trip frequency might be as high as 20 MHz. However, the 18 MHz signal will always evaluate to “low” as compared to the second trip frequency of 24 MHz. The use of two trip frequencies thus resolves potential ambiguities relating to clocking inaccuracies.

[0048] If MCLK is less than F₁, then MCLK1 is the same rate as MCLK. Alternatively, if MCLK is greater than F₁, then MCLK1 is some fraction of MCLK. In this embodiment, MCLK1 would be one-half the rate of MCLK if MCLK is greater than F₁, i.e., the MCLK signal is divided by 2. Similarly, if MCLK is less than F₂, then MCLK2 is the same rate as MCLK or, alternatively, if MCLK is greater than F₂, then MCLK2 is some fraction of MCLK. Again, in this particular embodiment, MCLK2 would be one-half the rate of MCLK if MCLK is greater than F₂. The comparison of MCLK to a trip frequency is done by simply counting the number of MCLK cycles during the trip period.

[0049] The trip frequencies can be provided using internally generated time constants. FIG. 5 depicts one embodiment of a timing circuit 64 that can be used by autodetect unit 36 for this purpose. A first current source I₁ is connected to a capacitor 66 and to the inputs of two comparators 68, 70. A second current source I₂ is connected to a resistive ladder 72 having nodes that are further connected to the other inputs of comparators 68, 70. In this manner, when a switch 74 at capacitor 66 is opened, the common voltage V_C from the first current source ramps up and, as it eventually reaches the voltages V₁ and V₂ set by the second current source, triggers comparators 68 and 70 (at different times since V₁ is greater than V₂). The corresponding output signals T₁ and T₂ have the prescribed trip frequencies F₁ and F₂.

[0050] The derived signals MCLK1 and MCLK2 are used by clock rate ratio sequencer 62 to calculate an LRCK ratio which determines the desired operating mode (base, high or quad mode). While only three modes are used in DAC 30, many different frequency combinations of MCLK and LRCK are supported that fall within one of these three modes. FIG. 6 illustrates how clock rate ratio sequencer 62 selects the appropriate MCLK/LCRK ratio. MCLK1 is provided (unchanged) as a first input to a multiplexer 80. MCLK1 is also divided by 2 to provide another input to multiplexer 80. A third input to multiplexer 80 is derived by dividing MCLK2 by 1.5, and a fourth input is derived by dividing MCLK2 by 2.25 (i.e., taking the previously divided MCLK2 signal and dividing again by 1.5). The particular values that are divided into the MCLK1 and MCLK2 rates are not necessarily limited to 1.5 or 2, but these values are exemplary for the previously listed set of supported master clock rates and corresponding LRCK rates. Additionally, while this implementation uses four inputs to multiplexer 80, an alternative embodiment could have more or less inputs depending upon the supported master clock rate and sample clock rate combinations.

[0051] The output of multiplexer 80 is passed to a divider/counter 82, which calculates a clock ratio using LRCK. The output of divider/counter 82 is fed to a comparator 84, which examines the ratio to see if it is valid, i.e., if it corresponds to one of a plurality of predetermined clock ratios. In the illustrative embodiment, valid MCLK/LRCK ratios are 256, 128 and 64 (these values are approximate and comparator 84 takes into account a small error tolerance of ±3). These values are selected as valid ratios because they correspond to MCLK/LRCK rates used by various conventional devices, according to this implementation. A ratio of 256 indicates that the base mode of operation is to be used. A ratio of 128 indicates that the high mode of operation is to be used, and a ratio of 64 indicates that the quad mode of operation is to be used. The output of comparator 84 is a 3-bit value having an active bit that indicates the desired mode.

[0052] Multiplexer 80 sequences through the inputs in a predetermined manner, starting at the top input as seen in FIG. 6 (MCLK1) and working toward the bottom input (MCLK2/2.25) which ensures that the highest valid ratio will be accepted in case there are multiple valid ratios which might otherwise be calculated. Similarly, comparator 84 first checks for a ratio of 256 from any of the multiplexer inputs. If a ratio of 256 is not found, comparator 84 cycles through the multiplexer inputs a second time searching for a ratio of 128. If a ratio of 128 is not found, then comparator 84 cycles through the multiplexer inputs a third time searching for a ratio of 64. The process stops once any valid ratio is found for the given cycle. If no valid ratio is found (i.e., within the small error range) after sequencing through the multiplexer these three times, then the system resets. The following three examples (which are not to be construed in a limiting sense) illustrate the operation of clock rate ratio sequencer 62.

[0053] MCLK is 18 MHz, LRCK is 48 kHz, and it is assumed that the first trip frequency is close to (or below) its nominal rate of 16 MHz. MCLK will accordingly trip F₁ but not trip F₂. Therefore:

[0054] MCLK1=9 MHz

[0055] MCLK2=18 MHz

[0056] ratio for first mux input=9 MHz/48 kHz=192

[0057] ratio for second mux input=12 MHz/48 kHz=256

[0058] ratio for third mux input=4.5 MHz/48 kHz=96

[0059] ratio for fourth mux input=8 MHz/48 kHz=167

Result: 256 is identified as a valid ratio during the first check cycle, and the base mode of operation is enabled.

[0060] Similar to Example 1, MCLK is 18 MHz and LRCK is 48 kHz, but it is now assumed that the first trip frequency is greatly above its nominal rate (i.e., it is above 18 MHz). MCLK will accordingly not trip either F₁ or F₂. Therefore:

[0061] MCLK1=18 MHz

[0062] MCLK2=18 MHz

[0063] ratio for first mux input=18 MHz/48 kHz=384

[0064] ratio for second mux input=12 MHz/48 kHz=256

[0065] ratio for third mux input=9 MHz/48 kHz=192

[0066] ratio for fourth mux input=8 MHz/48 kHz=167

Result: 256 is still identified as a valid ratio during the first check cycle, and the base mode of operation is enabled.

[0067] MCLK is 18 MHz, LRCK is 192 kHz, and it is again assumed that the first trip frequency is close to (or below) its nominal rate of 16 MHz. MCLK will accordingly trip F₁ but not trip F₂. Therefore:

[0068] MCLK1=9 MHz

[0069] MCLK2=18 MHz

[0070] ratio for first mux input=9 MHz/192 kHz=48

[0071] ratio for second mux input=12 MHz/192 kHz=64

[0072] ratio for third mux input=4.5 MHz/192 kHz=24

[0073] ratio for fourth mux input=8 MHz/192 kHz=43

Result: 64 is identified as a valid ratio during the third check cycle, and the quad mode of operation is enabled.

[0074] The clock autodetect feature of the present invention may be further understood with reference to the flow chart of FIG. 7. The process starts at power up block 90. The autodetect unit waits until both an MCLK and an LRCK are detected at block 92. The MCLK rate is then compared to the first trip frequency at decision block 94. If MCLK is less than or equal to F₁, then MCLK1 is set to MCLK at block 96, but if MCLK is greater than F₁, then MCLK1 is set to MCLK/2 at block 98. The MCLK rate is also compared to the second trip frequency at decision block 100. If MCLK is less than or equal to F₂, then MCLK2 is set to MCLK at block 102, but if MCLK is greater than F₂, then MCLK2 is set to MCLK/2 at block 104. These comparison and setting steps at blocks 94–98 and 100–104 are performed in parallel.

[0075] The ratios of the derived master clock signals to LRCK are then examined. During the first cycle the sequencer searches for any LRCK ratio equal to 256 at decision block 106. If a ratio of 256 is found, then the base operating mode is selected at block 108, and the autodetect process is complete at end block 110. If no ratio of 256 is found, then the sequencer next searches for any LRCK ratio equal to 128 at decision block 112. If a ratio of 128 is found, then the high operating mode is selected at block 114, and the autodetect process is complete at end block 110. If the sequencer fails to find a ratio of either 256 or 128, then the sequencer searches for any LRCK ratio equal to 64 at decision block 116. If a ratio of 64 is found, then the quad operating mode is selected at block 118, and the autodetect process is complete at end block 110.

[0076] If the sequencer never finds a valid ratio after cycling through all the derived MCLK/LRCK ratios, then the system is reset at block 120 and the process begins again at decision block 92. This result might occur due to unusual variations in the clock signal rates, or due to an input clock configuration which is not supported by DAC 30.

[0077] Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined in the appended claims.