Switching frequency jitter having output ripple cancel for power supplies

[0001] 1. Field of the Invention

[0002] The present invention relates to a power supply, and more specifically relates to a control method of a switching mode power supply.

[0003] 2. Description of Related Art

[0004] Power supplies have been used to convert an unregulated power source to a regulated voltage or current. FIG. 1 shows a traditional power supply. The power supply comprises a PWM controller 10 for generating a switching signal V_PWM. The switching signal V_PWM is used for switching a transformer 11 via a transistor 20. The duty cycle of the switching signal V_PWM determines the power delivered from an input of a power source to an output of the power supply. Although the switching technology can reduce the size of the power supply, switching devices generate electric and magnetic interference (EMI) that interferes the power source. An EMI filter 15 equipped at an input of the power supply is utilized to reduce the EMI. However, the EMI filter 15 causes power consumption and increases the cost and the size of the power supply. In recent development, many prior arts have been proposed to reduce the EMI using frequency jitter. For example, “Effects of Switching Frequency Modulation on EMI Performance of a Converter Using Spread Spectrum Approach” by M. Rahkala, T. Suntio, K. Kalliomaki, APEC 2002 (Applied Power Electronics Conference and Exposition, 2002), 17-Annual, IEEE, Volume 1, 10–14, Mar., 2002, Pages: 93–99; “Offline Converter with Integrated Softstart and Frequency Jitter” by Balu Balakirshnan, Alex Djenguerian, U.S. Pat. No. 6,229,366, May 8, 2001; and “Frequency Jittering Control for Varying the Switching Frequency of a Power Supply” by Balu Balakirshnan, Alex Djenguerian, U.S. Pat. No. 6,249,876, Jun. 19, 2001. However, the disadvantage of these prior arts is that the frequency jitter generates an undesirable ripple signal at the output of the power supply. The undesirable ripple signal generated by the frequency jitter could be realized as following description. An output power P_O of the power supply is the product of an output voltage V_O and an output current I_O, which is given by,
P_O=Vo×Io=η×P_IN . . .   (1)

[0005] An input power P_IN of the transformer 11 and a switching current I_P can be respectively expressed by,

[0006] $\begin{array}{c}{P}_{\mathrm{IN}}=\frac{1}{2\times T}\times L_P\times I_P^2\\ I_P=\frac{V_{\mathrm{IN}}}{L_P}\times T_{\mathrm{ON}}\end{array}$
Where η is the efficiency of the transformer 11; V_IN is an input voltage of the transformer 11; L_P is the primary inductance of the transformer 11; T is a switching period of the switching signal V_PWM; T_ON is an on-time of the switching signal V_PWM.
The equation (1) can be rewritten as,

[0007] $\begin{array}{cc}{P}_O=\eta \times \frac{V_{\mathrm{IN}}^2\times T_{\mathrm{ON}}^2}{2\times L_P\times T}& \left(2\right)\end{array}$

[0008] The switching period T varies in response to the frequency jitter. As shown in equation (2), the output power P_O varies whenever the switching period T varies. And therefore the undesirable ripple signal will be generated as the output power P_O varies.

[0009] An object of the present invention is to provide a frequency jitter to reduce the EMI for a power supply, in which the frequency jitter of the present invention will not generate the undesirable ripple signal at the output of the power supply.

[0010] A switching frequency jitter having output ripple cancel for power supplies according to the present invention includes a clock generator for generating a clock signal. A pattern generator generates a pattern code in response to the clock signal. An oscillator produces an oscillation signal to determine a switching frequency of a switching signal in response to the pattern code. An attenuator is connected to a voltage feedback loop for attenuating a feedback signal, in which the feedback signal is utilized to control the pulse width of the switching signal and to control the output power of the power supply. A programmable resistor is connected to the attenuator for programming an attenuation rate of the attenuator in response to the pattern code. The attenuation rate is increased whenever the switching frequency increases. The pulse width of the switching signal is thus reduced, which compensates the decrease of the switching period and keeps the output power and output voltage constant.

[0011] It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.

[0018] FIG. 1 shows a traditional power supply having an EMI filter. A PWM controller 10 modulates the pulse width of a switching signal V_PWM in response to a feedback signal V_FB. The feedback signal V_FB is obtained from an opto-coupler 85. An operational amplifier 80 and a reference voltage V_REF form an error amplifier to drive the opto-coupler 85. Resistors 72, 73 and the error amplifier form a voltage feedback loop to regulate an output voltage V_O of the power supply. A switching current I_P of a transformer 11 is converted into a switching-current signal V_S through a sense resistor 30. The switching-current signal V_S is provided to the PWM controller 10 for the pulse width modulation of the switching signal V_PWM.

[0019] FIG. 2 is a preferred embodiment of a switching frequency jitter having output ripple cancel according to the present invention. A clock generator 400 generates a clock signal CK for determining a jitter frequency. A pattern generator 300 is utilized to generate a pattern code [M_n . . . M₁] in response to the clock signal CK. An oscillator 200 is used for determining the switching frequency of the switching signal V_PWM in response to the pattern code [M_n . . . M₁]. A resistor R_A and a resistor R_B develop an attenuator 500. The resistor R_A is coupled to the voltage feedback loop for attenuating the feedback signal V_FB. A first terminal of the resistor R_A is supplied with the feedback signal V_FB. The feedback signal V_FB is utilized to control the pulse width of the switching signal V_PWM via a PWM control circuit 600. Therefore the output power of the power supply can be controlled. A second terminal of the resistor R_A is connected to a first terminal of the resistor R_B. A second terminal of the resistor R_B is connected to a ground reference level. A voltage V_B outputted from an output of the attenuator 500 is obtained across the resistor R_B. A programmable resistor 100 is connected to the output of the attenuator 500 for programming an attenuation rate of the attenuator 500 in response to the pattern code [M_n . . . M₁]. The attenuation rate is increased whenever the switching frequency increases. The pulse width of the switching signal V_PWM is therefore reduced, which compensates the decrease of the switching period and keeps the output power and the output voltage of the power supply constant.

[0020] The programmable resistor 100 comprises switching-resistor sets connected in parallel, in which the switching-resistor sets are formed by resistors R₁, R₂, . . . ,R_n and switches S₁,S₂, . . . S_n. The switch S₁ and the resistor R₁ are connected in series. The switch S₂ and the resistor R₂ are connected in series. The switch S_n and the resistor R_n are connected in series. The pattern code [M_n . . . M₁] controls switches S₁,S₂, . . . S_n.

[0021] FIG. 3 shows an embodiment of the oscillator 200 according to the present invention. Programmable charge-current sources comprise current sources I₁₁, I₁₂ . . . I_m and switches S₁₁, S₁₂ . . . S_m, in which the current source I₁₁ and the switch S₁₁ connected in series form a first programmable charge-current source. The current source I₁₂ and the switch S₁₂ connected in series form a second programmable charge-current source. The current source I_m and the switch S_m connected in series form a number-m programmable charge-current source. Programmable charge-current sources are connected to each other in parallel. The pattern code [M_n . . . M₁] controls switches S₁₁, S₁₂, . . . S_m. A current source I₁₀ is connected in parallel with programmable charge-current sources, in which a first terminal of the current source I₁₀ is supplied with a supply voltage V_CC. The current source I₁₀ and programmable charge-current sources produce a charge current I_CHG.

[0022] Programmable discharge-current sources comprise current sources I₂₁, I₂₂ . . . , I_k and switches S₂₁, S₂₂ . . . S_k, in which the current source I₂₁ and the switch S₂₁ connected in series form a first programmable discharge-current source. The current source I₂₂ and the switch S₂₂ connected in series form a second programmable discharge-current source. The current source I_k and the switch S_k connected in series form a number-k programmable discharge-current source. The programmable discharge-current sources are connected to each other in parallel. The pattern code [M_n . . . M₁] controls the switches S₂₁, S₂₂, . . . S_k. A current source I₂₀ is connected in parallel with programmable discharge-current sources, in which a second terminal of the current source I₂₀ is connected to the ground reference level. The current source I₂₀ and programmable charge-current sources produce a discharge current I_DCHG.

[0023] A charge switch S₃₁ is connected between a second terminal of the current source I₁₀ and a capacitor C. A discharge switch S₄₁ is connected between the capacitor C and a first terminal of the current source I₂₀. A comparator 210 has a positive input supplied with a threshold voltage V_H. A negative input of the comparator 210 is connected to the capacitor C. A comparator 220 has a negative input supplied with a threshold voltage V_L. The threshold voltage V_H is higher than the threshold voltage V_L. A positive input of the comparator 220 is connected to the capacitor C. A NAND gate 230 outputs an oscillation signal PLS to turn on/off the discharge switch S₄₁. A first input of the NAND gate 230 is driven by an output of the comparator 210. A NAND gate 240 has an output to turn on/off the charge switch S₃₁. Two inputs of the NAND gate 240 are respectively connected to the output of the NAND gate 230 and an output of the comparator 220. The output of the NAND gate 240 is further connected to a second input of the NAND gate 230.

[0024] FIG. 4 shows an embodiment of the pattern generator 300 according to the present invention. A timer 310 generates a binary code [b_n . . . b₀] in response to the clock signal CK. A read-only-memory 320 generate the pattern code [M_n . . . M₁] in response to the binary code [b_n . . . b₀]. The address inputs of the read-only memory 320 are driven by the output of the timer 310.

[0025] As shown in FIG. 5, the PWM control circuit 600 comprises a comparator 610, a D flip-flop 620 and an AND gate 630. The comparator 610 is used to reset the D flip-flop 620. The voltage V_B outputted from the attenuator 500 supplies a positive input of the comparator 610. The switching-current signal V_S supplies a negative input of the comparator 610 A D input of the D flip-flop 620 is pulled high by the supply voltage V_CC. A clock input of the D flip-flop 620 is supplied with the oscillation signal PLS. A first input of the AND gate 630 is also supplied with the oscillation signal PLS. A second input of the AND a gate 630 is connected to an output of the D flip-flop 620. An output of the AND gate 630 generates the switching signal V_PWM.

[0026] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.