Epitaxially grown fin for FinFET

[0001] The present application is a divisional of U.S. application Ser. No. 10/633,499, filed Aug. 5, 2003 now U.S. Pat. No. 6,835,618, the disclosure of which is incorporated by reference herein in its entirety.

[0002] The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).

[0003] Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk metal oxide semiconductor field effect transistor (MOSFET) devices below the 0.1 μm process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.

[0004] Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. A FinFET is a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFETs in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.

[0005] Fins of existing FinFETs are conventionally formed by direct etching of the layer of material that is to form the fin channel. This conventional direct etching can lead to rough fin sidewalls and, possibly, damage to the fin sidewalls. Such roughness and/or damage can negatively impact the performance of the eventual constructed FinFET. Therefore, there exists a need for methods for forming a fin of a FinFET that avoids the use of direct etching.

[0006] Consistent with the present invention, a method of growing a fin of a FinFET is provided that avoids the use of direct etching. An epitaxial growth process may be employed for growing a fin within a trench of a layer of material, such as, for example, an oxide layer. By growing the fin, instead of using an etching process, the resulting fin will have a relatively damage free surface, thereby improving FinFET performance.

[0007] Additional advantages and other features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.

[0008] According to the present invention, the foregoing and other advantages are achieved in part by a method of forming a fin for a FinFET. The method may include defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method may further include growing a second material in the trench to form the fin and removing the layer of first material.

[0009] According to another aspect of the invention, a method of forming a fin for a FinFET may include defining a trench in a first layer comprising a first material, the trench having a width. The method may further include growing a second material in the trench and removing the first layer to form a fin from the second material grown in the trench, where a width of the fin is substantially equal to the width of the trench.

[0010] According to a further aspect of the invention, a method may include forming a first layer comprising a first material over a buried oxide layer and forming a second layer comprising a second material over the first layer. The method may further include defining a trench in the second layer and forming a third material in the trench. The method may also include removing the first layer to form a fin from the third material, forming a third layer comprising a fourth material over exposed portions of the first layer and over the fin, and removing the third layer and portions of the first layer to leave the fin.

[0011] Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.

[0037] The following detailed description of the invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims.

[0038] Consistent with the present invention, a process of growing a fin of a FinFET transistor, that avoids the use of direct etching, is provided. An epitaxial growth process may be employed, consistent with the present invention, for growing a fin within a trench of a layer of material to reduce damage to the vertical surfaces of the fin, as compared to existing etching processes. The grown fin will have a relatively damage free surface, thereby improving the performance of the FinFET in which the fin is employed.

[0039] FIG. 1 illustrates a cross-section of a starting substrate 100 formed in accordance with an exemplary embodiment of the present invention. Substrate 100, consistent with the present invention, may include a silicon on insulator (SOI) structure that includes, for example, a seed layer 105 formed upon, for example, a buried oxide layer 110. Seed layer 105 may, for example, include a thin layer of silicon (Si) material. The thickness of seed layer 105 may range, for example, from about 50 Å to about 150 Å and the thickness of buried oxide layer 110 may range, for example, from about 1000 Å to about 3000 Å.

[0040] As shown in FIGS. 2A and 2B, after forming substrate 100, an oxide layer 205 and photo-resist layer 210 may be formed on substrate 100. Oxide layer 205 may include any type of oxide material, such as, for example, silicon oxide SiO₂. The thickness of oxide layer 205 may range, for example, from about 800 Å to about 2000 Å. Photo-resist layer 210 may include any type of existing photo-resist material employed in conventional photolithography. After formation of oxide layer 205 and photo-resist layer 210, photolithography may be employed to form channel trench 215 and source/drain 220 openings in the photo-resist 210.

[0041] As shown in FIGS. 3A and 3B, a channel trench 305 and source/drain (S/D) trench 310 may be defined by etching oxide layer 205 using the previously prepared channel trench opening 215. Portions of oxide layer 205 that are exposed via channel trench opening 215 and source/drain opening 220 in photo-resist 210 may be etched away using any conventional etching process. During etching, oxide layer 205 may be etched down to seed layer 105.

[0042] As shown in FIG. 4, crystalline material, such as, for example, silicon, may be epitaxially regrown in channel trench 305, from seed layer 105, to produce epitaxial regrowth 405. The crystalline material may be selectively regrown such that no deposition occurs in the oxide surfaces of oxide layer 205. Excess epitaxial regrowth 405, protruding above oxide layer 205 may then be polished off, as shown in FIG. 5, to create a crystalline fin and S/D region 505 filling channel trench 305 and source/drain trench 310.

[0043] As shown in FIG. 6, a slight recess 605 may be etched in fin 505 through, for example, a dry etch process. Recess 605 may be etched to approximately a depth of 100 Å. Since recess 605 may only be etched in the upper surface of fin 505, the sidewall surfaces of fin 505 will not be affected. A spacer 705 may then be formed upon fin 505, as shown in FIG. 7. Spacer 705 may include, for example, a nitride material. Any existing process, such as, for example, a conventional deposition and planarization process may be used for forming spacer 705. Alternatively, the exposed upper surface of fin 505 may be oxidized to a small extent to produce an oxide spacer 705.

[0044] As shown in FIG. 8, the remaining portions of oxide layer 205 may be stripped from fin and S/D 505 using, for example, an existing oxide etching process. A liner 805 may be formed upon spacer 705, the vertical surfaces of fin and S/D 505, and seed layer 105. Liner 805 may include, for example, a thin nitride or oxide layer that may be formed using existing deposition techniques. The thickness of liner 805 may range, for example, from about 50 Å to about 200 Å. As further shown in FIG. 9, after forming liner 805, a portion of liner 805, formed on spacer 705, may be removed 905 using, for example, an existing etching process to expose the upper surface of spacer 705.

[0045] Seed layer 105 may be etched away, as shown in FIG. 10, using spacer 705 and liner 805 as a mask (e.g., a nitride mask). Seed layer 105 may also be laterally over-etched 1005 to expose a bottom portion of fin and S/D 505. As shown in FIG. 11, spacer 705 and liner 805 may then be stripped away (e.g., using a nitride strip) such that only fin and S/D 505 remain. Fin and S/D 505 may, thus, consistent with the present invention, be formed without damage (e.g., plasma damage) to the fin sidewalls as occurs with conventional fin etching processes. FinFETs constructed using fin and S/D 505 may, therefore, have improved performance relative to FinFETs constructed with conventionally etched fins.

[0046] In another exemplary embodiment of the present invention, the source and drain regions of a FinFET may be amorphized through the implantation of dopants in the source/drain (S/D) regions. To amorphize the source and drain regions, defects may be introduced in the S/D regions, and then dopants may be implanted. The S/D regions may include, for example, Si or Ge, and the dopants may include Xe⁺, Ar⁺, Kr⁺, Ge⁺, Si⁺ or the like. A high temperature anneal of the dopants may increase diffusion, whereas a lower temperature anneal may increase activation of the dopants. The amorphized S/D regions result in more heavily and uniformly doped S/D regions that, in turn, reduce S/D resistance and enhance FinFET currents.

[0047] FIGS. 12–22 illustrate an exemplary strained fin formed via epitaxial growth consistent with another embodiment of the present invention. FIG. 12 illustrates a cross-section of a starting substrate 1200 formed in accordance with an exemplary embodiment of the present invention. Substrate 1200, consistent with the present invention, may include a silicon on insulator (SOI) structure that includes, for example, a seed layer 1205 formed upon, for example, a buried oxide layer 1210. Seed layer 1205 may, for example, include a thin layer of silicon (Si) material. The thickness of seed layer 1205 may range, for example, from about 50 Å to about 150 Å and the thickness of buried oxide layer 1210 may range, for example, from about 1000 Å to about 3000 Å.

[0048] As shown in FIGS. 13A and 13B, after forming substrate 1200, an oxide layer 1305 and photo-resist layer 1310 may be formed on substrate 120. Oxide layer 1305 may include any type of oxide material, such as, for example, silicon oxide SiO₂. The thickness of oxide layer 1305 may range, for example, from about 800 Å to about 2000 Å. Photo-resist layer 1310 may include any type of existing photo-resist material employed in conventional photolithography. After formation of oxide layer 1305 and photo-resist layer 1310, photolithography may be employed to form channel trench 1315 and source/drain 1320 openings in the photo-resist 1310.

[0049] As shown in FIGS. 14A and 14B, a channel trench 1405 and source/drain (S/D) trench 1410 may be defined by etching oxide layer 1305 using the previously prepared channel trench opening 1315. Portions of oxide layer 1305 that are exposed via channel trench opening 1315 and source/drain opening 1320 in photo-resist 1310 may be etched away using any conventional etching process. During etching, oxide layer 1305 may be etched down to seed layer 1305.

[0050] As shown in FIG. 15, crystalline material, such as, for example, silicon Germanium (SiGe) 1505, may be epitaxially regrown in channel trench 1405, from seed layer 1205, to produce epitaxial regrowth 1510. As SiGe 1505 is grown in channel trench 1405, the SiGe may be gradually graded to strained Si 1515. The crystalline material may be selectively regrown such that no deposition occurs in the oxide surfaces of oxide layer 1305. Excess epitaxial regrowth, protruding above oxide layer 1305 may then be polished off, as shown in FIG. 16, to create a crystalline fin and S/D region 1605 filling channel trench 1405 and source/drain trench 1410, where fin and S/D region 1605 include SiGe 1505 graded to strained Si 1515.

[0051] As shown in FIG. 17, a slight recess 1705 may be etched in fin 1605 through, for example, a dry etch process. Recess 1705 may be etched to approximately a depth of 100 Å. Since recess 1705 may only be etched in the upper surface of fin 1605, the sidewall surfaces of fin 1605 will not be affected. A spacer 1805 may then be formed upon fin 1605, as shown in FIG. 18. Spacer 1805 may include, for example, a nitride material. Any existing process, such as, for example, a conventional deposition and planarization process may be used for forming spacer 1805. Alternatively, the exposed upper surface of fin 1605 may be oxidized to a small extent to produce an oxide spacer 1805.

[0052] As shown in FIG. 19, the remaining portions of oxide layer 1305 may be stripped from fin and S/D 1605 using, for example, an existing oxide etching process. A liner 1905 may be formed upon spacer 1805, the vertical surfaces of fin and S/D 1605, and seed layer 1205. Liner 1905 may include, for example, a thin nitride or oxide layer that may be formed using existing deposition techniques. The thickness of liner 1905 may range, for example, from about 50 Å to about 200 Å. As further shown in FIG. 20, after forming liner 1905, a portion of liner 1905, formed on spacer 1805, may be removed 2005 using, for example, an existing etching process to expose the upper surface of spacer 1805.

[0053] Seed layer 1205 may be etched away, as shown in FIG. 21, using spacer 1805 and liner 1905 as a mask (e.g., a nitride mask). Seed layer 125 may also be laterally over-etched 2105 to expose a bottom portion of fin and S/D 1605. As shown in FIG. 22, spacer 1805 and liner 1905 may then be stripped away (e.g., using a nitride strip) such that only fin and S/D 1605, including SiGe 1505 graded to strained Si 1515, remain. Fin and S/D 1605 may, thus, consistent with the present invention, be formed without damage (e.g., plasma damage) to the fin sidewalls as occurs with conventional fin etching processes. Creation of the strained Si 1515 in fin 1605 improves the carrier mobility of FinFET devices.

[0054] In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, the present invention can be practiced without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention. In practicing the present invention, conventional photolithographic and etching techniques may be employed, and hence, the details of such techniques have not been set forth herein in detail.

[0055] Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein.